x86: templatize VNNI templates

Reduce redundancy, in preparation of the addition of further counterparts
for AVX10.2.

2 files changed, 37 insertions, 46 deletions

diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 1d5b8d9..c2ee1ac 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -3061,48 +3061,39 @@ vpshrdw, 0x6672, AVX512_VBMI2, Modrm|Masking|Space0F3A|Src1VVVV|VexW1|Disp8Shift
 
 // AVX512_VBMI2 instructions end
 
-// AVX512_VNNI instructions
+<sat:opc, $:0, s:1>
 
-vpdpbusd, 0x6650, AVX512_VNNI, Modrm|Masking|Space0F38|Src1VVVV|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
-vpdpwssd, 0x6652, AVX512_VNNI, Modrm|Masking|Space0F38|Src1VVVV|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
+// {AVX512,AVX}_VNNI instructions
 
-vpdpbusds, 0x6651, AVX512_VNNI, Modrm|Masking|Space0F38|Src1VVVV|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
-vpdpwssds, 0x6653, AVX512_VNNI, Modrm|Masking|Space0F38|Src1VVVV|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
+<vnni:avx:attr:reg:mem, $z:AVX512:Masking|Broadcast|Disp8ShiftVL:RegZMM:Dword, $y:AVX:Vex::>
 
-// AVX512_VNNI instructions end
+vpdpbusd<vnni><sat>, 0x6650|<sat:opc>, <vnni:avx>_VNNI, Modrm|Space0F38|Src1VVVV|VexW0|<vnni:attr>|CheckOperandSize|NoSuf, { RegXMM|RegYMM|<vnni:reg>|<vnni:mem>|Unspecified|BaseIndex, RegXMM|RegYMM|<vnni:reg>, RegXMM|RegYMM|<vnni:reg> }
+vpdpwssd<vnni><sat>, 0x6652|<sat:opc>, <vnni:avx>_VNNI, Modrm|Space0F38|Src1VVVV|VexW0|<vnni:attr>|CheckOperandSize|NoSuf, { RegXMM|RegYMM|<vnni:reg>|<vnni:mem>|Unspecified|BaseIndex, RegXMM|RegYMM|<vnni:reg>, RegXMM|RegYMM|<vnni:reg> }
 
-// AVX_VNNI instructions
+<vnni>
 
-vpdpbusd, 0x6650, AVX_VNNI, Modrm|Vex|Space0F38|Src1VVVV|VexW0|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vpdpwssd, 0x6652, AVX_VNNI, Modrm|Vex|Space0F38|Src1VVVV|VexW0|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-
-vpdpbusds, 0x6651, AVX_VNNI, Modrm|Vex|Space0F38|Src1VVVV|VexW0|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vpdpwssds, 0x6653, AVX_VNNI, Modrm|Vex|Space0F38|Src1VVVV|VexW0|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-
-// AVX_VNNI instructions end
+// {AVX512,AVX}_VNNI instructions end
 
 // AVX-VNNI-INT8 instructions.
 
-vpdpbuud, 0x50, AVX_VNNI_INT8, Modrm|Vex|Space0F38|Src1VVVV|VexW0|CheckOperandSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
-vpdpbuuds, 0x51, AVX_VNNI_INT8, Modrm|Vex|Space0F38|Src1VVVV|VexW0|CheckOperandSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
-vpdpbssd, 0xf250, AVX_VNNI_INT8, Modrm|Vex|Space0F38|Src1VVVV|VexW0|CheckOperandSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
-vpdpbssds, 0xf251, AVX_VNNI_INT8, Modrm|Vex|Space0F38|Src1VVVV|VexW0|CheckOperandSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
-vpdpbsud, 0xf350, AVX_VNNI_INT8, Modrm|Vex|Space0F38|Src1VVVV|VexW0|CheckOperandSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
-vpdpbsuds, 0xf351, AVX_VNNI_INT8, Modrm|Vex|Space0F38|Src1VVVV|VexW0|CheckOperandSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
+<dpb:pfx, uu:, ss:f2, su:f3>
+
+vpdpb<dpb>d<sat>, 0x<dpb:pfx>50|<sat:opc>, AVX_VNNI_INT8, Modrm|Vex|Space0F38|Src1VVVV|VexW0|CheckOperandSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
 
 // AVX-VNNI-INT8 instructions end.
 
 // AVX-VNNI-INT16 instructions.
 
-vpdpwuud, 0xd2, AVX_VNNI_INT16, Modrm|Vex|Space0F38|Src1VVVV|VexW0|CheckOperandSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
-vpdpwuuds, 0xd3, AVX_VNNI_INT16, Modrm|Vex|Space0F38|Src1VVVV|VexW0|CheckOperandSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
-vpdpwusd, 0x66d2, AVX_VNNI_INT16, Modrm|Vex|Space0F38|Src1VVVV|VexW0|CheckOperandSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
-vpdpwusds, 0x66d3, AVX_VNNI_INT16, Modrm|Vex|Space0F38|Src1VVVV|VexW0|CheckOperandSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
-vpdpwsud, 0xf3d2, AVX_VNNI_INT16, Modrm|Vex|Space0F38|Src1VVVV|VexW0|CheckOperandSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
-vpdpwsuds, 0xf3d3, AVX_VNNI_INT16, Modrm|Vex|Space0F38|Src1VVVV|VexW0|CheckOperandSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
+<dpw:pfx, uu:, us:66, su:f3>
+
+vpdpw<dpw>d<sat>, 0x<dpw:pfx>d2|<sat:opc>, AVX_VNNI_INT16, Modrm|Vex|Space0F38|Src1VVVV|VexW0|CheckOperandSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
 
 // AVX-VNNI-INT16 instructions end.
 
+<dpw>
+<dpb>
+<sat>
+
 // AVX512_BITALG instructions
 
 vpopcnt<bw>, 0x6654, AVX512_BITALG, Modrm|Masking|Space0F38|<bw:vexw>|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index b5307e3..60705c3 100644
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -42018,7 +42018,7 @@ static const insn_template i386_optab[] =
 	  1, 1, 1, 0, 0, 0 } },
       { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 	  1, 1, 1, 0, 0, 0 } } } },
-  { MN_vpdpbusd, 0x50, 3, SPACE_0F38, None,
+  { MN_vpdpbusd, 0x50|0, 3, SPACE_0F38, None,
     { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
       0, 0, 0, 0, 1, 1, 1, 0, 0, 5, 1, 3, 0, 0, 7, 0, 0, 0, 0, 0,
       0, 0 },
@@ -42030,7 +42030,7 @@ static const insn_template i386_optab[] =
 	  1, 1, 1, 0, 0, 0 } },
       { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 	  1, 1, 1, 0, 0, 0 } } } },
-  { MN_vpdpbusd, 0x50, 3, SPACE_0F38, None,
+  { MN_vpdpbusd, 0x50|0, 3, SPACE_0F38, None,
     { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
       0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
       0, 0 },
@@ -42042,7 +42042,7 @@ static const insn_template i386_optab[] =
 	  1, 1, 0, 0, 0, 0 } },
       { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 	  1, 1, 0, 0, 0, 0 } } } },
-  { MN_vpdpwssd, 0x52, 3, SPACE_0F38, None,
+  { MN_vpdpbusds, 0x50|1, 3, SPACE_0F38, None,
     { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
       0, 0, 0, 0, 1, 1, 1, 0, 0, 5, 1, 3, 0, 0, 7, 0, 0, 0, 0, 0,
       0, 0 },
@@ -42054,7 +42054,7 @@ static const insn_template i386_optab[] =
 	  1, 1, 1, 0, 0, 0 } },
       { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 	  1, 1, 1, 0, 0, 0 } } } },
-  { MN_vpdpwssd, 0x52, 3, SPACE_0F38, None,
+  { MN_vpdpbusds, 0x50|1, 3, SPACE_0F38, None,
     { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
       0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
       0, 0 },
@@ -42066,7 +42066,7 @@ static const insn_template i386_optab[] =
 	  1, 1, 0, 0, 0, 0 } },
       { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 	  1, 1, 0, 0, 0, 0 } } } },
-  { MN_vpdpbusds, 0x51, 3, SPACE_0F38, None,
+  { MN_vpdpwssd, 0x52|0, 3, SPACE_0F38, None,
     { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
       0, 0, 0, 0, 1, 1, 1, 0, 0, 5, 1, 3, 0, 0, 7, 0, 0, 0, 0, 0,
       0, 0 },
@@ -42078,7 +42078,7 @@ static const insn_template i386_optab[] =
 	  1, 1, 1, 0, 0, 0 } },
       { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 	  1, 1, 1, 0, 0, 0 } } } },
-  { MN_vpdpbusds, 0x51, 3, SPACE_0F38, None,
+  { MN_vpdpwssd, 0x52|0, 3, SPACE_0F38, None,
     { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
       0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
       0, 0 },
@@ -42090,7 +42090,7 @@ static const insn_template i386_optab[] =
 	  1, 1, 0, 0, 0, 0 } },
       { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 	  1, 1, 0, 0, 0, 0 } } } },
-  { MN_vpdpwssds, 0x53, 3, SPACE_0F38, None,
+  { MN_vpdpwssds, 0x52|1, 3, SPACE_0F38, None,
     { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
       0, 0, 0, 0, 1, 1, 1, 0, 0, 5, 1, 3, 0, 0, 7, 0, 0, 0, 0, 0,
       0, 0 },
@@ -42102,7 +42102,7 @@ static const insn_template i386_optab[] =
 	  1, 1, 1, 0, 0, 0 } },
       { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 	  1, 1, 1, 0, 0, 0 } } } },
-  { MN_vpdpwssds, 0x53, 3, SPACE_0F38, None,
+  { MN_vpdpwssds, 0x52|1, 3, SPACE_0F38, None,
     { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
       0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
       0, 0 },
@@ -42114,7 +42114,7 @@ static const insn_template i386_optab[] =
 	  1, 1, 0, 0, 0, 0 } },
       { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 	  1, 1, 0, 0, 0, 0 } } } },
-  { MN_vpdpbuud, 0x50, 3, SPACE_0F38, None,
+  { MN_vpdpbuud, 0x50|0, 3, SPACE_0F38, None,
     { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
       0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
       0, 0 },
@@ -42126,7 +42126,7 @@ static const insn_template i386_optab[] =
 	  1, 1, 0, 0, 0, 0 } },
       { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 	  1, 1, 0, 0, 0, 0 } } } },
-  { MN_vpdpbuuds, 0x51, 3, SPACE_0F38, None,
+  { MN_vpdpbuuds, 0x50|1, 3, SPACE_0F38, None,
     { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
       0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
       0, 0 },
@@ -42138,7 +42138,7 @@ static const insn_template i386_optab[] =
 	  1, 1, 0, 0, 0, 0 } },
       { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 	  1, 1, 0, 0, 0, 0 } } } },
-  { MN_vpdpbssd, 0x50, 3, SPACE_0F38, None,
+  { MN_vpdpbssd, 0x50|0, 3, SPACE_0F38, None,
     { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
       0, 0, 0, 1, 1, 1, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
       0, 0 },
@@ -42150,7 +42150,7 @@ static const insn_template i386_optab[] =
 	  1, 1, 0, 0, 0, 0 } },
       { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 	  1, 1, 0, 0, 0, 0 } } } },
-  { MN_vpdpbssds, 0x51, 3, SPACE_0F38, None,
+  { MN_vpdpbssds, 0x50|1, 3, SPACE_0F38, None,
     { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
       0, 0, 0, 1, 1, 1, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
       0, 0 },
@@ -42162,7 +42162,7 @@ static const insn_template i386_optab[] =
 	  1, 1, 0, 0, 0, 0 } },
       { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 	  1, 1, 0, 0, 0, 0 } } } },
-  { MN_vpdpbsud, 0x50, 3, SPACE_0F38, None,
+  { MN_vpdpbsud, 0x50|0, 3, SPACE_0F38, None,
     { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
       0, 0, 0, 1, 1, 1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
       0, 0 },
@@ -42174,7 +42174,7 @@ static const insn_template i386_optab[] =
 	  1, 1, 0, 0, 0, 0 } },
       { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 	  1, 1, 0, 0, 0, 0 } } } },
-  { MN_vpdpbsuds, 0x51, 3, SPACE_0F38, None,
+  { MN_vpdpbsuds, 0x50|1, 3, SPACE_0F38, None,
     { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
       0, 0, 0, 1, 1, 1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
       0, 0 },
@@ -42186,7 +42186,7 @@ static const insn_template i386_optab[] =
 	  1, 1, 0, 0, 0, 0 } },
       { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 	  1, 1, 0, 0, 0, 0 } } } },
-  { MN_vpdpwuud, 0xd2, 3, SPACE_0F38, None,
+  { MN_vpdpwuud, 0xd2|0, 3, SPACE_0F38, None,
     { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
       0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
       0, 0 },
@@ -42198,7 +42198,7 @@ static const insn_template i386_optab[] =
 	  1, 1, 0, 0, 0, 0 } },
       { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 	  1, 1, 0, 0, 0, 0 } } } },
-  { MN_vpdpwuuds, 0xd3, 3, SPACE_0F38, None,
+  { MN_vpdpwuuds, 0xd2|1, 3, SPACE_0F38, None,
     { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
       0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
       0, 0 },
@@ -42210,7 +42210,7 @@ static const insn_template i386_optab[] =
 	  1, 1, 0, 0, 0, 0 } },
       { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 	  1, 1, 0, 0, 0, 0 } } } },
-  { MN_vpdpwusd, 0xd2, 3, SPACE_0F38, None,
+  { MN_vpdpwusd, 0xd2|0, 3, SPACE_0F38, None,
     { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
       0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
       0, 0 },
@@ -42222,7 +42222,7 @@ static const insn_template i386_optab[] =
 	  1, 1, 0, 0, 0, 0 } },
       { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 	  1, 1, 0, 0, 0, 0 } } } },
-  { MN_vpdpwusds, 0xd3, 3, SPACE_0F38, None,
+  { MN_vpdpwusds, 0xd2|1, 3, SPACE_0F38, None,
     { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
       0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
       0, 0 },
@@ -42234,7 +42234,7 @@ static const insn_template i386_optab[] =
 	  1, 1, 0, 0, 0, 0 } },
       { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 	  1, 1, 0, 0, 0, 0 } } } },
-  { MN_vpdpwsud, 0xd2, 3, SPACE_0F38, None,
+  { MN_vpdpwsud, 0xd2|0, 3, SPACE_0F38, None,
     { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
       0, 0, 0, 1, 1, 1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
       0, 0 },
@@ -42246,7 +42246,7 @@ static const insn_template i386_optab[] =
 	  1, 1, 0, 0, 0, 0 } },
       { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 	  1, 1, 0, 0, 0, 0 } } } },
-  { MN_vpdpwsuds, 0xd3, 3, SPACE_0F38, None,
+  { MN_vpdpwsuds, 0xd2|1, 3, SPACE_0F38, None,
     { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
       0, 0, 0, 1, 1, 1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
       0, 0 },