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| author | Richard Sandiford <richard.sandiford@arm.com> | 2021-11-30 17:50:25 +0000 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2021-11-30 17:50:25 +0000 |
| commit | ed96bdcba59ec5bba01de1b1db398f338f9200b1 (patch) | |
| tree | 3aa29e4f6223f8e6d35b9cff98bc5a1a42e5b5aa | |
| parent | b009f915c9e744b1671f72806c5714af00a8ee89 (diff) | |
| download | gdb-ed96bdcba59ec5bba01de1b1db398f338f9200b1.zip gdb-ed96bdcba59ec5bba01de1b1db398f338f9200b1.tar.gz gdb-ed96bdcba59ec5bba01de1b1db398f338f9200b1.tar.bz2 | |
aarch64: Remove ZIDR_EL1
ZIDR_EL1 was part of an early version of SVE, but didn't make
it to the final release.
opcodes/
* aarch64-opc.c (aarch64_sys_regs): Remove zidr_el1 entry.
gas/
* testsuite/gas/aarch64/sve-sysreg.s: Remove zidr_el1.
* testsuite/gas/aarch64/sve-sysreg.d: Update accordingly.
* testsuite/gas/aarch64/sve-sysreg-invalid.l: Likewise.
| -rw-r--r-- | gas/testsuite/gas/aarch64/sve-sysreg-invalid.l | 2 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/sve-sysreg.d | 2 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/sve-sysreg.s | 3 | ||||
| -rw-r--r-- | opcodes/aarch64-opc.c | 1 |
4 files changed, 0 insertions, 8 deletions
diff --git a/gas/testsuite/gas/aarch64/sve-sysreg-invalid.l b/gas/testsuite/gas/aarch64/sve-sysreg-invalid.l index b68c41d..0eaefe1 100644 --- a/gas/testsuite/gas/aarch64/sve-sysreg-invalid.l +++ b/gas/testsuite/gas/aarch64/sve-sysreg-invalid.l @@ -17,5 +17,3 @@ .*:20: Error: selected processor does not support system register name 'zcr_el3' .*:21: Error: selected processor does not support system register name 'zcr_el3' .*:22: Error: selected processor does not support system register name 'zcr_el3' -.*:24: Error: selected processor does not support system register name 'zidr_el1' -.*:25: Error: selected processor does not support system register name 'zidr_el1' diff --git a/gas/testsuite/gas/aarch64/sve-sysreg.d b/gas/testsuite/gas/aarch64/sve-sysreg.d index 24ab421..22d9e5ac 100644 --- a/gas/testsuite/gas/aarch64/sve-sysreg.d +++ b/gas/testsuite/gas/aarch64/sve-sysreg.d @@ -25,5 +25,3 @@ Disassembly of section .*: .*: d53e121b mrs x27, zcr_el3 .*: d51e1200 msr zcr_el3, x0 .*: d51e121a msr zcr_el3, x26 -.*: d53800e0 mrs x0, zidr_el1 -.*: d53800fb mrs x27, zidr_el1 diff --git a/gas/testsuite/gas/aarch64/sve-sysreg.s b/gas/testsuite/gas/aarch64/sve-sysreg.s index a38ad7f..90e0951 100644 --- a/gas/testsuite/gas/aarch64/sve-sysreg.s +++ b/gas/testsuite/gas/aarch64/sve-sysreg.s @@ -20,6 +20,3 @@ mrs X27, zcr_el3 msr ZCR_EL3, X0 msr zcr_el3, x26 - - mrs x0, ZIDR_EL1 - mrs X27, zidr_el1 diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 34b141e..ace7032 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -4119,7 +4119,6 @@ const aarch64_sys_reg aarch64_sys_regs [] = SR_SVE ("zcr_el12", CPENC (3,5,C1,C2,0), 0), SR_SVE ("zcr_el2", CPENC (3,4,C1,C2,0), 0), SR_SVE ("zcr_el3", CPENC (3,6,C1,C2,0), 0), - SR_SVE ("zidr_el1", CPENC (3,0,C0,C0,7), 0), SR_CORE ("ttbr0_el1", CPENC (3,0,C2,C0,0), 0), SR_CORE ("ttbr1_el1", CPENC (3,0,C2,C0,1), 0), SR_V8_A ("ttbr0_el2", CPENC (3,4,C2,C0,0), 0), |