x86: CET v2.0: Rename savessp to saveprevssp

Replace savessp with saveprevssp for CET v2.0:

https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf

gas/

	* testsuite/gas/i386/cet-intel.d: Updated.
	* testsuite/gas/i386/cet.d: Likewise.
	* testsuite/gas/i386/x86-64-cet-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-cet.d: Likewise.
	* testsuite/gas/i386/cet.s: Replace savessp with saveprevssp.
	* testsuite/gas/i386/x86-64-cet.s: Likewise.

opcodes/

	* i386-dis.c (prefix_table): Replace savessp with saveprevssp.
	* i386-opc.tbl: Likewise.
	* i386-tbl.h: Regenerated.

11 files changed, 30 insertions, 15 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index ed35a21..855401d 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,14 @@
 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 
+	* testsuite/gas/i386/cet-intel.d: Updated.
+	* testsuite/gas/i386/cet.d: Likewise.
+	* testsuite/gas/i386/x86-64-cet-intel.d: Likewise.
+	* testsuite/gas/i386/x86-64-cet.d: Likewise.
+	* testsuite/gas/i386/cet.s: Replace savessp with saveprevssp.
+	* testsuite/gas/i386/x86-64-cet.s: Likewise.
+
+2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
+
 	* config/tc-i386.c (md_assemble): Update NOTRACK prefix check.
 	* testsuite/gas/i386/notrack-intel.d: Updated.
 	* testsuite/gas/i386/notrack.d: Likewise.
diff --git a/gas/testsuite/gas/i386/cet-intel.d b/gas/testsuite/gas/i386/cet-intel.d
index a5f5533..c16a963 100644
--- a/gas/testsuite/gas/i386/cet-intel.d
+++ b/gas/testsuite/gas/i386/cet-intel.d
@@ -10,7 +10,7 @@ Disassembly of section .text:
 0+ <_start>:
  +[a-f0-9]+:	f3 0f 01 e9          	incsspd 
  +[a-f0-9]+:	f3 0f 1e c9          	rdsspd ecx
- +[a-f0-9]+:	f3 0f 01 ea          	savessp 
+ +[a-f0-9]+:	f3 0f 01 ea          	saveprevssp 
  +[a-f0-9]+:	f3 0f 01 29          	rstorssp QWORD PTR \[ecx\]
  +[a-f0-9]+:	0f 38 f6 04 02       	wrssd  \[edx\+eax\*1\],eax
  +[a-f0-9]+:	66 0f 38 f5 14 2f    	wrussd \[edi\+ebp\*1\],edx
@@ -20,7 +20,7 @@ Disassembly of section .text:
  +[a-f0-9]+:	f3 0f 1e fb          	endbr32 
  +[a-f0-9]+:	f3 0f 01 e9          	incsspd 
  +[a-f0-9]+:	f3 0f 1e c9          	rdsspd ecx
- +[a-f0-9]+:	f3 0f 01 ea          	savessp 
+ +[a-f0-9]+:	f3 0f 01 ea          	saveprevssp 
  +[a-f0-9]+:	f3 0f 01 2c 01       	rstorssp QWORD PTR \[ecx\+eax\*1\]
  +[a-f0-9]+:	0f 38 f6 02          	wrssd  \[edx\],eax
  +[a-f0-9]+:	66 0f 38 f5 14 2f    	wrussd \[edi\+ebp\*1\],edx
diff --git a/gas/testsuite/gas/i386/cet.d b/gas/testsuite/gas/i386/cet.d
index bb356e4..449f04e 100644
--- a/gas/testsuite/gas/i386/cet.d
+++ b/gas/testsuite/gas/i386/cet.d
@@ -8,7 +8,7 @@ Disassembly of section .text:
 0+ <_start>:
  +[a-f0-9]+:	f3 0f 01 e9          	incsspd 
  +[a-f0-9]+:	f3 0f 1e c9          	rdsspd %ecx
- +[a-f0-9]+:	f3 0f 01 ea          	savessp 
+ +[a-f0-9]+:	f3 0f 01 ea          	saveprevssp 
  +[a-f0-9]+:	f3 0f 01 29          	rstorssp \(%ecx\)
  +[a-f0-9]+:	0f 38 f6 04 02       	wrssd  %eax,\(%edx,%eax,1\)
  +[a-f0-9]+:	66 0f 38 f5 14 2f    	wrussd %edx,\(%edi,%ebp,1\)
@@ -18,7 +18,7 @@ Disassembly of section .text:
  +[a-f0-9]+:	f3 0f 1e fb          	endbr32 
  +[a-f0-9]+:	f3 0f 01 e9          	incsspd 
  +[a-f0-9]+:	f3 0f 1e c9          	rdsspd %ecx
- +[a-f0-9]+:	f3 0f 01 ea          	savessp 
+ +[a-f0-9]+:	f3 0f 01 ea          	saveprevssp 
  +[a-f0-9]+:	f3 0f 01 2c 01       	rstorssp \(%ecx,%eax,1\)
  +[a-f0-9]+:	0f 38 f6 02          	wrssd  %eax,\(%edx\)
  +[a-f0-9]+:	66 0f 38 f5 14 2f    	wrussd %edx,\(%edi,%ebp,1\)
diff --git a/gas/testsuite/gas/i386/cet.s b/gas/testsuite/gas/i386/cet.s
index deb659d..f0b6db0 100644
--- a/gas/testsuite/gas/i386/cet.s
+++ b/gas/testsuite/gas/i386/cet.s
@@ -3,7 +3,7 @@
 _start:
 	incsspd
 	rdsspd %ecx
-	savessp
+	saveprevssp
 	rstorssp (%ecx)
 	wrssd %eax, (%edx, %eax)
 	wrussd %edx, (%edi, %ebp)
@@ -15,7 +15,7 @@ _start:
 	.intel_syntax noprefix
 	incsspd
 	rdsspd ecx
-	savessp
+	saveprevssp
 	rstorssp QWORD PTR [ecx + eax]
 	wrssd [edx],eax
 	wrussd [edi + ebp],edx
diff --git a/gas/testsuite/gas/i386/x86-64-cet-intel.d b/gas/testsuite/gas/i386/x86-64-cet-intel.d
index 07e666f..2d2af71 100644
--- a/gas/testsuite/gas/i386/x86-64-cet-intel.d
+++ b/gas/testsuite/gas/i386/x86-64-cet-intel.d
@@ -11,7 +11,7 @@ Disassembly of section .text:
  +[a-f0-9]+:	f3 48 0f 01 e9       	incsspq 
  +[a-f0-9]+:	f3 41 0f 1e cc       	rdsspd r12d
  +[a-f0-9]+:	f3 48 0f 1e c8       	rdsspq rax
- +[a-f0-9]+:	f3 0f 01 ea          	savessp 
+ +[a-f0-9]+:	f3 0f 01 ea          	saveprevssp 
  +[a-f0-9]+:	f3 41 0f 01 2c 24    	rstorssp QWORD PTR \[r12\]
  +[a-f0-9]+:	41 0f 38 f6 04 24    	wrssd  \[r12\],eax
  +[a-f0-9]+:	4a 0f 38 f6 14 39    	wrssq  \[rcx\+r15\*1\],rdx
@@ -25,7 +25,7 @@ Disassembly of section .text:
  +[a-f0-9]+:	f3 48 0f 01 e9       	incsspq 
  +[a-f0-9]+:	f3 41 0f 1e cc       	rdsspd r12d
  +[a-f0-9]+:	f3 48 0f 1e c8       	rdsspq rax
- +[a-f0-9]+:	f3 0f 01 ea          	savessp 
+ +[a-f0-9]+:	f3 0f 01 ea          	saveprevssp 
  +[a-f0-9]+:	f3 41 0f 01 2c 24    	rstorssp QWORD PTR \[r12\]
  +[a-f0-9]+:	41 0f 38 f6 04 24    	wrssd  \[r12\],eax
  +[a-f0-9]+:	4a 0f 38 f6 14 39    	wrssq  \[rcx\+r15\*1\],rdx
diff --git a/gas/testsuite/gas/i386/x86-64-cet.d b/gas/testsuite/gas/i386/x86-64-cet.d
index 7e5b717..6981e9f 100644
--- a/gas/testsuite/gas/i386/x86-64-cet.d
+++ b/gas/testsuite/gas/i386/x86-64-cet.d
@@ -10,7 +10,7 @@ Disassembly of section .text:
  +[a-f0-9]+:	f3 48 0f 01 e9       	incsspq 
  +[a-f0-9]+:	f3 41 0f 1e cc       	rdsspd %r12d
  +[a-f0-9]+:	f3 48 0f 1e c8       	rdsspq %rax
- +[a-f0-9]+:	f3 0f 01 ea          	savessp 
+ +[a-f0-9]+:	f3 0f 01 ea          	saveprevssp 
  +[a-f0-9]+:	f3 41 0f 01 2c 24    	rstorssp \(%r12\)
  +[a-f0-9]+:	41 0f 38 f6 04 24    	wrssd  %eax,\(%r12\)
  +[a-f0-9]+:	4a 0f 38 f6 14 39    	wrssq  %rdx,\(%rcx,%r15,1\)
@@ -24,7 +24,7 @@ Disassembly of section .text:
  +[a-f0-9]+:	f3 48 0f 01 e9       	incsspq 
  +[a-f0-9]+:	f3 41 0f 1e cc       	rdsspd %r12d
  +[a-f0-9]+:	f3 48 0f 1e c8       	rdsspq %rax
- +[a-f0-9]+:	f3 0f 01 ea          	savessp 
+ +[a-f0-9]+:	f3 0f 01 ea          	saveprevssp 
  +[a-f0-9]+:	f3 41 0f 01 2c 24    	rstorssp \(%r12\)
  +[a-f0-9]+:	41 0f 38 f6 04 24    	wrssd  %eax,\(%r12\)
  +[a-f0-9]+:	4a 0f 38 f6 14 39    	wrssq  %rdx,\(%rcx,%r15,1\)
diff --git a/gas/testsuite/gas/i386/x86-64-cet.s b/gas/testsuite/gas/i386/x86-64-cet.s
index 15a28d7..fbed700 100644
--- a/gas/testsuite/gas/i386/x86-64-cet.s
+++ b/gas/testsuite/gas/i386/x86-64-cet.s
@@ -5,7 +5,7 @@ _start:
 	incsspq
 	rdsspd %r12d
 	rdsspq %rax
-	savessp
+	saveprevssp
 	rstorssp (%r12)
 	wrssd %eax, (%r12)
 	wrssq %rdx, (%rcx, %r15)
@@ -21,7 +21,7 @@ _start:
 	incsspq
 	rdsspd r12d
 	rdsspq rax
-	savessp
+	saveprevssp
 	rstorssp QWORD PTR [r12]
 	wrssd [r12],eax
 	wrssq [rcx+r15],rdx
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 671837f..3ffafa1 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,11 @@
 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 
+	* i386-dis.c (prefix_table): Replace savessp with saveprevssp.
+	* i386-opc.tbl: Likewise.
+	* i386-tbl.h: Regenerated.
+
+2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
+
 	* i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
 	and "jmp{&|}".
 	(NOTRACK_Fixup): Support memory indirect branch with NOTRACK
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 2e35e38..58d4c06 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -3798,7 +3798,7 @@ static const struct dis386 prefix_table[][4] = {
   /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
   {
     { Bad_Opcode },
-    { "savessp",	{ Skip_MODRM }, PREFIX_OPCODE },
+    { "saveprevssp",	{ Skip_MODRM }, PREFIX_OPCODE },
   },
 
   /* PREFIX_0F10 */
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 5b1a4fd..47e1f66 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -6013,7 +6013,7 @@ incsspd, 0, 0xf30f01e9, None, 3, CpuCET, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_s
 incsspq, 0, 0xf30f01e9, None, 3, CpuCET|Cpu64, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { 0 }
 rdsspd, 1, 0xf30f1e, 0x1, 2, CpuCET, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32 }
 rdsspq, 1, 0xf30f1e, 0x1, 2, CpuCET|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg64 }
-savessp, 0, 0xf30f01ea, None, 3, CpuCET, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
+saveprevssp, 0, 0xf30f01ea, None, 3, CpuCET, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
 rstorssp, 1, 0xf30f01, 0x5, 2, CpuCET, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
 wrssd, 2, 0x0f38f6, None, 3, CpuCET, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
 wrssq, 2, 0x0f38f6, None, 3, CpuCET|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg64, Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index 1fcd003..4bc3878 100644
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -92045,7 +92045,7 @@ const insn_template i386_optab[] =
     { { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } },
-  { "savessp", 0, 0xf30f01ea, None, 3,
+  { "saveprevssp", 0, 0xf30f01ea, None, 3,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,