x86: Add CheckRegSize to AVX512_BF16 instructions with Disp8ShiftVL

For AVX512 instructions with Disp8ShiftVL and Broadcast, we may need to
add CheckRegSize to check if broadcast matches the destination register
size.

gas/

	PR gas/24625
	* testsuite/gas/i386/inval-avx512f.s: Add tests for AVX512_BF16
	instructions with invalid broadcast.
	* testsuite/gas/i386/x86-64-inval-avx512f.s: Likewise.
	* testsuite/gas/i386/inval-avx512f.l: Updated.
	* testsuite/gas/i386/x86-64-inval-avx512f.l: Likewise.

opcodes/

	PR gas/24625
	* i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
	Disp8ShiftVL.
	* i386-tbl.h: Regenerated.

8 files changed, 38 insertions, 4 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 6ca88da..7de5247 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,12 @@
+2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR gas/24625
+	* testsuite/gas/i386/inval-avx512f.s: Add tests for AVX512_BF16
+	instructions with invalid broadcast.
+	* testsuite/gas/i386/x86-64-inval-avx512f.s: Likewise.
+	* testsuite/gas/i386/inval-avx512f.l: Updated.
+	* testsuite/gas/i386/x86-64-inval-avx512f.l: Likewise.
+
 2019-05-27  Alan Modra  <amodra@gmail.com>
 
 	* config/tc-ppc.c (is_ppc64_target): New function.
diff --git a/gas/testsuite/gas/i386/inval-avx512f.l b/gas/testsuite/gas/i386/inval-avx512f.l
index 048e88b..e414129 100644
--- a/gas/testsuite/gas/i386/inval-avx512f.l
+++ b/gas/testsuite/gas/i386/inval-avx512f.l
@@ -211,6 +211,8 @@
 .*:304: Error: .*masking.*vscatterpf1dps.*
 .*:305: Error: .*masking.*vscatterpf1qpd.*
 .*:306: Error: .*masking.*vscatterpf1qps.*
+.*:308: Error: .*unsupported broadcast for `vdpbf16ps'
+.*:309: Error: .*unsupported broadcast for `vcvtne2ps2bf16'
 GAS LISTING .*
 
 
@@ -546,3 +548,6 @@ GAS LISTING .*
 [ 	]*304[ 	]+vscatterpf1dps \(%eax,%zmm1\)\{%k1\}\{z\}
 [ 	]*305[ 	]+vscatterpf1qpd \(%eax,%zmm1\)\{%k1\}\{z\}
 [ 	]*306[ 	]+vscatterpf1qps \(%eax,%zmm1\)\{%k1\}\{z\}
+[ 	]*307[ 	]*
+[ 	]*308[ 	]+vdpbf16ps 8\(%eax\)\{1to8\}, %zmm2, %zmm2
+[ 	]*309[ 	]+vcvtne2ps2bf16 8\(%eax\)\{1to8\}, %zmm2, %zmm2
diff --git a/gas/testsuite/gas/i386/inval-avx512f.s b/gas/testsuite/gas/i386/inval-avx512f.s
index f380fe3..2833b1e 100644
--- a/gas/testsuite/gas/i386/inval-avx512f.s
+++ b/gas/testsuite/gas/i386/inval-avx512f.s
@@ -304,3 +304,6 @@ _start:
 	vscatterpf1dps (%eax,%zmm1){%k1}{z}
 	vscatterpf1qpd (%eax,%zmm1){%k1}{z}
 	vscatterpf1qps (%eax,%zmm1){%k1}{z}
+
+	vdpbf16ps 8(%eax){1to8}, %zmm2, %zmm2
+	vcvtne2ps2bf16 8(%eax){1to8}, %zmm2, %zmm2
diff --git a/gas/testsuite/gas/i386/x86-64-inval-avx512f.l b/gas/testsuite/gas/i386/x86-64-inval-avx512f.l
index 7aa4d5d..634683f 100644
--- a/gas/testsuite/gas/i386/x86-64-inval-avx512f.l
+++ b/gas/testsuite/gas/i386/x86-64-inval-avx512f.l
@@ -39,6 +39,8 @@
 .*:55: Error: .*
 .*:56: Error: .*
 .*:58: Error: .*
+.*:61: Error: .*unsupported broadcast for `vdpbf16ps'
+.*:62: Error: .*unsupported broadcast for `vcvtne2ps2bf16'
 GAS LISTING .*
 
 
@@ -101,3 +103,7 @@ GAS LISTING .*
 [ 	]*57[ 	]*
 GAS LISTING .*
 [ 	]*58[ 	]+vcvtps2qq xmm0, DWORD PTR \[rax\]
+[ 	]*59[ 	]*
+[ 	]*60[ 	]+\.att_syntax prefix
+[ 	]*61[ 	]+vdpbf16ps 8\(%rax\)\{1to8\}, %zmm2, %zmm2
+[ 	]*62[ 	]+vcvtne2ps2bf16 8\(%rax\)\{1to8\}, %zmm2, %zmm2
diff --git a/gas/testsuite/gas/i386/x86-64-inval-avx512f.s b/gas/testsuite/gas/i386/x86-64-inval-avx512f.s
index 91bf562..934e906 100644
--- a/gas/testsuite/gas/i386/x86-64-inval-avx512f.s
+++ b/gas/testsuite/gas/i386/x86-64-inval-avx512f.s
@@ -56,3 +56,7 @@ _start:
 	vaddps zmm2{z}, zmm1, zmm0
 
 	vcvtps2qq xmm0, DWORD PTR [rax]
+
+	.att_syntax prefix
+	vdpbf16ps 8(%rax){1to8}, %zmm2, %zmm2
+	vcvtne2ps2bf16 8(%rax){1to8}, %zmm2, %zmm2
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index faeccf4..8c881a2 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,10 @@
+2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR gas/24625
+	* i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
+	Disp8ShiftVL.
+	* i386-tbl.h: Regenerated.
+
 2019-05-24  Alan Modra  <amodra@gmail.com>
 
 	* po/POTFILES.in: Regenerate.
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 11ee240..f3b3a95 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -4713,7 +4713,7 @@ movdir64b, 2, 0x660f38f8, None, 3, CpuMOVDIR64B|Cpu64, Modrm|No_bSuf|No_wSuf|No_
 
 // AVX512_BF16 instructions.
 
-vcvtne2ps2bf16, 3, 0xf272, None, 1, CpuAVX512_BF16, Modrm|VexOpcode|VexVVVV|Masking=3|VexW0|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
+vcvtne2ps2bf16, 3, 0xf272, None, 1, CpuAVX512_BF16, Modrm|VexOpcode|VexVVVV|Masking=3|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
 
 vcvtneps2bf16, 2, 0xf372, None, 1, CpuAVX512_BF16|CpuAVX512VL, Modrm|VexOpcode|EVex128|Masking=3|VexW0|Broadcast|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|BaseIndex, RegXMM }
 vcvtneps2bf16, 2, 0xf372, None, 1, CpuAVX512_BF16|CpuAVX512VL, Modrm|VexOpcode|EVex256|Masking=3|VexW0|Broadcast|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|BaseIndex, RegXMM }
@@ -4722,6 +4722,6 @@ vcvtneps2bf16, 2, 0xf372, None, 1, CpuAVX512_BF16, Modrm|VexOpcode|EVex512|Maski
 vcvtneps2bf16x, 2, 0xf372, None, 1, CpuAVX512_BF16|CpuAVX512VL, Modrm|VexOpcode|EVex128|Masking=3|VexW0|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Unspecified|BaseIndex, RegXMM }
 vcvtneps2bf16y, 2, 0xf372, None, 1, CpuAVX512_BF16|CpuAVX512VL, Modrm|VexOpcode|EVex256|Masking=3|VexW0|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Unspecified|BaseIndex, RegXMM }
 
-vdpbf16ps, 3, 0xf352, None, 1, CpuAVX512_BF16, Modrm|VexOpcode|VexVVVV|Masking=3|VexW0|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
+vdpbf16ps, 3, 0xf352, None, 1, CpuAVX512_BF16, Modrm|VexOpcode|VexVVVV|Masking=3|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
 
 // AVX512_BF16 instructions end.
diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index ab251c6..5e1611e 100644
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -67651,7 +67651,7 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0 } },
-    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1,
       1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
       1, 1, 0, 0, 0, 0, 0, 3, 3, 0, 0, 7, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
@@ -67750,7 +67750,7 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0 } },
-    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1,
       1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
       1, 1, 0, 0, 0, 0, 0, 3, 3, 0, 0, 7, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,