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| author | Gavin Romig-Koch <gavin@redhat.com> | 1997-09-20 18:22:22 +0000 |
|---|---|---|
| committer | Gavin Romig-Koch <gavin@redhat.com> | 1997-09-20 18:22:22 +0000 |
| commit | c476ac55601cb83d48fe31e0b075ac8c8ee2cbc5 (patch) | |
| tree | fe3b4fb9f8e0200104233c12eb63e69b197ea9d4 | |
| parent | 20b32dc554f8f0a728a7f695533ca5f05f54f165 (diff) | |
| download | gdb-c476ac55601cb83d48fe31e0b075ac8c8ee2cbc5.zip gdb-c476ac55601cb83d48fe31e0b075ac8c8ee2cbc5.tar.gz gdb-c476ac55601cb83d48fe31e0b075ac8c8ee2cbc5.tar.bz2 | |
Add handling for 3900's SDBBP, DERET, and RFE insns.
* gencode.c (SDBBP,DERET): Added (3900) insns.
(RFE): Turn on for 3900.
* interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
(dsstate): Made global.
(SUBTARGET_R3900): Added.
(CANCELDELAYSLOT): New.
(SignalException): Ignore SystemCall rather than ignore and
terminate. Add DebugBreakPoint handling.
(decode_coproc): New insns RFE, DERET; and new registers Debug
and DEPC protected by SUBTARGET_R3900.
(sim_engine_run): Use CANCELDELAYSLOT rather than clearing
bits explicitly.
* Makefile.in,configure.in: Add mips subtarget option.
* configure: Update.
| -rw-r--r-- | sim/mips/configure.in | 8 | ||||
| -rw-r--r-- | sim/mips/gencode.c | 14 |
2 files changed, 15 insertions, 7 deletions
diff --git a/sim/mips/configure.in b/sim/mips/configure.in index 1ffee3c..a417a48 100644 --- a/sim/mips/configure.in +++ b/sim/mips/configure.in @@ -27,6 +27,14 @@ case "${target}" in esac AC_SUBST(SIMCONF) +case "${target}" in +# start-sanitize-tx19 + mipstx19*-*-*) SIM_SUBTARGET="-DSUBTARGET_R3900=1";; +# end-sanitize-tx19 + *) SIM_SUBTARGET="";; +esac +AC_SUBST(SIM_SUBTARGET) + AC_CHECK_HEADERS(string.h strings.h stdlib.h stdlib.h) AC_CHECK_LIB(m, fabs) AC_CHECK_FUNCS(aint anint sqrt) diff --git a/sim/mips/gencode.c b/sim/mips/gencode.c index 2f8e60e..7f0269f 100644 --- a/sim/mips/gencode.c +++ b/sim/mips/gencode.c @@ -290,6 +290,7 @@ typedef enum { SHIFT, /* perform a logical or arithmetic shift */ TRAP, /* system exception generation */ BREAK, /* system breakpoint exception generation */ + SDBBP, /* software debug breakpoint exception generation */ SYSCALL, /* system exception generation */ SYNC, /* system cache control */ DECODE, /* co-processor instruction */ @@ -823,6 +824,7 @@ struct instruction MIPS_DECODE[] = { {"SCD", 3,"111100sssssgggggeeeeeeeeeeeeeeee",NORMAL, STORE, (DOUBLEWORD | ATOMIC)}, {"SD", 3,"111111sssssgggggeeeeeeeeeeeeeeee",NORMAL, STORE, (DOUBLEWORD)}, {"SDC1", 2,"111101sssssttttteeeeeeeeeeeeeeee",NORMAL, STORE, (DOUBLEWORD | COPROC)}, + {"SDBBP", T3,"000000????????????????????001110",SPECIAL,SDBBP, (NOARG)}, {"SDC2", 2,"111110sssssttttteeeeeeeeeeeeeeee",NORMAL, STORE, (DOUBLEWORD | COPROC)}, {"SDL", 3,"101100sssssgggggyyyyyyyyyyyyyyyy",NORMAL, STORE, (DOUBLEWORD | LEFT)}, {"SDR", 3,"101101sssssgggggyyyyyyyyyyyyyyyy",NORMAL, STORE, (DOUBLEWORD | RIGHT)}, @@ -941,6 +943,7 @@ static const struct instruction MIPS16_DECODE[] = { {"NOT", 1, "11101dddyyy01111Z", RR, OR, NOT }, {"OR", 1, "11101wwwyyy01101", RR, OR, NONE }, {"SB", 1, "11000xxxyyy55555", RRI, STORE, BYTE }, +{"SDBBP", T3, "11100??????00001", RR, SDBBP, NOARG }, {"SD", 3, "01111xxxyyyDDDDD", RRI, STORE, DOUBLEWORD }, {"SDSP", 3, "11111001yyyDDDDDs", RI64, STORE, DOUBLEWORD }, {"SDRASP", 3, "11111010CCCCCCCCsQ", I64, STORE, DOUBLEWORD }, @@ -2418,6 +2421,10 @@ build_instruction (doisa, features, mips16, insn) printf(" SignalException(BreakPoint,instruction);\n"); break ; + case SDBBP: + printf(" SignalException(DebugBreakPoint,instruction);\n"); + break ; + case TRAP: { int boolNOT = (insn->flags & NOT); @@ -4493,10 +4500,3 @@ my_strtoul(nptr, endptr, base) /*---------------------------------------------------------------------------*/ /*> EOF gencode.c <*/ - - - - - - - |