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authorMichael Snyder <msnyder@vmware.com>2003-08-11 19:36:23 +0000
committerMichael Snyder <msnyder@vmware.com>2003-08-11 19:36:23 +0000
commitbe8fb42bc59b5e593fc259b4d2cd2fefe98fba33 (patch)
tree65dcefc2735e6244e8535241ce2ca31381474845
parentd1789acece69deabeddae520341aa828d5a96c7f (diff)
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2003-08-11 Michael Snyder <msnyder@redhat.com>
* macl.s: New file. * macw.s: New file. * allinsn.exp: Add new tests for mac.w and mac.l.
-rw-r--r--sim/testsuite/sim/sh/ChangeLog6
-rw-r--r--sim/testsuite/sim/sh/allinsn.exp2
-rw-r--r--sim/testsuite/sim/sh/macl.s54
-rw-r--r--sim/testsuite/sim/sh/macw.s56
4 files changed, 118 insertions, 0 deletions
diff --git a/sim/testsuite/sim/sh/ChangeLog b/sim/testsuite/sim/sh/ChangeLog
index 832eac4..7df64f7 100644
--- a/sim/testsuite/sim/sh/ChangeLog
+++ b/sim/testsuite/sim/sh/ChangeLog
@@ -1,3 +1,9 @@
+2003-08-11 Michael Snyder <msnyder@redhat.com>
+
+ * macl.s: New file.
+ * macw.s: New file.
+ * allinsn.exp: Add new tests for mac.w and mac.l.
+
2003-07-25 Michael Snyder <msnyder@redhat.com>
* pshai.s, pshar.s, pshli.s, pshlr.s: New files.
diff --git a/sim/testsuite/sim/sh/allinsn.exp b/sim/testsuite/sim/sh/allinsn.exp
index 8664af0..7192e81 100644
--- a/sim/testsuite/sim/sh/allinsn.exp
+++ b/sim/testsuite/sim/sh/allinsn.exp
@@ -24,6 +24,8 @@ if [istarget sh-*elf] {
run_sim_test fsqrt.s sh
run_sim_test fsub.s sh
run_sim_test ftrc.s sh
+ run_sim_test macl.s sh
+ run_sim_test macw.s sh
run_sim_test paddc.s shdsp
run_sim_test padd.s shdsp
run_sim_test pand.s shdsp
diff --git a/sim/testsuite/sim/sh/macl.s b/sim/testsuite/sim/sh/macl.s
new file mode 100644
index 0000000..39b3b7d
--- /dev/null
+++ b/sim/testsuite/sim/sh/macl.s
@@ -0,0 +1,54 @@
+# sh testcase for mac.l
+# mach: all
+# as(sh): -defsym sim_cpu=0
+# as(shdsp): -defsym sim_cpu=1 -dsp
+
+ .include "testutils.inc"
+
+ start
+ # force S-bit clear
+ clrs
+
+init:
+ # Prime {MACL, MACH} to #1.
+ mov #1, r0
+ dmulu.l r0, r0
+
+ # Set up addresses.
+ mov.l pfour00, r0 ! 85
+ mov.l pfour12, r1 ! 17
+
+test:
+ mac.l @r0+, @r1+
+
+check:
+ # Check result.
+ assert_sreg 0, mach
+ assert_sreg 85*17+1, macl
+
+ # Ensure post-increment occurred.
+ assertreg0 four00+4
+ assertreg four12+4, r1
+
+doubleinc:
+ mov.l pfour00, r0
+ mac.l @r0+, @r0+
+ assertreg0 four00+8
+
+
+ pass
+ exit 0
+
+ .align 1
+four00:
+ .long 85
+ .long 2
+four12:
+ .long 17
+ .long 3
+
+ .align 2
+pfour00:
+ .long four00
+pfour12:
+ .long four12
diff --git a/sim/testsuite/sim/sh/macw.s b/sim/testsuite/sim/sh/macw.s
new file mode 100644
index 0000000..7e3ebc0
--- /dev/null
+++ b/sim/testsuite/sim/sh/macw.s
@@ -0,0 +1,56 @@
+# sh testcase for mac.w
+# mach: all
+# as(sh): -defsym sim_cpu=0
+# as(shdsp): -defsym sim_cpu=1 -dsp
+
+ .include "testutils.inc"
+
+ start
+ set_grs_a5a5
+
+ # Prime {MACL, MACH} to #1.
+ mov #1, r0
+ dmulu.l r0, r0
+
+ # Set up addresses.
+ mov.l pfour00, r0 ! 85
+ mov.l pfour12, r1 ! 17
+
+test:
+ mac.w @r0+, @r1+ ! MAC = 85 * 17 + 1
+
+check:
+ # Check result.
+ assert_sreg 0, mach
+ assert_sreg 85*17+1, macl
+
+ # Ensure post-increment occurred.
+ assertreg0 four00+2
+ assertreg four12+2, r1
+
+doubleinc:
+ mov.l pfour00, r0
+ mac.w @r0+, @r0+
+ assertreg0 four00+4
+
+ set_greg 0xa5a5a5a5, r0
+ set_greg 0xa5a5a5a5, r1
+
+ test_grs_a5a5
+
+ pass
+ exit 0
+
+ .align 2
+four00:
+ .word 85
+ .word 2
+four12:
+ .word 17
+ .word 3
+
+
+pfour00:
+ .long four00
+pfour12:
+ .long four12