From 948bf10686a16b92f8c413bb3f1440f0f770b087 Mon Sep 17 00:00:00 2001 From: Eric Botcazou Date: Mon, 30 Nov 2009 08:31:40 +0000 Subject: sparc.c (DF_MODES): Simplify. * config/sparc/sparc.c (DF_MODES): Simplify. (TF_ONLY_MODES, OF_ONLY_MODES): Delete. (TF_MODES, OF_MODES): Adjust for above change. (TF_MODES_NO_S, OF_MODES_NO_S): Likewise. * config/sparc/sparc.h (REGNO_REG_CLASS): Move around. From-SVN: r154755 --- gcc/ChangeLog | 9 ++++++++- gcc/config/sparc/sparc.c | 25 ++++++++++--------------- gcc/config/sparc/sparc.h | 18 +++++++++--------- 3 files changed, 27 insertions(+), 25 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index a2a90f8..ae70d02 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2009-11-30 Eric Botcazou + + * config/sparc/sparc.c (DF_MODES): Simplify. + (TF_ONLY_MODES, OF_ONLY_MODES): Delete. + (TF_MODES, OF_MODES): Adjust for above change. + (TF_MODES_NO_S, OF_MODES_NO_S): Likewise. + * config/sparc/sparc.h (REGNO_REG_CLASS): Move around. + 2009-11-30 Paolo Bonzini PR rtl-optimization/41812 @@ -13,7 +21,6 @@ (df_md_local_compute): Only include live registers in init. (df_md_transfer_function): Prune the in-set computed by the confluence function, and the gen-set too. - (df_simulate_one_insn_forwards): Fix typo. 2009-11-30 Hans-Peter Nilsson diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c index 75bb2dd..ee069d6 100644 --- a/gcc/config/sparc/sparc.c +++ b/gcc/config/sparc/sparc.c @@ -3733,27 +3733,22 @@ enum sparc_mode_class { #define SF_MODES (S_MODES) /* Modes for double-float and smaller quantities. */ -#define DF_MODES (S_MODES | D_MODES) - -/* Modes for double-float only quantities. */ -#define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE)) - -/* Modes for quad-float only quantities. */ -#define TF_ONLY_MODES (1 << (int) TF_MODE) +#define DF_MODES (D_MODES) /* Modes for quad-float and smaller quantities. */ -#define TF_MODES (DF_MODES | TF_ONLY_MODES) +#define TF_MODES (DF_MODES | (1 << (int) TF_MODE)) -/* Modes for quad-float and double-float quantities. */ -#define TF_MODES_NO_S (DF_MODES_NO_S | TF_ONLY_MODES) +/* Modes for quad-float pairs and smaller quantities. */ +#define OF_MODES (TF_MODES | (1 << (int) OF_MODE)) -/* Modes for quad-float pair only quantities. */ -#define OF_ONLY_MODES (1 << (int) OF_MODE) +/* Modes for double-float only quantities. */ +#define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE)) -/* Modes for quad-float pairs and smaller quantities. */ -#define OF_MODES (TF_MODES | OF_ONLY_MODES) +/* Modes for quad-float and double-float only quantities. */ +#define TF_MODES_NO_S (DF_MODES_NO_S | (1 << (int) TF_MODE)) -#define OF_MODES_NO_S (TF_MODES_NO_S | OF_ONLY_MODES) +/* Modes for quad-float pairs and double-float only quantities. */ +#define OF_MODES_NO_S (TF_MODES_NO_S | (1 << (int) OF_MODE)) /* Modes for condition codes. */ #define CC_MODES (1 << (int) CC_MODE) diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h index 13efc69..58c584e 100644 --- a/gcc/config/sparc/sparc.h +++ b/gcc/config/sparc/sparc.h @@ -1068,6 +1068,15 @@ enum reg_class { NO_REGS, FPCC_REGS, I64_REGS, GENERAL_REGS, FP_REGS, {-1, -1, -1, 0x20}, /* GENERAL_OR_EXTRA_FP_REGS */ \ {-1, -1, -1, 0x3f}} /* ALL_REGS */ +/* The same information, inverted: + Return the class number of the smallest class containing + reg number REGNO. This could be a conditional expression + or could index an array. */ + +extern enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER]; + +#define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)] + /* The following macro defines cover classes for Integrated Register Allocator. Cover classes is a set of non-intersected register classes covering all hard registers used for register allocation @@ -1095,15 +1104,6 @@ enum reg_class { NO_REGS, FPCC_REGS, I64_REGS, GENERAL_REGS, FP_REGS, && GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ ? reg_classes_intersect_p (CLASS, FP_REGS) : 0) -/* The same information, inverted: - Return the class number of the smallest class containing - reg number REGNO. This could be a conditional expression - or could index an array. */ - -extern enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER]; - -#define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)] - /* This is the order in which to allocate registers normally. We put %f0-%f7 last among the float registers, so as to make it more -- cgit v1.1