From 4a684e46ec9a2a42b2b0c7e919e6624b5eca127f Mon Sep 17 00:00:00 2001 From: liuhongt Date: Thu, 24 Aug 2023 12:07:57 +0800 Subject: Refactor mode iterator V_128 and V_128H, V_256 and V_256H Merge then together. gcc/ChangeLog: * config/i386/sse.md (vec_set): Removed. (V_128H): Merge into .. (V_128): .. this. (V_256H): Merge into .. (V_256): .. this. (V_512): Add V32HF, V32BF. (*ssse3_palignr_perm): Adjust mode iterator from V_128H to V_128. (vcond): Removed (vcondu): Removed. (avx_vbroadcastf128_): Refator from V_256H to V_256. --- gcc/config/i386/sse.md | 65 ++++++-------------------------------------------- 1 file changed, 7 insertions(+), 58 deletions(-) (limited to 'gcc') diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 2b1f351..4857545 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -312,17 +312,10 @@ ;; All 128bit vector modes (define_mode_iterator V_128 - [V16QI V8HI V4SI V2DI V4SF (V2DF "TARGET_SSE2")]) - -(define_mode_iterator V_128H [V16QI V8HI V8HF V8BF V4SI V2DI V4SF (V2DF "TARGET_SSE2")]) ;; All 256bit vector modes (define_mode_iterator V_256 - [V32QI V16HI V8SI V4DI V8SF V4DF]) - -;; All 256bit vector modes including HF/BF vector modes -(define_mode_iterator V_256H [V32QI V16HI V8SI V4DI V8SF V4DF V16HF V16BF]) ;; All 128bit and 256bit vector modes @@ -331,7 +324,7 @@ V16HF V8HF V8SF V4SF V4DF V2DF]) ;; All 512bit vector modes -(define_mode_iterator V_512 [V64QI V32HI V16SI V8DI V16SF V8DF]) +(define_mode_iterator V_512 [V64QI V32HI V16SI V8DI V16SF V8DF V32HF V32BF]) ;; All 256bit and 512bit vector modes (define_mode_iterator V_256_512 @@ -4614,21 +4607,6 @@ DONE; }) -(define_expand "vcond" - [(set (match_operand:VF_AVX512HFBFVL 0 "register_operand") - (if_then_else:VF_AVX512HFBFVL - (match_operator 3 "" - [(match_operand: 4 "vector_operand") - (match_operand: 5 "vector_operand")]) - (match_operand:VF_AVX512HFBFVL 1 "general_operand") - (match_operand:VF_AVX512HFBFVL 2 "general_operand")))] - "TARGET_AVX512FP16" -{ - bool ok = ix86_expand_int_vcond (operands); - gcc_assert (ok); - DONE; -}) - (define_expand "vcond" [(set (match_operand: 0 "register_operand") (if_then_else: @@ -11369,20 +11347,6 @@ }) (define_expand "vec_set" - [(match_operand:V8BFH_128 0 "register_operand") - (match_operand: 1 "register_operand") - (match_operand 2 "vec_setm_sse41_operand")] - "TARGET_SSE" -{ - if (CONST_INT_P (operands[2])) - ix86_expand_vector_set (false, operands[0], operands[1], - INTVAL (operands[2])); - else - ix86_expand_vector_set_var (operands[0], operands[1], operands[2]); - DONE; -}) - -(define_expand "vec_set" [(match_operand:V_256_512 0 "register_operand") (match_operand: 1 "register_operand") (match_operand 2 "vec_setm_avx2_operand")] @@ -11835,7 +11799,7 @@ (define_expand "avx_vextractf128" [(match_operand: 0 "nonimmediate_operand") - (match_operand:V_256H 1 "register_operand") + (match_operand:V_256 1 "register_operand") (match_operand:SI 2 "const_0_to_1_operand")] "TARGET_AVX" { @@ -17282,21 +17246,6 @@ DONE; }) -(define_expand "vcondu" - [(set (match_operand:VF_AVX512FP16VL 0 "register_operand") - (if_then_else:VF_AVX512FP16VL - (match_operator 3 "" - [(match_operand: 4 "vector_operand") - (match_operand: 5 "vector_operand")]) - (match_operand:VF_AVX512FP16VL 1 "general_operand") - (match_operand:VF_AVX512FP16VL 2 "general_operand")))] - "TARGET_AVX512FP16" -{ - bool ok = ix86_expand_int_vcond (operands); - gcc_assert (ok); - DONE; -}) - (define_expand "vcondeqv2di" [(set (match_operand:VI8F_128 0 "register_operand") (if_then_else:VI8F_128 @@ -26834,8 +26783,8 @@ "operands[2] = gen_lowpart (mode, operands[0]);") (define_insn "avx_vbroadcastf128_" - [(set (match_operand:V_256H 0 "register_operand" "=x,x,x,v,v,v,v") - (vec_concat:V_256H + [(set (match_operand:V_256 0 "register_operand" "=x,x,x,v,v,v,v") + (vec_concat:V_256 (match_operand: 1 "nonimmediate_operand" "m,0,?x,m,0,m,0") (match_dup 1)))] "TARGET_AVX" @@ -27155,9 +27104,9 @@ (set_attr "mode" "")]) (define_insn "*ssse3_palignr_perm" - [(set (match_operand:V_128H 0 "register_operand" "=x,Yw") - (vec_select:V_128H - (match_operand:V_128H 1 "register_operand" "0,Yw") + [(set (match_operand:V_128 0 "register_operand" "=x,Yw") + (vec_select:V_128 + (match_operand:V_128 1 "register_operand" "0,Yw") (match_parallel 2 "palignr_operand" [(match_operand 3 "const_int_operand")])))] "TARGET_SSSE3" -- cgit v1.1