From 00eab082e9f6ac2a7c4b38323829be29f092abcb Mon Sep 17 00:00:00 2001 From: Pat Haugen Date: Mon, 9 Aug 2021 10:05:49 -0500 Subject: Verify destination[source] of a load[store] instruction is a register. gcc/ChangeLog: * config/rs6000/rs6000.c (is_load_insn1): Verify destination is a register. (is_store_insn1): Verify source is a register. --- gcc/config/rs6000/rs6000.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) (limited to 'gcc') diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 5b1c06b..60f406a 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -18363,7 +18363,12 @@ is_load_insn1 (rtx pat, rtx *load_mem) return false; if (GET_CODE (pat) == SET) - return find_mem_ref (SET_SRC (pat), load_mem); + { + if (REG_P (SET_DEST (pat))) + return find_mem_ref (SET_SRC (pat), load_mem); + else + return false; + } if (GET_CODE (pat) == PARALLEL) { @@ -18400,7 +18405,12 @@ is_store_insn1 (rtx pat, rtx *str_mem) return false; if (GET_CODE (pat) == SET) - return find_mem_ref (SET_DEST (pat), str_mem); + { + if (REG_P (SET_SRC (pat)) || SUBREG_P (SET_SRC (pat))) + return find_mem_ref (SET_DEST (pat), str_mem); + else + return false; + } if (GET_CODE (pat) == PARALLEL) { -- cgit v1.1