From 0a09a9483825233f16e5b26bb0ffee76752339fc Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Thu, 9 Jan 2020 16:36:42 +0000 Subject: [AArch64] Add support for the SVE2 ACLE This patch adds support for the SVE2 ACLE, The implementation and tests follow the same pattern as the exiting SVE ACLE support. 2020-01-09 Richard Sandiford gcc/ * config.gcc (aarch64*-*-*): Add aarch64-sve-builtins-sve2.o to extra_objs. * config/aarch64/t-aarch64 (aarch64-sve-builtins.o): Depend on aarch64-sve-builtins-base.def, aarch64-sve-builtins-sve2.def and aarch64-sve-builtins-sve2.h. (aarch64-sve-builtins-sve2.o): New rule. * config/aarch64/aarch64.h (AARCH64_ISA_SVE2_AES): New macro. (AARCH64_ISA_SVE2_BITPERM, AARCH64_ISA_SVE2_SHA3): Likewise. (AARCH64_ISA_SVE2_SM4, TARGET_SVE2_AES, TARGET_SVE2_BITPERM): Likewise. (TARGET_SVE2_SHA, TARGET_SVE2_SM4): Likewise. * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Handle TARGET_SVE2_AES, TARGET_SVE2_BITPERM, TARGET_SVE2_SHA3 and TARGET_SVE2_SM4. * config/aarch64/aarch64-sve.md: Update comments with SVE2 instructions that are handled here. (@cond_asrd): Generalize to... (@cond_): ...this. (*cond_asrd_2): Generalize to... (*cond__2): ...this. (*cond_asrd_z): Generalize to... (*cond__z): ...this. * config/aarch64/aarch64.md (UNSPEC_LDNT1_GATHER): New unspec. (UNSPEC_STNT1_SCATTER, UNSPEC_WHILEGE, UNSPEC_WHILEGT): Likewise. (UNSPEC_WHILEHI, UNSPEC_WHILEHS): Likewise. * config/aarch64/aarch64-sve2.md (@aarch64_gather_ldnt): New pattern. (@aarch64_gather_ldnt_) (@aarch64_scatter_stnt): Likewise. (@aarch64_scatter_stnt_) (@aarch64_mul_lane_): Likewise. (@aarch64_sve_suqadd_const): Likewise. (*h): Generalize to... (@aarch64_pred_): ...this new pattern. (@cond_): New expander. (*cond__2): New pattern. (*cond__3): Likewise. (*cond__any): Likewise. (*cond__z): Likewise. (@aarch64_sve_):: Likewise. (@aarch64_sve__lane_): Likewise. (@aarch64_pred_): Likewise. (@cond_): New expander. (*cond__2): New pattern. (*cond__3): Likewise. (*cond__any): Likewise. (@aarch64_sve_): Likewise. (@aarch64_sve__lane_) (@aarch64_sve_add_mul_lane_): Likewise. (@aarch64_sve_sub_mul_lane_): Likewise. (@aarch64_sve2_xar): Likewise. (@aarch64_sve2_bcax): Likewise. (*aarch64_sve2_eor3): Rename to... (@aarch64_sve2_eor3): ...this. (@aarch64_sve2_bsl): New expander. (@aarch64_sve2_nbsl): Likewise. (@aarch64_sve2_bsl1n): Likewise. (@aarch64_sve2_bsl2n): Likewise. (@aarch64_sve_add_): Likewise. (*aarch64_sve2_sra): Add MOVPRFX support. (@aarch64_sve_add_): New pattern. (@aarch64_sve_): Likewise. (@aarch64_sve2_aba): New expander. (*aarch64_sve2_aba): New pattern. (@aarch64_sve_): Likewise. (mull): Generalize to... (@aarch64_sve_): ...this new pattern. (@aarch64_sve__lane_) (@aarch64_sve_) (@aarch64_sve_add_) (@aarch64_sve_add__lane_) (@aarch64_sve_qadd_) (@aarch64_sve_qadd__lane_) (@aarch64_sve_sub_) (@aarch64_sve_sub__lane_) (@aarch64_sve_qsub_) (@aarch64_sve_qsub__lane_) (@aarch64_sve_): New patterns. (@aarch64__lane_) (@aarch64_sve_): Likewise. (@aarch64_sve_): Likewise. (@aarch64_sve_): Likewise. (@aarch64_sve_): Likewise. (shrnb): Generalize to... (@aarch64_sve_): ...this new pattern. (shrnt): Generalize to... (@aarch64_sve_): ...this new pattern. (@aarch64_pred_): New pattern. (@aarch64_pred_): Likewise. (@cond_): New expander. (*cond__2): New pattern. (*cond__z): Likewise. (@aarch64_sve_): Likewise. (@aarch64_sve_): Likewise. (@aarch64__lane_): Likewise. (@aarch64_sve_): Likewise. (@aarch64__lane_): Likewise. (@aarch64_pred_): Likewise. (@cond_): New expander. (*cond_): New pattern. (@aarch64_sve2_cvtnt): Likewise. (@aarch64_pred_): Likewise. (@cond_): New expander. (*cond__any): New pattern. (@aarch64_sve2_cvtxnt): Likewise. (@aarch64_pred_): Likewise. (@cond_): New expander. (*cond_): New pattern. (@aarch64_pred_): Likewise. (@cond_): New expander. (*cond_): New pattern. (@aarch64_sve2_pmul): Likewise. (@aarch64_sve_): Likewise. (@aarch64_sve_): Likewise. (@aarch64_sve2_tbl2): Likewise. (@aarch64_sve2_tbx): Likewise. (@aarch64_sve_): Likewise. (@aarch64_sve2_histcnt): Likewise. (@aarch64_sve2_histseg): Likewise. (@aarch64_pred_): Likewise. (*aarch64_pred__cc): Likewise. (*aarch64_pred__ptest): Likewise. (aarch64_sve2_aes): Likewise. (aarch64_sve2_aes): Likewise. (*aarch64_sve2_aese_fused, *aarch64_sve2_aesd_fused): Likewise. (aarch64_sve2_rax1, aarch64_sve2_sm4e, aarch64_sve2_sm4ekey): Likewise. (mulhs3): Update after above pattern name changes. * config/aarch64/iterators.md (VNx16QI_ONLY, VNx4SF_ONLY) (SVE_STRUCT2, SVE_FULL_BHI, SVE_FULL_HSI, SVE_FULL_HDI) (SVE2_PMULL_PAIR_I): New mode iterators. (UNSPEC_ADCLB, UNSPEC_ADCLT, UNSPEC_ADDHNB, UNSPEC_ADDHNT, UNSPEC_BDEP) (UNSPEC_BEXT, UNSPEC_BGRP, UNSPEC_CADD90, UNSPEC_CADD270, UNSPEC_CDOT) (UNSPEC_CDOT90, UNSPEC_CDOT180, UNSPEC_CDOT270, UNSPEC_CMLA) (UNSPEC_CMLA90, UNSPEC_CMLA180, UNSPEC_CMLA270, UNSPEC_COND_FCVTLT) (UNSPEC_COND_FCVTNT, UNSPEC_COND_FCVTX, UNSPEC_COND_FCVTXNT) (UNSPEC_COND_FLOGB, UNSPEC_EORBT, UNSPEC_EORTB, UNSPEC_FADDP) (UNSPEC_FMAXP, UNSPEC_FMAXNMP, UNSPEC_FMLALB, UNSPEC_FMLALT) (UNSPEC_FMLSLB, UNSPEC_FMLSLT, UNSPEC_FMINP, UNSPEC_FMINNMP) (UNSPEC_HISTCNT, UNSPEC_HISTSEG, UNSPEC_MATCH, UNSPEC_NMATCH) (UNSPEC_PMULLB, UNSPEC_PMULLB_PAIR, UNSPEC_PMULLT, UNSPEC_PMULLT_PAIR) (UNSPEC_RADDHNB, UNSPEC_RADDHNT, UNSPEC_RSUBHNB, UNSPEC_RSUBHNT) (UNSPEC_SLI, UNSPEC_SRI, UNSPEC_SABDLB, UNSPEC_SABDLT, UNSPEC_SADDLB) (UNSPEC_SADDLBT, UNSPEC_SADDLT, UNSPEC_SADDWB, UNSPEC_SADDWT) (UNSPEC_SBCLB, UNSPEC_SBCLT, UNSPEC_SMAXP, UNSPEC_SMINP) (UNSPEC_SQCADD90, UNSPEC_SQCADD270, UNSPEC_SQDMULLB, UNSPEC_SQDMULLBT) (UNSPEC_SQDMULLT, UNSPEC_SQRDCMLAH, UNSPEC_SQRDCMLAH90) (UNSPEC_SQRDCMLAH180, UNSPEC_SQRDCMLAH270, UNSPEC_SQRSHRNB) (UNSPEC_SQRSHRNT, UNSPEC_SQRSHRUNB, UNSPEC_SQRSHRUNT, UNSPEC_SQSHRNB) (UNSPEC_SQSHRNT, UNSPEC_SQSHRUNB, UNSPEC_SQSHRUNT, UNSPEC_SQXTNB) (UNSPEC_SQXTNT, UNSPEC_SQXTUNB, UNSPEC_SQXTUNT, UNSPEC_SSHLLB) (UNSPEC_SSHLLT, UNSPEC_SSUBLB, UNSPEC_SSUBLBT, UNSPEC_SSUBLT) (UNSPEC_SSUBLTB, UNSPEC_SSUBWB, UNSPEC_SSUBWT, UNSPEC_SUBHNB) (UNSPEC_SUBHNT, UNSPEC_TBL2, UNSPEC_UABDLB, UNSPEC_UABDLT) (UNSPEC_UADDLB, UNSPEC_UADDLT, UNSPEC_UADDWB, UNSPEC_UADDWT) (UNSPEC_UMAXP, UNSPEC_UMINP, UNSPEC_UQRSHRNB, UNSPEC_UQRSHRNT) (UNSPEC_UQSHRNB, UNSPEC_UQSHRNT, UNSPEC_UQXTNB, UNSPEC_UQXTNT) (UNSPEC_USHLLB, UNSPEC_USHLLT, UNSPEC_USUBLB, UNSPEC_USUBLT) (UNSPEC_USUBWB, UNSPEC_USUBWT): New unspecs. (UNSPEC_SMULLB, UNSPEC_SMULLT, UNSPEC_UMULLB, UNSPEC_UMULLT) (UNSPEC_SMULHS, UNSPEC_SMULHRS, UNSPEC_UMULHS, UNSPEC_UMULHRS) (UNSPEC_RSHRNB, UNSPEC_RSHRNT, UNSPEC_SHRNB, UNSPEC_SHRNT): Move further down file. (VNARROW, Ventype): New mode attributes. (Vewtype): Handle VNx2DI. Fix typo in comment. (VDOUBLE): New mode attribute. (sve_lane_con): Handle VNx8HI. (SVE_INT_UNARY): Include ss_abs and ss_neg for TARGET_SVE2. (SVE_INT_BINARY): Likewise ss_plus, us_plus, ss_minus and us_minus. (sve_int_op, sve_int_op_rev): Handle the above codes. (sve_pred_int_rhs2_operand): Likewise. (MULLBT, SHRNB, SHRNT): Delete. (SVE_INT_SHIFT_IMM): New int iterator. (SVE_WHILE): Add UNSPEC_WHILEGE, UNSPEC_WHILEGT, UNSPEC_WHILEHI and UNSPEC_WHILEHS for TARGET_SVE2. (SVE2_U32_UNARY, SVE2_INT_UNARY_NARROWB, SVE2_INT_UNARY_NARROWT) (SVE2_INT_BINARY, SVE2_INT_BINARY_LANE, SVE2_INT_BINARY_LONG) (SVE2_INT_BINARY_LONG_LANE, SVE2_INT_BINARY_NARROWB) (SVE2_INT_BINARY_NARROWT, SVE2_INT_BINARY_PAIR, SVE2_FP_BINARY_PAIR) (SVE2_INT_BINARY_PAIR_LONG, SVE2_INT_BINARY_WIDE): New int iterators. (SVE2_INT_SHIFT_IMM_LONG, SVE2_INT_SHIFT_IMM_NARROWB): Likewise. (SVE2_INT_SHIFT_IMM_NARROWT, SVE2_INT_SHIFT_INSERT, SVE2_INT_CADD) (SVE2_INT_BITPERM, SVE2_INT_TERNARY, SVE2_INT_TERNARY_LANE): Likewise. (SVE2_FP_TERNARY_LONG, SVE2_FP_TERNARY_LONG_LANE, SVE2_INT_CMLA) (SVE2_INT_CDOT, SVE2_INT_ADD_BINARY_LONG, SVE2_INT_QADD_BINARY_LONG) (SVE2_INT_SUB_BINARY_LONG, SVE2_INT_QSUB_BINARY_LONG): Likewise. (SVE2_INT_ADD_BINARY_LONG_LANE, SVE2_INT_QADD_BINARY_LONG_LANE) (SVE2_INT_SUB_BINARY_LONG_LANE, SVE2_INT_QSUB_BINARY_LONG_LANE) (SVE2_COND_INT_UNARY_FP, SVE2_COND_FP_UNARY_LONG): Likewise. (SVE2_COND_FP_UNARY_NARROWB, SVE2_COND_INT_BINARY): Likewise. (SVE2_COND_INT_BINARY_NOREV, SVE2_COND_INT_BINARY_REV): Likewise. (SVE2_COND_INT_SHIFT, SVE2_MATCH, SVE2_PMULL): Likewise. (optab): Handle the new unspecs. (su, r): Remove entries for UNSPEC_SHRNB, UNSPEC_SHRNT, UNSPEC_RSHRNB and UNSPEC_RSHRNT. (lr): Handle the new unspecs. (bt): Delete. (cmp_op, while_optab_cmp, sve_int_op): Handle the new unspecs. (sve_int_op_rev, sve_int_add_op, sve_int_qadd_op, sve_int_sub_op) (sve_int_qsub_op): New int attributes. (sve_fp_op, rot): Handle the new unspecs. * config/aarch64/aarch64-sve-builtins.h (function_resolver::require_matching_pointer_type): Declare. (function_resolver::resolve_unary): Add an optional boolean argument. (function_resolver::finish_opt_n_resolution): Add an optional type_suffix_index argument. (gimple_folder::redirect_call): Declare. (gimple_expander::prepare_gather_address_operands): Add an optional bool parameter. * config/aarch64/aarch64-sve-builtins.cc: Include aarch64-sve-builtins-sve2.h. (TYPES_b_unsigned, TYPES_b_integer, TYPES_bh_integer): New macros. (TYPES_bs_unsigned, TYPES_hs_signed, TYPES_hs_integer): Likewise. (TYPES_hd_unsigned, TYPES_hsd_signed): Likewise. (TYPES_hsd_integer): Use TYPES_hsd_signed. (TYPES_s_float_hsd_integer, TYPES_s_float_sd_integer): New macros. (TYPES_s_unsigned): Likewise. (TYPES_s_integer): Use TYPES_s_unsigned. (TYPES_sd_signed, TYPES_sd_unsigned): New macros. (TYPES_sd_integer): Use them. (TYPES_d_unsigned): New macro. (TYPES_d_integer): Use it. (TYPES_d_data, TYPES_cvt_long, TYPES_cvt_narrow_s): New macros. (TYPES_cvt_narrow): Likewise. (DEF_SVE_TYPES_ARRAY): Include the new types macros above. (preds_mx): New variable. (function_builder::add_overloaded_function): Allow the new feature set to be more restrictive than the original one. (function_resolver::infer_pointer_type): Remove qualifiers from the pointer type before printing it. (function_resolver::require_matching_pointer_type): New function. (function_resolver::resolve_sv_displacement): Handle functions that don't support 32-bit vector indices or svint32_t vector offsets. (function_resolver::finish_opt_n_resolution): Take the inferred type as a separate argument. (function_resolver::resolve_unary): Optionally treat all forms in the same way as normal merging functions. (gimple_folder::redirect_call): New function. (function_expander::prepare_gather_address_operands): Add an argument that says whether scaled forms are available. If they aren't, handle scaling of vector indices and don't add the extension and scaling operands. (function_expander::map_to_unspecs): If aarch64_sve isn't available, fall back to using cond_* instead. * config/aarch64/aarch64-sve-builtins-functions.h (rtx_code_function): Split out the member variables into... (rtx_code_function_base): ...this new base class. (rtx_code_function_rotated): Inherit rtx_code_function_base. (unspec_based_function): Split out the member variables into... (unspec_based_function_base): ...this new base class. (unspec_based_function_rotated): Inherit unspec_based_function_base. (unspec_based_function_exact_insn): New class. (unspec_based_add_function, unspec_based_add_lane_function) (unspec_based_lane_function, unspec_based_pred_function) (unspec_based_qadd_function, unspec_based_qadd_lane_function) (unspec_based_qsub_function, unspec_based_qsub_lane_function) (unspec_based_sub_function, unspec_based_sub_lane_function): New typedefs. (unspec_based_fused_function): New class. (unspec_based_mla_function, unspec_based_mls_function): New typedefs. (unspec_based_fused_lane_function): New class. (unspec_based_mla_lane_function, unspec_based_mls_lane_function): New typedefs. (CODE_FOR_MODE1): New macro. (fixed_insn_function): New class. (while_comparison): Likewise. * config/aarch64/aarch64-sve-builtins-shapes.h (binary_long_lane) (binary_long_opt_n, binary_narrowb_opt_n, binary_narrowt_opt_n) (binary_to_uint, binary_wide, binary_wide_opt_n, compare, compare_ptr) (load_ext_gather_index_restricted, load_ext_gather_offset_restricted) (load_gather_sv_restricted, shift_left_imm_long): Declare. (shift_left_imm_to_uint, shift_right_imm_narrowb): Likewise. (shift_right_imm_narrowt, shift_right_imm_narrowb_to_uint): Likewise. (shift_right_imm_narrowt_to_uint, store_scatter_index_restricted) (store_scatter_offset_restricted, tbl_tuple, ternary_long_lane) (ternary_long_opt_n, ternary_qq_lane_rotate, ternary_qq_rotate) (ternary_shift_left_imm, ternary_shift_right_imm, ternary_uint) (unary_convert_narrowt, unary_long, unary_narrowb, unary_narrowt) (unary_narrowb_to_uint, unary_narrowt_to_uint, unary_to_int): Likewise. * config/aarch64/aarch64-sve-builtins-shapes.cc (apply_predication): Also add an initial argument for unary_convert_narrowt, regardless of the predication type. (build_32_64): Allow loads and stores to specify MODE_none. (build_sv_index64, build_sv_uint_offset): New functions. (long_type_suffix): New function. (binary_imm_narrowb_base, binary_imm_narrowt_base): New classes. (binary_imm_long_base, load_gather_sv_base): Likewise. (shift_right_imm_narrow_wrapper, ternary_shift_imm_base): Likewise. (ternary_resize2_opt_n_base, ternary_resize2_lane_base): Likewise. (unary_narrowb_base, unary_narrowt_base): Likewise. (binary_long_lane_def, binary_long_lane): New shape. (binary_long_opt_n_def, binary_long_opt_n): Likewise. (binary_narrowb_opt_n_def, binary_narrowb_opt_n): Likewise. (binary_narrowt_opt_n_def, binary_narrowt_opt_n): Likewise. (binary_to_uint_def, binary_to_uint): Likewise. (binary_wide_def, binary_wide): Likewise. (binary_wide_opt_n_def, binary_wide_opt_n): Likewise. (compare_def, compare): Likewise. (compare_ptr_def, compare_ptr): Likewise. (load_ext_gather_index_restricted_def, load_ext_gather_index_restricted): Likewise. (load_ext_gather_offset_restricted_def, load_ext_gather_offset_restricted): Likewise. (load_gather_sv_def): Inherit from load_gather_sv_base. (load_gather_sv_restricted_def, load_gather_sv_restricted): New shape. (shift_left_imm_def, shift_left_imm): Likewise. (shift_left_imm_long_def, shift_left_imm_long): Likewise. (shift_left_imm_to_uint_def, shift_left_imm_to_uint): Likewise. (store_scatter_index_restricted_def, store_scatter_index_restricted): Likewise. (store_scatter_offset_restricted_def, store_scatter_offset_restricted): Likewise. (tbl_tuple_def, tbl_tuple): Likewise. (ternary_long_lane_def, ternary_long_lane): Likewise. (ternary_long_opt_n_def, ternary_long_opt_n): Likewise. (ternary_qq_lane_def): Inherit from ternary_resize2_lane_base. (ternary_qq_lane_rotate_def, ternary_qq_lane_rotate): New shape (ternary_qq_opt_n_def): Inherit from ternary_resize2_opt_n_base. (ternary_qq_rotate_def, ternary_qq_rotate): New shape. (ternary_shift_left_imm_def, ternary_shift_left_imm): Likewise. (ternary_shift_right_imm_def, ternary_shift_right_imm): Likewise. (ternary_uint_def, ternary_uint): Likewise. (unary_convert): Fix typo in comment. (unary_convert_narrowt_def, unary_convert_narrowt): New shape. (unary_long_def, unary_long): Likewise. (unary_narrowb_def, unary_narrowb): Likewise. (unary_narrowt_def, unary_narrowt): Likewise. (unary_narrowb_to_uint_def, unary_narrowb_to_uint): Likewise. (unary_narrowt_to_uint_def, unary_narrowt_to_uint): Likewise. (unary_to_int_def, unary_to_int): Likewise. * config/aarch64/aarch64-sve-builtins-base.cc (unspec_cmla) (unspec_fcmla, unspec_cond_fcmla, expand_mla_mls_lane): New functions. (svasrd_impl): Delete. (svcadd_impl::expand): Handle integer operations too. (svcmla_impl::expand, svcmla_lane::expand): Likewise, using the new functions to derive the unspec numbers. (svmla_svmls_lane_impl): Replace with... (svmla_lane_impl, svmls_lane_impl): ...these new classes. Handle integer operations too. (svwhile_impl): Rename to... (svwhilelx_impl): ...this and inherit from while_comparison. (svasrd): Use unspec_based_function. (svmla_lane): Use svmla_lane_impl. (svmls_lane): Use svmls_lane_impl. (svrecpe, svrsqrte): Handle unsigned integer operations too. (svwhilele, svwhilelt): Use svwhilelx_impl. * config/aarch64/aarch64-sve-builtins-sve2.h: New file. * config/aarch64/aarch64-sve-builtins-sve2.cc: Likewise. * config/aarch64/aarch64-sve-builtins-sve2.def: Likewise. * config/aarch64/aarch64-sve-builtins.def: Include aarch64-sve-builtins-sve2.def. gcc/testsuite/ * g++.target/aarch64/sve/acle/general-c++/mul_lane_1.c: New test. * g++.target/aarch64/sve2/acle: New directory. * gcc.target/aarch64/pragma_cpp_predefs_3.c: New test. * gcc.target/aarch64/sve/acle/asm/test_sve_acle.h (TEST_TYPE_CHANGE_Z) (TEST_DUAL_ZD, TEST_TYPE_CHANGE_ZX, TEST_TBL2, TEST_TBL2_REV): New macros. * gcc.target/aarch64/sve/acle/general-c/binary_lane_1.c: Do not expect an error saying that the function has no f32 form, but instead expect an error about SVE2 being required if the current target doesn't support SVE2. * gcc.target/aarch64/sve/acle/general-c/ternary_lane_1.c: Likewise. * gcc.target/aarch64/sve/acle/general-c/ternary_lane_rotate_1.c Likewise. * gcc.target/aarch64/sve/acle/general-c/binary_long_lane_1.c, * gcc.target/aarch64/sve/acle/general-c/binary_long_opt_n_1.c, * gcc.target/aarch64/sve/acle/general-c/binary_narrowb_opt_n_1.c, * gcc.target/aarch64/sve/acle/general-c/binary_narrowt_opt_n_1.c, * gcc.target/aarch64/sve/acle/general-c/binary_to_uint_1.c, * gcc.target/aarch64/sve/acle/general-c/binary_wide_1.c, * gcc.target/aarch64/sve/acle/general-c/binary_wide_opt_n_1.c, * gcc.target/aarch64/sve/acle/general-c/compare_1.c, * gcc.target/aarch64/sve/acle/general-c/compare_ptr_1.c, * gcc.target/aarch64/sve/acle/general-c/load_ext_gather_index_restricted_1.c, * gcc.target/aarch64/sve/acle/general-c/load_ext_gather_offset_restricted_1.c, * gcc.target/aarch64/sve/acle/general-c/load_ext_gather_offset_restricted_2.c, * gcc.target/aarch64/sve/acle/general-c/load_ext_gather_offset_restricted_3.c, * gcc.target/aarch64/sve/acle/general-c/load_ext_gather_offset_restricted_4.c, * gcc.target/aarch64/sve/acle/general-c/load_gather_sv_restricted_1.c, * gcc.target/aarch64/sve/acle/general-c/load_gather_sv_restricted_2.c, * gcc.target/aarch64/sve/acle/general-c/mul_lane_1.c, * gcc.target/aarch64/sve/acle/general-c/shift_left_imm_long_1.c, * gcc.target/aarch64/sve/acle/general-c/shift_left_imm_to_uint_1.c, * gcc.target/aarch64/sve/acle/general-c/shift_left_imm_to_uint_2.c, * gcc.target/aarch64/sve/acle/general-c/shift_right_imm_narrowb_1.c, * gcc.target/aarch64/sve/acle/general-c/shift_right_imm_narrowb_to_uint_1.c, * gcc.target/aarch64/sve/acle/general-c/shift_right_imm_narrowt_1.c, * gcc.target/aarch64/sve/acle/general-c/shift_right_imm_narrowt_to_uint_1.c, * gcc.target/aarch64/sve/acle/general-c/store_scatter_index_restricted_1.c, * gcc.target/aarch64/sve/acle/general-c/store_scatter_offset_restricted_1.c, * gcc.target/aarch64/sve/acle/general-c/tbl_tuple_1.c, * gcc.target/aarch64/sve/acle/general-c/ternary_long_lane_1.c, * gcc.target/aarch64/sve/acle/general-c/ternary_long_opt_n_1.c, * gcc.target/aarch64/sve/acle/general-c/ternary_qq_lane_rotate_1.c, * gcc.target/aarch64/sve/acle/general-c/ternary_qq_rotate_1.c, * gcc.target/aarch64/sve/acle/general-c/ternary_shift_right_imm_1.c, * gcc.target/aarch64/sve/acle/general-c/ternary_uint_1.c, * gcc.target/aarch64/sve/acle/general-c/unary_convert_narrowt_1.c, * gcc.target/aarch64/sve/acle/general-c/unary_narrowb_1.c, * gcc.target/aarch64/sve/acle/general-c/unary_narrowb_to_uint_1.c, * gcc.target/aarch64/sve/acle/general-c/unary_narrowt_1.c, * gcc.target/aarch64/sve/acle/general-c/unary_narrowt_to_uint_1.c, * gcc.target/aarch64/sve/acle/general-c/unary_to_int_1.c: New tests. * gcc.target/aarch64/sve2/bcax_1.c: Likewise. * gcc.target/aarch64/sve2/acle: New directory. From-SVN: r280060 --- gcc/config.gcc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc/config.gcc') diff --git a/gcc/config.gcc b/gcc/config.gcc index 6c957c4..2c57c24 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -319,7 +319,7 @@ aarch64*-*-*) c_target_objs="aarch64-c.o" cxx_target_objs="aarch64-c.o" d_target_objs="aarch64-d.o" - extra_objs="aarch64-builtins.o aarch-common.o aarch64-sve-builtins.o aarch64-sve-builtins-shapes.o aarch64-sve-builtins-base.o cortex-a57-fma-steering.o aarch64-speculation.o falkor-tag-collision-avoidance.o aarch64-bti-insert.o" + extra_objs="aarch64-builtins.o aarch-common.o aarch64-sve-builtins.o aarch64-sve-builtins-shapes.o aarch64-sve-builtins-base.o aarch64-sve-builtins-sve2.o cortex-a57-fma-steering.o aarch64-speculation.o falkor-tag-collision-avoidance.o aarch64-bti-insert.o" target_gtfiles="\$(srcdir)/config/aarch64/aarch64-builtins.c \$(srcdir)/config/aarch64/aarch64-sve-builtins.h \$(srcdir)/config/aarch64/aarch64-sve-builtins.cc" target_has_targetm_common=yes ;; -- cgit v1.1 From abbe1ed27355178223cd099fb73227f392416ea6 Mon Sep 17 00:00:00 2001 From: Stam Markianos-Wright Date: Fri, 10 Jan 2020 19:23:41 +0000 Subject: config.gcc: Add arm_bf16.h. 2020-01-10 Stam Markianos-Wright * config.gcc: Add arm_bf16.h. * config/aarch64/aarch64-builtins.c (aarch64_simd_builtin_std_type): Add BFmode. (aarch64_init_simd_builtin_types): Define element types for vector types. (aarch64_init_bf16_types): New function. (aarch64_general_init_builtins): Add arm_init_bf16_types function call. * config/aarch64/aarch64-modes.def: Add BFmode and V4BF, V8BF vector modes. * config/aarch64/aarch64-simd-builtin-types.def: Add BF SIMD types. * config/aarch64/aarch64-simd.md: Add BF vector types to NEON move patterns. * config/aarch64/aarch64.h (AARCH64_VALID_SIMD_DREG_MODE): Add V4BF. (AARCH64_VALID_SIMD_QREG_MODE): Add V8BF. * config/aarch64/aarch64.c (aarch64_classify_vector_mode): Add support for BF types. (aarch64_gimplify_va_arg_expr): Add support for BF types. (aarch64_vq_mode): Add support for BF types. (aarch64_simd_container_mode): Add support for BF types. (aarch64_mangle_type): Add support for BF scalar type. * config/aarch64/aarch64.md: Add BFmode to movhf pattern. * config/aarch64/arm_bf16.h: New file. * config/aarch64/arm_neon.h: Add arm_bf16.h and Bfloat vector types. * config/aarch64/iterators.md: Add BF types to mode attributes. (HFBF, GPF_TF_F16_MOV, VDMOV, VQMOV, VQMOV_NO2Em VALL_F16MOV): New. 2020-01-10 Stam Markianos-Wright * g++.dg/abi/mangle-neon-aarch64.C: Add Bfloat SIMD types to test. * g++.dg/ext/arm-bf16/bf16-mangle-aarch64-1.C: New test. * gcc.target/aarch64/bfloat16_scalar_1.c: New test. * gcc.target/aarch64/bfloat16_scalar_2.c: New test. * gcc.target/aarch64/bfloat16_scalar_3.c: New test. * gcc.target/aarch64/bfloat16_scalar_4.c: New test. * gcc.target/aarch64/bfloat16_simd_1.c: New test. * gcc.target/aarch64/bfloat16_simd_2.c: New test. * gcc.target/aarch64/bfloat16_simd_3.c: New test. From-SVN: r280129 --- gcc/config.gcc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc/config.gcc') diff --git a/gcc/config.gcc b/gcc/config.gcc index 2c57c24..30bea51 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -315,7 +315,7 @@ m32c*-*-*) ;; aarch64*-*-*) cpu_type=aarch64 - extra_headers="arm_fp16.h arm_neon.h arm_acle.h arm_sve.h" + extra_headers="arm_fp16.h arm_neon.h arm_bf16.h arm_acle.h arm_sve.h" c_target_objs="aarch64-c.o" cxx_target_objs="aarch64-c.o" d_target_objs="aarch64-d.o" -- cgit v1.1 From 2e87b2f4121fe1d39edb76f4e492dfe327be6a1b Mon Sep 17 00:00:00 2001 From: Stam Markianos-Wright Date: Thu, 16 Jan 2020 15:50:08 +0000 Subject: [GCC][PATCH][ARM] Add Bfloat16_t scalar type, vector types and machine modes to ARM back-end [1/2] gcc/ChangeLog: 2020-01-16 Stam Markianos-Wright * config.gcc: Add arm_bf16.h. * config/arm/arm-builtins.c (arm_mangle_builtin_type): Fix comment. (arm_simd_builtin_std_type): Add BFmode. (arm_init_simd_builtin_types): Define element types for vector types. (arm_init_bf16_types): New function. (arm_init_builtins): Add arm_init_bf16_types function call. * config/arm/arm-modes.def: Add BFmode and V4BF, V8BF vector modes. * config/arm/arm-simd-builtin-types.def: Add V4BF, V8BF. * config/arm/arm.c (aapcs_vfp_sub_candidate): Add BFmode. (arm_hard_regno_mode_ok): Add BFmode and tidy up statements. (arm_vector_mode_supported_p): Add V4BF, V8BF. (arm_mangle_type): Add __bf16. * config/arm/arm.h: Add V4BF, V8BF to VALID_NEON_DREG_MODE, VALID_NEON_QREG_MODE respectively. Add export arm_bf16_type_node, arm_bf16_ptr_type_node. * config/arm/arm.md: Add BFmode to movhf expand, mov pattern and define_split between ARM registers. * config/arm/arm_bf16.h: New file. * config/arm/arm_neon.h: Add arm_bf16.h and Bfloat vector types. * config/arm/iterators.md: (ANY64_BF, VDXMOV, VHFBF, HFBF, fporbf): New. (VQXMOV): Add V8BF. * config/arm/neon.md: Add BF vector types to movhf NEON move patterns. * config/arm/vfp.md: Add BFmode to movhf patterns. gcc/testsuite/ChangeLog: 2020-01-16 Stam Markianos-Wright * g++.dg/abi/mangle-neon.C: Add BF16 SIMD types. * g++.dg/ext/arm-bf16/bf16-mangle-1.C: New test. * gcc.target/arm/bfloat16_scalar_1_1.c: New test. * gcc.target/arm/bfloat16_scalar_1_2.c: New test. * gcc.target/arm/bfloat16_scalar_2_1.c: New test. * gcc.target/arm/bfloat16_scalar_2_2.c: New test. * gcc.target/arm/bfloat16_scalar_3_1.c: New test. * gcc.target/arm/bfloat16_scalar_3_2.c: New test. * gcc.target/arm/bfloat16_scalar_4.c: New test. * gcc.target/arm/bfloat16_simd_1_1.c: New test. * gcc.target/arm/bfloat16_simd_1_2.c: New test. * gcc.target/arm/bfloat16_simd_2_1.c: New test. * gcc.target/arm/bfloat16_simd_2_2.c: New test. * gcc.target/arm/bfloat16_simd_3_1.c: New test. * gcc.target/arm/bfloat16_simd_3_2.c: New test. --- gcc/config.gcc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc/config.gcc') diff --git a/gcc/config.gcc b/gcc/config.gcc index 30bea51..5a2f173 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -344,7 +344,7 @@ arc*-*-*) arm*-*-*) cpu_type=arm extra_objs="arm-builtins.o aarch-common.o" - extra_headers="mmintrin.h arm_neon.h arm_acle.h arm_fp16.h arm_cmse.h" + extra_headers="mmintrin.h arm_neon.h arm_acle.h arm_fp16.h arm_cmse.h arm_bf16.h" target_type_format_char='%' c_target_objs="arm-c.o" cxx_target_objs="arm-c.o" -- cgit v1.1 From 8118184c3e144cb6455caca0b19541cb317061a4 Mon Sep 17 00:00:00 2001 From: Hans-Peter Nilsson Date: Sat, 18 Jan 2020 14:23:59 +0100 Subject: config.gcc : Add crisv32-*-* and cris-*-linux* I'm sorry to say that there's no incentive to maintain crisv32-*-* and cris-*-linux* configurations beyond nostalgia, (and I'm out of that for the moment). Support in the Linux kernel for either applicable CRIS variant (CRIS v10 and CRIS v32) is gone since 2018. Their related part of the cc0 transition workload would be noticable. Note that cris-elf remains, but crisv32-elf and the CRIS v32 multilib will be removed, at least for now. I'm not completely happy about the message (the next-next line after the context) "*** unless a maintainer comes forward" because it'd have to be at an infinitesimal maintenance cost to the cris-elf support. Still, I'm not bothered enough to add another case construct or means for "planned obsolescence". --- gcc/config.gcc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'gcc/config.gcc') diff --git a/gcc/config.gcc b/gcc/config.gcc index 5a2f173..5532a7b 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -248,6 +248,8 @@ md_file= # Obsolete configurations. case ${target} in tile*-*-* \ + | crisv32-*-* \ + | cris-*-linux* \ ) if test "x$enable_obsolete" != xyes; then echo "*** Configuration ${target} is obsolete." >&2 -- cgit v1.1 From 591f869ad70ba2b5cf1d8a8b57529142cc0d0554 Mon Sep 17 00:00:00 2001 From: Andrew Stubbs Date: Mon, 3 Feb 2020 15:02:22 +0000 Subject: Remove gfx801 "carrizo" support 2020-02-03 Andrew Stubbs gcc/ * config.gcc: Remove "carrizo" support. * config/gcn/gcn-opts.h (processor_type): Likewise. * config/gcn/gcn.c (gcn_omp_device_kind_arch_isa): Likewise. * config/gcn/gcn.opt (gpu_type): Likewise. * config/gcn/t-omp-device: Likewise. libgomp/ * plugin/plugin-gcn.c (EF_AMDGPU_MACH_AMDGCN_GFX801): Remove. (gcn_gfx801_s): Remove. (isa_hsa_name): Remove gfx801. (isa_gcc_name): Remove gfx801/carizzo. (isa_code): Remove gfx801. --- gcc/config.gcc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc/config.gcc') diff --git a/gcc/config.gcc b/gcc/config.gcc index 5532a7b..ae5a845 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -4404,7 +4404,7 @@ case "${target}" in for which in arch tune; do eval "val=\$with_$which" case ${val} in - "" | carrizo | fiji | gfx900 | gfx906 ) + "" | fiji | gfx900 | gfx906 ) # OK ;; *) -- cgit v1.1 From 48c16b2867917883b1efc0cb7d9142c833fb5ec4 Mon Sep 17 00:00:00 2001 From: Andreas Krebbel Date: Wed, 4 Mar 2020 13:29:39 +0100 Subject: IBM Z: zTPF: Include glibc-stdint.h to get __UINTPTR_TYPE__ defined Building a zTPF cross currently fails when building libstdc++ complaining about the __UINTPTR_TYPE__ to be missing. Fixed by including the glibc-stdint.h header. 2020-03-04 Andreas Krebbel * config.gcc: Include the glibc-stdint.h header for zTPF. --- gcc/config.gcc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc/config.gcc') diff --git a/gcc/config.gcc b/gcc/config.gcc index ae5a845..2df4b36 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -3104,7 +3104,7 @@ s390x-*-linux*) tmake_file="${tmake_file} s390/t-linux64 s390/t-s390" ;; s390x-ibm-tpf*) - tm_file="s390/s390x.h s390/s390.h dbxelf.h elfos.h s390/tpf.h" + tm_file="s390/s390x.h s390/s390.h dbxelf.h elfos.h glibc-stdint.h s390/tpf.h" tm_p_file=s390/s390-protos.h c_target_objs="${c_target_objs} s390-c.o" cxx_target_objs="${cxx_target_objs} s390-c.o" -- cgit v1.1 From 63c8f7d6a082b1cd0519fe06d4ed506b04280921 Mon Sep 17 00:00:00 2001 From: Srinath Parvathaneni Date: Mon, 16 Mar 2020 17:06:29 +0000 Subject: [ARM][GCC][1/x]: MVE ACLE intrinsics framework patch. This patch creates the required framework for MVE ACLE intrinsics. The following changes are done in this patch to support MVE ACLE intrinsics. Header file arm_mve.h is added to source code, which contains the definitions of MVE ACLE intrinsics and different data types used in MVE. Machine description file mve.md is also added which contains the RTL patterns defined for MVE. A new reigster "p0" is added which is used in by MVE predicated patterns. A new register class "VPR_REG" is added and its contents are defined in REG_CLASS_CONTENTS. The vec-common.md file is modified to support the standard move patterns. The prefix of neon functions which are also used by MVE is changed from "neon_" to "simd_". eg: neon_immediate_valid_for_move changed to simd_immediate_valid_for_move. In the patch standard patterns mve_move, mve_store and move_load for MVE are added and neon.md and vfp.md files are modified to support this common patterns. Please refer to Arm reference manual [1] for more details. [1] https://developer.arm.com/docs/ddi0553/latest 2020-03-06 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config.gcc (arm_mve.h): Include mve intrinsics header file. * config/arm/aout.h (p0): Add new register name for MVE predicated cases. * config/arm-builtins.c (ARM_BUILTIN_SIMD_LANE_CHECK): Define macro common to Neon and MVE. (ARM_BUILTIN_NEON_LANE_CHECK): Renamed to ARM_BUILTIN_SIMD_LANE_CHECK. (arm_init_simd_builtin_types): Disable poly types for MVE. (arm_init_neon_builtins): Move a check to arm_init_builtins function. (arm_init_builtins): Use ARM_BUILTIN_SIMD_LANE_CHECK instead of ARM_BUILTIN_NEON_LANE_CHECK. (mve_dereference_pointer): Add function. (arm_expand_builtin_args): Call to mve_dereference_pointer when MVE is enabled. (arm_expand_neon_builtin): Moved to arm_expand_builtin function. (arm_expand_builtin): Moved from arm_expand_neon_builtin function. * config/arm/arm-c.c (__ARM_FEATURE_MVE): Define macro for MVE and MVE with floating point enabled. * config/arm/arm-protos.h (neon_immediate_valid_for_move): Renamed to simd_immediate_valid_for_move. (simd_immediate_valid_for_move): Renamed from neon_immediate_valid_for_move function. * config/arm/arm.c (arm_options_perform_arch_sanity_checks): Generate error if vfpv2 feature bit is disabled and mve feature bit is also disabled for HARD_FLOAT_ABI. (use_return_insn): Check to not push VFP regs for MVE. (aapcs_vfp_allocate): Add MVE check to have same Procedure Call Standard as Neon. (aapcs_vfp_allocate_return_reg): Likewise. (thumb2_legitimate_address_p): Check to return 0 on valid Thumb-2 address operand for MVE. (arm_rtx_costs_internal): MVE check to determine cost of rtx. (neon_valid_immediate): Rename to simd_valid_immediate. (simd_valid_immediate): Rename from neon_valid_immediate. (simd_valid_immediate): MVE check on size of vector is 128 bits. (neon_immediate_valid_for_move): Rename to simd_immediate_valid_for_move. (simd_immediate_valid_for_move): Rename from neon_immediate_valid_for_move. (neon_immediate_valid_for_logic): Modify call to neon_valid_immediate function. (neon_make_constant): Modify call to neon_valid_immediate function. (neon_vector_mem_operand): Return VFP register for POST_INC or PRE_DEC for MVE. (output_move_neon): Add MVE check to generate vldm/vstm instrcutions. (arm_compute_frame_layout): Calculate space for saved VFP registers for MVE. (arm_save_coproc_regs): Save coproc registers for MVE. (arm_print_operand): Add case 'E' to print memory operands for MVE. (arm_print_operand_address): Check to print register number for MVE. (arm_hard_regno_mode_ok): Check for arm hard regno mode ok for MVE. (arm_modes_tieable_p): Check to allow structure mode for MVE. (arm_regno_class): Add VPR_REGNUM check. (arm_expand_epilogue_apcs_frame): MVE check to calculate epilogue code for APCS frame. (arm_expand_epilogue): MVE check for enabling pop instructions in epilogue. (arm_print_asm_arch_directives): Modify function to disable print of .arch_extension "mve" and "fp" for cases where MVE is enabled with "SOFT FLOAT ABI". (arm_vector_mode_supported_p): Check for modes available in MVE interger and MVE floating point. (arm_array_mode_supported_p): Add TARGET_HAVE_MVE check for array mode pointer support. (arm_conditional_register_usage): Enable usage of conditional regsiter for MVE. (fixed_regs[VPR_REGNUM]): Enable VPR_REG for MVE. (arm_declare_function_name): Modify function to disable print of .arch_extension "mve" and "fp" for cases where MVE is enabled with "SOFT FLOAT ABI". * config/arm/arm.h (TARGET_HAVE_MVE): Disable for soft float abi and when target general registers are required. (TARGET_HAVE_MVE_FLOAT): Likewise. (FIXED_REGISTERS): Add bit for VFP_REG class which is enabled in arm.c for MVE. (CALL_USED_REGISTERS): Set bit for VFP_REG class in CALL_USED_REGISTERS which indicate this is not available for across function calls. (FIRST_PSEUDO_REGISTER): Modify. (VALID_MVE_MODE): Define valid MVE mode. (VALID_MVE_SI_MODE): Define valid MVE SI mode. (VALID_MVE_SF_MODE): Define valid MVE SF mode. (VALID_MVE_STRUCT_MODE): Define valid MVE struct mode. (VPR_REGNUM): Add Vector Predication Register in arm_regs_in_sequence for MVE. (IS_VPR_REGNUM): Macro to check for VPR_REG register. (REG_ALLOC_ORDER): Add VPR_REGNUM entry. (enum reg_class): Add VPR_REG entry. (REG_CLASS_NAMES): Add VPR_REG entry. * config/arm/arm.md (VPR_REGNUM): Define. (conds): Check is_mve_type attrbiute to differentiate "conditional" and "unconditional" instructions. (arm_movsf_soft_insn): Modify RTL to not allow for MVE. (movdf_soft_insn): Modify RTL to not allow for MVE. (vfp_pop_multiple_with_writeback): Enable for MVE. (include "mve.md"): Include mve.md file. * config/arm/arm_mve.h: Add MVE intrinsics head file. * config/arm/constraints.md (Up): Constraint to enable "p0" register in MVE for vector predicated operands. * config/arm/iterators.md (VNIM1): Define. (VNINOTM1): Define. (VHFBF_split): Define * config/arm/mve.md: New file. (mve_mov): Define RTL for move, store and load in MVE. (mve_mov): Define move RTL pattern with vec_duplicate operator for second operand. * config/arm/neon.md (neon_immediate_valid_for_move): Rename with simd_immediate_valid_for_move. (neon_mov): Split pattern and move expand pattern "movv8hf" which is common to MVE and NEON to vec-common.md file. (vec_init): Add TARGET_HAVE_MVE check. * config/arm/predicates.md (vpr_register_operand): Define. * config/arm/t-arm: Add mve.md file. * config/arm/types.md (mve_move): Add MVE instructions mve_move to attribute "type". (mve_store): Add MVE instructions mve_store to attribute "type". (mve_load): Add MVE instructions mve_load to attribute "type". (is_mve_type): Define attribute. * config/arm/vec-common.md (mov): Modify RTL expand to support standard move patterns in MVE along with NEON and IWMMXT with mode iterator VNIM1. (mov): Modify RTL expand to support standard move patterns in NEON and IWMMXT with mode iterator V8HF. (movv8hf): Define RTL expand to support standard "movv8hf" pattern in NEON and MVE. * config/arm/vfp.md (neon_immediate_valid_for_move): Rename to simd_immediate_valid_for_move. 2020-03-16 Andre Vieira Mihail Ionescu Srinath Parvathaneni * gcc.target/arm/mve/intrinsics/mve_vector_float.c: New test. * gcc.target/arm/mve/intrinsics/mve_vector_float1.c: Likewise. * gcc.target/arm/mve/intrinsics/mve_vector_float2.c: Likewise. * gcc.target/arm/mve/intrinsics/mve_vector_int.c: Likewise. * gcc.target/arm/mve/intrinsics/mve_vector_int1.c: Likewise. * gcc.target/arm/mve/intrinsics/mve_vector_int2.c: Likewise. * gcc.target/arm/mve/intrinsics/mve_vector_uint.c: Likewise. * gcc.target/arm/mve/intrinsics/mve_vector_uint1.c: Likewise. * gcc.target/arm/mve/intrinsics/mve_vector_uint2.c: Likewise. * gcc.target/arm/mve/mve.exp: New file. * lib/target-supports.exp (check_effective_target_arm_v8_1m_mve_fp_ok_nocache): Proc to check armv8.1-m.main+mve.fp and returning corresponding options. (check_effective_target_arm_v8_1m_mve_fp_ok): Proc to call check_effective_target_arm_v8_1m_mve_fp_ok_nocache to check support of MVE with floating point on the current target. (add_options_for_arm_v8_1m_mve_fp): Proc to call check_effective_target_arm_v8_1m_mve_fp_ok to return corresponding compiler options for MVE with floating point. (check_effective_target_arm_v8_1m_mve_ok_nocache): Modify to test and return hard float-abi on success. --- gcc/config.gcc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc/config.gcc') diff --git a/gcc/config.gcc b/gcc/config.gcc index 2df4b36..13e3cb7 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -346,7 +346,7 @@ arc*-*-*) arm*-*-*) cpu_type=arm extra_objs="arm-builtins.o aarch-common.o" - extra_headers="mmintrin.h arm_neon.h arm_acle.h arm_fp16.h arm_cmse.h arm_bf16.h" + extra_headers="mmintrin.h arm_neon.h arm_acle.h arm_fp16.h arm_cmse.h arm_bf16.h arm_mve.h" target_type_format_char='%' c_target_objs="arm-c.o" cxx_target_objs="arm-c.o" -- cgit v1.1 From 975e6670c428b032aa6ec600f57082d3cfb57393 Mon Sep 17 00:00:00 2001 From: Dennis Zhang Date: Wed, 8 Apr 2020 15:06:31 +0100 Subject: arm: CLI for Custom Datapath Extension (CDE) This patch is part of a series that adds support for the Arm Custom Datapath Extension. It defines the options cdecp0-cdecp7 for CLI to enable the CDE on corresponding coprocessor 0-7. It also adds new target supports for CDE feature testsuite. gcc/ChangeLog: 2020-04-08 Dennis Zhang * config.gcc: Add arm_cde.h. * config/arm/arm-c.c (arm_cpu_builtins): Define or undefine __ARM_FEATURE_CDE and __ARM_FEATURE_CDE_COPROC. * config/arm/arm-cpus.in (cdecp0, cdecp1, ..., cdecp7): New options. * config/arm/arm.c (arm_option_reconfigure_globals): Configure arm_arch_cde and arm_arch_cde_coproc to store the feature bits. * config/arm/arm.h (TARGET_CDE): New macro. * config/arm/arm_cde.h: New file. * doc/invoke.texi: Document CDE options +cdecp[0-7]. * doc/sourcebuild.texi (arm_v8m_main_cde_ok): Document new target supports option. (arm_v8m_main_cde_fp, arm_v8_1m_main_cde_mve): Likewise. gcc/testsuite/ChangeLog: 2020-04-08 Dennis Zhang * gcc.target/arm/pragma_cde.c: New test. * lib/target-supports.exp (arm_v8m_main_cde_ok): New target support option. (arm_v8m_main_cde_fp, arm_v8_1m_main_cde_mve): Likewise. --- gcc/config.gcc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc/config.gcc') diff --git a/gcc/config.gcc b/gcc/config.gcc index 13e3cb7..7624c65 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -346,7 +346,7 @@ arc*-*-*) arm*-*-*) cpu_type=arm extra_objs="arm-builtins.o aarch-common.o" - extra_headers="mmintrin.h arm_neon.h arm_acle.h arm_fp16.h arm_cmse.h arm_bf16.h arm_mve.h" + extra_headers="mmintrin.h arm_neon.h arm_acle.h arm_fp16.h arm_cmse.h arm_bf16.h arm_mve.h arm_cde.h" target_type_format_char='%' c_target_objs="arm-c.o" cxx_target_objs="arm-c.o" -- cgit v1.1 From 78bf9163764aba15bb0c254cd38c985713924380 Mon Sep 17 00:00:00 2001 From: Matthew Malcomson Date: Wed, 8 Apr 2020 16:06:47 +0100 Subject: [Arm] Implement CDE intrinsics for MVE registers. Implement CDE intrinsics on MVE registers. Other than the basics required for adding intrinsics this patch consists of three changes. ** We separate out the MVE types and casts from the arm_mve.h header. This is so that the types can be used in arm_cde.h without the need to include the entire arm_mve.h header. The only type that arm_cde.h needs is `uint8x16_t`, so this separation could be avoided by using a `typedef` in this file. Since the introduced intrinsics are all defined to act on the full range of MVE types, declaring all such types seems intuitive since it will provide their declaration to the user too. This arm_mve_types.h header not only includes the MVE types, but also the conversion intrinsics between them. Some of the conversion intrinsics are needed for arm_cde.h, but most are not. We include all conversion intrinsics to keep the definition of such conversion functions all in one place, on the understanding that extra conversion functions being defined when including `arm_cde.h` is not a problem. ** We define the TARGET_RESOLVE_OVERLOADED_BUILTIN hook for the Arm backend. This is needed to implement the polymorphism for the required intrinsics. The intrinsics have no specialised version, and the resulting assembly instruction for all different types should be exactly the same. Due to this we have implemented these intrinsics via one builtin on one type. All other calls to the intrinsic with different types are implicitly cast to the one type that is defined, and hence are all expanded to the same RTL pattern that is only defined for one machine mode. ** We seperate the initialisation of the CDE intrinsics from others. This allows us to ensure that the CDE intrinsics acting on MVE registers are only created when both CDE and MVE are available. Only initialising these builtins when both features are available is especially important since they require a type that is only initialised when the target supports hard float. Hence trying to initialise these builtins on a soft float target would cause an ICE. Testing done: Full bootstrap and regtest on arm-none-linux-gnueabihf Regression test on arm-none-eabi Ok for trunk? gcc/ChangeLog: 2020-03-10 Matthew Malcomson * config.gcc (arm_mve_types.h): New extra_header for arm. * config/arm/arm-builtins.c (arm_resolve_overloaded_builtin): New. (arm_init_cde_builtins): New. (arm_init_acle_builtins): Remove initialisation of CDE builtins. (arm_init_builtins): Call arm_init_cde_builtins when target supports CDE. * config/arm/arm-c.c (arm_resolve_overloaded_builtin): New declaration. (arm_register_target_pragmas): Initialise resolve_overloaded_builtin hook to the implementation for the arm backend. * config/arm/arm.h (ARM_MVE_CDE_CONST_1): New. (ARM_MVE_CDE_CONST_2): New. (ARM_MVE_CDE_CONST_3): New. * config/arm/arm_cde.h (__arm_vcx1q_u8): New. (__arm_vcx1qa): New. (__arm_vcx2q): New. (__arm_vcx2q_u8): New. (__arm_vcx2qa): New. (__arm_vcx3q): New. (__arm_vcx3q_u8): New. (__arm_vcx3qa): New. * config/arm/arm_cde_builtins.def (vcx1q, vcx1qa, vcx2q, vcx2qa, vcx3q, vcx3qa): New builtins defined. * config/arm/arm_mve.h: Move typedefs and conversion intrinsics to arm_mve_types.h header. * config/arm/arm_mve_types.h: New file. * config/arm/mve.md (arm_vcx1qv16qi, arm_vcx1qav16qi, arm_vcx2qv16qi, arm_vcx2qav16qi, arm_vcx3qv16qi, arm_vcx3qav16qi): New patterns. * config/arm/predicates.md (const_int_mve_cde1_operand, const_int_mve_cde2_operand, const_int_mve_cde3_operand): New. gcc/testsuite/ChangeLog: 2020-03-23 Matthew Malcomson Dennis Zhang * gcc.target/arm/acle/cde-mve-error-1.c: New test. * gcc.target/arm/acle/cde-mve-error-2.c: New test. * gcc.target/arm/acle/cde-mve-error-3.c: New test. * gcc.target/arm/acle/cde-mve-full-assembly.c: New test. * gcc.target/arm/acle/cde-mve-tests.c: New test. * lib/target-supports.exp (arm_v8_1m_main_cde_mve_fp): New check effective. (arm_v8_1m_main_cde_mve, arm_v8m_main_cde_fp): Use -mfpu=auto so we only check configurations that make sense. --- gcc/config.gcc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc/config.gcc') diff --git a/gcc/config.gcc b/gcc/config.gcc index 7624c65..cf1a87e 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -346,7 +346,7 @@ arc*-*-*) arm*-*-*) cpu_type=arm extra_objs="arm-builtins.o aarch-common.o" - extra_headers="mmintrin.h arm_neon.h arm_acle.h arm_fp16.h arm_cmse.h arm_bf16.h arm_mve.h arm_cde.h" + extra_headers="mmintrin.h arm_neon.h arm_acle.h arm_fp16.h arm_cmse.h arm_bf16.h arm_mve_types.h arm_mve.h arm_cde.h" target_type_format_char='%' c_target_objs="arm-c.o" cxx_target_objs="arm-c.o" -- cgit v1.1 From 366386c7a970bf6a32c5a2abb714ca6c7f4e7790 Mon Sep 17 00:00:00 2001 From: liuhongt Date: Wed, 4 Mar 2020 14:08:40 +0800 Subject: Enable GCC support for SERIALIZE 2020-03-04 Hongtao Liu 2020-03-04 Wei Xiao gcc/Changelog: * gcc/common/config/i386/i386-common.c (OPTION_MASK_ISA2_SERIALIZE_SET, OPTION_MASK_ISA2_SERIALIZE_UNSET): New macros. (ix86_handle_option): Handle -mserialize. * gcc/config.gcc (serializeintrin.h): New header file. * gcc/config/i386/cpuid.h (bit_SERIALIZE): New bit. * gcc/config/i386/driver-i386.c (host_detect_local_cpu): Detect -mserialize. * gcc/config/i386/i386-builtin.def: Add new builtin. * gcc/config/i386/i386-c.c (__SERIALIZE__): New macro. * gcc/config/i386/i386-options.c (ix86_target_opts_isa2_opts): Add -mserialize. * (ix86_valid_target_attribute_inner_p): Add target attribute * for serialize. * gcc/config/i386/i386.h (TARGET_SERIALIZE, TARGET_SERIALIZE_P): New macros. * gcc/config/i386/i386.md (UNSPECV_SERIALIZE): New unspec. (serialize): New define_insn. * gcc/config/i386/i386.opt (mserialize): New option * gcc/config/i386/immintrin.h: Include serailizeintrin.h. * gcc/config/i386/serializeintrin.h: New header file. * gcc/doc/invoke.texi: Add documents for -mserialize. gcc/testsuite/Changelog * gcc/testsuite/gcc.target/i386/serialize-1.c: New test. * gcc/testsuite/g++.dg/other/i386-2.C: Add -mserialize. * gcc/testsuite/g++.dg/other/i386-3.C: Ditto. * gcc/testsuite/gcc.target/i386/funcspec-56.inc: Ditto. * gcc/testsuite/gcc.target/i386/sse-12.c: Ditto. * gcc/testsuite/gcc.target/i386/sse-13.c: Ditto. * gcc/testsuite/gcc.target/i386/sse-14.c: Ditto. * gcc/testsuite/gcc.target/i386/sse-22.c: Ditto. * gcc/testsuite/gcc.target/i386/sse-23.c: Ditto. --- gcc/config.gcc | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'gcc/config.gcc') diff --git a/gcc/config.gcc b/gcc/config.gcc index cf1a87e..d48b6c7 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -412,8 +412,9 @@ i[34567]86-*-*) avx512vnnivlintrin.h vaesintrin.h vpclmulqdqintrin.h avx512vpopcntdqvlintrin.h avx512bitalgintrin.h pconfigintrin.h wbnoinvdintrin.h movdirintrin.h - waitpkgintrin.h cldemoteintrin.h avx512bf16vlintrin.h avx512bf16intrin.h - enqcmdintrin.h avx512vp2intersectintrin.h avx512vp2intersectvlintrin.h" + waitpkgintrin.h cldemoteintrin.h avx512bf16vlintrin.h + avx512bf16intrin.h enqcmdintrin.h serializeintrin.h + avx512vp2intersectintrin.h avx512vp2intersectvlintrin.h" ;; x86_64-*-*) cpu_type=i386 @@ -445,8 +446,9 @@ x86_64-*-*) avx512vnnivlintrin.h vaesintrin.h vpclmulqdqintrin.h avx512vpopcntdqvlintrin.h avx512bitalgintrin.h pconfigintrin.h wbnoinvdintrin.h movdirintrin.h - waitpkgintrin.h cldemoteintrin.h avx512bf16vlintrin.h avx512bf16intrin.h - enqcmdintrin.h avx512vp2intersectintrin.h avx512vp2intersectvlintrin.h" + waitpkgintrin.h cldemoteintrin.h avx512bf16vlintrin.h + avx512bf16intrin.h enqcmdintrin.h serializeintrin.h + avx512vp2intersectintrin.h avx512vp2intersectvlintrin.h" ;; ia64-*-*) extra_headers=ia64intrin.h -- cgit v1.1 From 1e47cb3597c9051f57dbd09b3e8c57371f70f037 Mon Sep 17 00:00:00 2001 From: liuhongt Date: Fri, 14 Feb 2020 15:40:46 +0800 Subject: Enable TARGET_TSXLDTRK for GCC support. gcc/ * common/config/i386/i386-common.c (OPTION_MASK_ISA2_TSXLDTRK_SET, OPTION_MASK_ISA2_TSXLDTRK_UNSET): New macros. * config.gcc: Add tsxldtrkintrin.h to extra_headers. * config/i386/driver-i386.c (host_detect_local_cpu): Detect TSXLDTRK. * config/i386/i386-builtin.def: Add new builtins. * config/i386/i386-c.c (ix86_target_macros_internal): Define __TSXLDTRK__. * config/i386/i386-options.c (ix86_target_string): Add -mtsxldtrk. (ix86_valid_target_attribute_inner_p): Add attribute tsxldtrk. * config/i386/i386.h (TARGET_TSXLDTRK, TARGET_TSXLDTRK_P): New. * config/i386/i386.md (define_c_enum "unspec"): Add UNSPECV_SUSLDTRK, UNSPECV_RESLDTRK. (TSXLDTRK): New define_int_iterator. (""): New define_insn. * config/i386/i386.opt: Add -mtsxldtrk. * config/i386/immintrin.h: Include tsxldtrkintrin.h. * config/i386/tsxldtrkintrin.h: New. * doc/invoke.texi: Document -mtsxldtrk. gcc/testsuite/ * g++.dg/other/i386-2.c: Add -mtsxldtrk. * g++.dg/other/i386-3.c: Likewise. * gcc.target/i386/sse-12.c: Likewise. * gcc.target/i386/sse-13.c: Likewise. * gcc.target/i386/sse-14.c: Likewise. * gcc.target/i386/sse-22.c: Likewsie. * gcc.target/i386/sse-23.c: Likewise. * gcc.target/i386/tsxldtrk-1.c: New test. * gcc.target/i386/funcspec-56.inc: Add target attribute tests for tsxldtrk. --- gcc/config.gcc | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'gcc/config.gcc') diff --git a/gcc/config.gcc b/gcc/config.gcc index d48b6c7..113bc64 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -414,7 +414,8 @@ i[34567]86-*-*) pconfigintrin.h wbnoinvdintrin.h movdirintrin.h waitpkgintrin.h cldemoteintrin.h avx512bf16vlintrin.h avx512bf16intrin.h enqcmdintrin.h serializeintrin.h - avx512vp2intersectintrin.h avx512vp2intersectvlintrin.h" + avx512vp2intersectintrin.h avx512vp2intersectvlintrin.h + tsxldtrkintrin.h" ;; x86_64-*-*) cpu_type=i386 @@ -448,7 +449,8 @@ x86_64-*-*) pconfigintrin.h wbnoinvdintrin.h movdirintrin.h waitpkgintrin.h cldemoteintrin.h avx512bf16vlintrin.h avx512bf16intrin.h enqcmdintrin.h serializeintrin.h - avx512vp2intersectintrin.h avx512vp2intersectvlintrin.h" + avx512vp2intersectintrin.h avx512vp2intersectvlintrin.h + tsxldtrkintrin.h" ;; ia64-*-*) extra_headers=ia64intrin.h -- cgit v1.1 From 2b36e4dc813af8b2572be7d145e6b98457ded962 Mon Sep 17 00:00:00 2001 From: Hans-Peter Nilsson Date: Wed, 22 Jan 2020 05:39:31 +0100 Subject: config.gcc: Remove support for crisv32-*-* and cris-*-linux*. Or really, move from the obsolete targets section, to unsupported targets section, and remove crisv32-*-* and cris-*-linux* from the rest. Part of the removal of crisv32-* and cris-*-linux* (cris-elf remains). gcc: * config.gcc: Remove support for crisv32-*-* and cris-*-linux*. --- gcc/config.gcc | 28 ++-------------------------- 1 file changed, 2 insertions(+), 26 deletions(-) (limited to 'gcc/config.gcc') diff --git a/gcc/config.gcc b/gcc/config.gcc index 113bc64..b7f1630 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -248,8 +248,6 @@ md_file= # Obsolete configurations. case ${target} in tile*-*-* \ - | crisv32-*-* \ - | cris-*-linux* \ ) if test "x$enable_obsolete" != xyes; then echo "*** Configuration ${target} is obsolete." >&2 @@ -273,6 +271,8 @@ case ${target} in | arm*-*-elf \ | arm*-*-linux* \ | arm*-*-uclinux* \ + | cris-*-linux* \ + | crisv32-*-* \ | i[34567]86-go32-* \ | i[34567]86-*-go32* \ | m68k-*-uclinuxoldabi* \ @@ -365,9 +365,6 @@ bfin*-*) bpf-*-*) cpu_type=bpf ;; -crisv32-*) - cpu_type=cris - ;; frv*) cpu_type=frv extra_options="${extra_options} g.opt" ;; @@ -1504,14 +1501,6 @@ cr16-*-elf) tmake_file="${tmake_file} cr16/t-cr16 " use_collect2=no ;; -crisv32-*-elf | crisv32-*-none) - tm_file="dbxelf.h elfos.h newlib-stdint.h ${tm_file}" - tmake_file="cris/t-cris" - target_cpu_default=32 - gas=yes - extra_options="${extra_options} cris/elf.opt" - use_gcc_stdint=wrap - ;; cris-*-elf | cris-*-none) tm_file="dbxelf.h elfos.h newlib-stdint.h ${tm_file}" tmake_file="cris/t-cris cris/t-elfmulti" @@ -1519,19 +1508,6 @@ cris-*-elf | cris-*-none) extra_options="${extra_options} cris/elf.opt" use_gcc_stdint=wrap ;; -crisv32-*-linux* | cris-*-linux*) - tm_file="dbxelf.h elfos.h ${tm_file} gnu-user.h linux.h glibc-stdint.h cris/linux.h" - tmake_file="${tmake_file} cris/t-cris cris/t-linux" - extra_options="${extra_options} cris/linux.opt" - case $target in - cris-*-*) - target_cpu_default=10 - ;; - crisv32-*-*) - target_cpu_default=32 - ;; - esac - ;; csky-*-*) if test x${with_endian} != x; then case ${with_endian} in -- cgit v1.1 From de6320a81695800de0f0f5fc3e4c6487a52cd430 Mon Sep 17 00:00:00 2001 From: Craig Blackmore Date: Tue, 12 May 2020 14:41:08 -0700 Subject: RISC-V: Add shorten_memrefs pass. gcc/ * config.gcc: Add riscv-shorten-memrefs.o to extra_objs for riscv. * config/riscv/riscv-passes.def: New file. * config/riscv/riscv-protos.h (make_pass_shorten_memrefs): Declare. * config/riscv/riscv-shorten-memrefs.c: New file. * config/riscv/riscv.c (tree-pass.h): New include. (riscv_compressed_reg_p): New Function (riscv_compressed_lw_offset_p): Likewise. (riscv_compressed_lw_address_p): Likewise. (riscv_shorten_lw_offset): Likewise. (riscv_legitimize_address): Attempt to convert base + large_offset to compressible new_base + small_offset. (riscv_address_cost): Make anticipated compressed load/stores cheaper for code size than uncompressed load/stores. (riscv_register_priority): Move compressed register check to riscv_compressed_reg_p. * config/riscv/riscv.h (C_S_BITS): Define. (CSW_MAX_OFFSET): Define. * config/riscv/riscv.opt (mshorten-memefs): New option. * config/riscv/t-riscv (riscv-shorten-memrefs.o): New rule. (PASSES_EXTRA): Add riscv-passes.def. * doc/invoke.texi: Document -mshorten-memrefs. * config/riscv/riscv.c (riscv_new_address_profitable_p): New function. (TARGET_NEW_ADDRESS_PROFITABLE_P): Define. * doc/tm.texi: Regenerate. * doc/tm.texi.in (TARGET_NEW_ADDRESS_PROFITABLE_P): New hook. * sched-deps.c (attempt_change): Use old address if it is cheaper than new address. * target.def (new_address_profitable_p): New hook. * targhooks.c (default_new_address_profitable_p): New function. * targhooks.h (default_new_address_profitable_p): Declare. gcc/testsuite/ * gcc.target/riscv/shorten-memrefs-1.c: New test. * gcc.target/riscv/shorten-memrefs-2.c: New test. * gcc.target/riscv/shorten-memrefs-3.c: New test. * gcc.target/riscv/shorten-memrefs-4.c: New test. * gcc.target/riscv/shorten-memrefs-5.c: New test. * gcc.target/riscv/shorten-memrefs-6.c: New test. * gcc.target/riscv/shorten-memrefs-7.c: New test. --- gcc/config.gcc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc/config.gcc') diff --git a/gcc/config.gcc b/gcc/config.gcc index b7f1630..f544932 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -526,7 +526,7 @@ pru-*-*) ;; riscv*) cpu_type=riscv - extra_objs="riscv-builtins.o riscv-c.o riscv-sr.o" + extra_objs="riscv-builtins.o riscv-c.o riscv-sr.o riscv-shorten-memrefs.o" d_target_objs="riscv-d.o" ;; rs6000*-*-*) -- cgit v1.1 From 86b14bb1a93d8ef01678d132013a2006a4f00deb Mon Sep 17 00:00:00 2001 From: Iain Buclaw Date: Mon, 1 Jun 2020 00:18:44 +0200 Subject: Fix unrecognised -mcpu target 'armv7-a' on arm-wrs-vxworks7 In the removal of arm-wrs-vxworks, the default cpu was updated from arm8 to armv7-a, but this is not recognized as a valid -mcpu target. There is however generic-armv7-a, which was likely the intended cpu that should have been used instead. gcc/ChangeLog: PR target/95420 * config.gcc (arm-wrs-vxworks7*): Set default cpu to generic-armv7-a. --- gcc/config.gcc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc/config.gcc') diff --git a/gcc/config.gcc b/gcc/config.gcc index f544932..06ad813 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -1193,7 +1193,7 @@ arm-wrs-vxworks7*) tmake_file="${tmake_file} arm/t-arm arm/t-vxworks arm/t-bpabi" tm_file="elfos.h arm/elf.h arm/bpabi.h arm/aout.h ${tm_file}" tm_file="${tm_file} vx-common.h vxworks.h arm/vxworks.h" - target_cpu_cname="armv7-a" + target_cpu_cname="generic-armv7-a" need_64bit_hwint=yes ;; arm*-*-freebsd*) # ARM FreeBSD EABI -- cgit v1.1