aboutsummaryrefslogtreecommitdiff
path: root/gcc
AgeCommit message (Collapse)AuthorFilesLines
2020-09-24updating for generic libcody interfacedevel/lto-offloadJohn Ravi2-12/+12
2020-08-291. renamed libcody lto functions to invoke functionsJohn Ravi3-45/+34
2. invoke (send to libcody) all the lto trans commands at once
2020-08-23check lto compilation statusJohn Ravi2-2/+21
2020-08-19Merge remote-tracking branch 'origin/master' into devel/lto-offloadJohn Ravi1994-162788/+186527
2020-08-19analyzer: fix ICE on deref_rvalue on SK_COMPOUND [PR96643]David Malcolm2-21/+31
gcc/analyzer/ChangeLog: PR analyzer/96643 * region-model.cc (region_model::deref_rvalue): Rather than attempting to handle all svalue kinds in the switch, only cover the special cases, and move symbolic-region handling to after the switch, thus implicitly handling the missing case SK_COMPOUND. gcc/testsuite/ChangeLog: PR analyzer/96643 * g++.dg/analyzer/pr96643.C: New test.
2020-08-19analyzer: fix ICE on folding vector 0 [PR96705]David Malcolm2-2/+11
gcc/analyzer/ChangeLog: * region-model-manager.cc PR analyzer/96705 (region_model_manager::maybe_fold_binop): Check that we have an integral type before calling build_int_cst. gcc/testsuite/ChangeLog: PR analyzer/96705 * gcc.dg/analyzer/pr96705.c: New test.
2020-08-19analyzer: fix ICE converting float to int [PR96699]David Malcolm2-0/+18
gcc/analyzer/ChangeLog: PR analyzer/96699 * region-model-manager.cc (region_model_manager::get_or_create_cast): Use FIX_TRUNC_EXPR for casting from REAL_TYPE to INTEGER_TYPE. gcc/testsuite/ChangeLog: PR analyzer/96699 * gcc.dg/analyzer/pr96699.c: New test.
2020-08-19rs6000, restrict bfloat convert intrinsic to Power 10. Fix BU_P10V macro ↵Carl Love3-322/+347
definitions. gcc/ChangeLog 2020-08-19 Carl Love <cel@us.ibm.com> * config/rs6000/rs6000-builtin.def (BU_P10V_0, BU_P10V_1, BU_P10V_2, BU_P10V_3): Rename BU_P10V_VSX_0, BU_P10V_VSX_1, BU_P10V_VSX_2, BU_P10V_VSX_3 respectively. (BU_P10V_4): Remove. (BU_P10V_AV_0, BU_P10V_AV_1, BU_P10V_AV_2, BU_P10V_AV_3, BU_P10V_AV_4): New definitions for Power 10 Altivec macros. (VSTRIBR, VSTRIHR, VSTRIBL, VSTRIHL, VSTRIBR_P, VSTRIHR_P, VSTRIBL_P, VSTRIHL_P, MTVSRBM, MTVSRHM, MTVSRWM, MTVSRDM, MTVSRQM, VEXPANDMB, VEXPANDMH, VEXPANDMW, VEXPANDMD, VEXPANDMQ, VEXTRACTMB, VEXTRACTMH, VEXTRACTMW, VEXTRACTMD, VEXTRACTMQ): Replace macro expansion BU_P10V_1 with BU_P10V_AV_1. (VCLRLB, VCLRRB, VCFUGED, VCLZDM, VCTZDM, VPDEPD, VPEXTD, VGNB, VCNTMBB, VCNTMBH, VCNTMBW, VCNTMBD): Replace macro expansion BU_P10V_2 with BU_P10V_AV_2. (VEXTRACTBL, VEXTRACTHL, VEXTRACTWL, VEXTRACTDL, VEXTRACTBR, VEXTRACTHR, VEXTRACTWR, VEXTRACTDR, VINSERTGPRBL, VINSERTGPRHL, VINSERTGPRWL, VINSERTGPRDL, VINSERTVPRBL, VINSERTVPRHL, VINSERTVPRWL, VINSERTGPRBR, VINSERTGPRHR, VINSERTGPRWR, VINSERTGPRDR, VINSERTVPRBR, VINSERTVPRHR, VINSERTVPRWR, VREPLACE_ELT_V4SI, VREPLACE_ELT_UV4SI, VREPLACE_ELT_V2DF, VREPLACE_ELT_V4SF, VREPLACE_ELT_V2DI, VREPLACE_ELT_UV2DI, VREPLACE_UN_V4SI, VREPLACE_UN_UV4SI, VREPLACE_UN_V4SF, VREPLACE_UN_V2DI, VREPLACE_UN_UV2DI, VREPLACE_UN_V2DF, VSLDB_V16QI, VSLDB_V8HI, VSLDB_V4SI, VSLDB_V2DI, VSRDB_V16QI, VSRDB_V8HI, VSRDB_V4SI, VSRDB_V2DI): Replace macro expansion BU_P10V_3 with BU_P10V_AV_3. (VXXSPLTIW_V4SI, VXXSPLTIW_V4SF, VXXSPLTID): Replace macro expansion BU_P10V_1 with BU_P10V_AV_1. (XXGENPCVM_V16QI, XXGENPCVM_V8HI, XXGENPCVM_V4SI, XXGENPCVM_V2DI): Replace macro expansion BU_P10V_2 with BU_P10V_VSX_2. (VXXSPLTI32DX_V4SI, VXXSPLTI32DX_V4SF, VXXBLEND_V16QI, VXXBLEND_V8HI, VXXBLEND_V4SI, VXXBLEND_V2DI, VXXBLEND_V4SF, VXXBLEND_V2DF): Replace macor expansion BU_P10V_3 with BU_P10V_VSX_3. (XXEVAL, VXXPERMX): Replace macro expansion BU_P10V_4 with BU_P10V_VSX_4. (XVCVBF16SP, XVCVSPBF16): Replace macro expansion BU_VSX_1 with BU_P10V_VSX_1. Also change MISC to CONST. * config/rs6000/rs6000-c.c: (P10_BUILTIN_VXXPERMX): Replace with P10V_BUILTIN_VXXPERMX. (P10_BUILTIN_VCLRLB, P10_BUILTIN_VCLRLB, P10_BUILTIN_VCLRRB, P10_BUILTIN_VGNB, P10_BUILTIN_XXEVAL, P10_BUILTIN_VXXPERMX, P10_BUILTIN_VEXTRACTBL, P10_BUILTIN_VEXTRACTHL, P10_BUILTIN_VEXTRACTWL, P10_BUILTIN_VEXTRACTDL, P10_BUILTIN_VINSERTGPRHL, P10_BUILTIN_VINSERTGPRWL, P10_BUILTIN_VINSERTGPRDL, P10_BUILTIN_VINSERTVPRBL, P10_BUILTIN_VINSERTVPRHL, P10_BUILTIN_VEXTRACTBR, P10_BUILTIN_VEXTRACTHR, P10_BUILTIN_VEXTRACTWR, P10_BUILTIN_VEXTRACTDR, P10_BUILTIN_VINSERTGPRBR, P10_BUILTIN_VINSERTGPRHR, P10_BUILTIN_VINSERTGPRWR, P10_BUILTIN_VINSERTGPRDR, P10_BUILTIN_VINSERTVPRBR, P10_BUILTIN_VINSERTVPRHR, P10_BUILTIN_VINSERTVPRWR, P10_BUILTIN_VREPLACE_ELT_UV4SI, P10_BUILTIN_VREPLACE_ELT_V4SI, P10_BUILTIN_VREPLACE_ELT_UV2DI, P10_BUILTIN_VREPLACE_ELT_V2DI, P10_BUILTIN_VREPLACE_ELT_V2DF, P10_BUILTIN_VREPLACE_UN_UV4SI, P10_BUILTIN_VREPLACE_UN_V4SI, P10_BUILTIN_VREPLACE_UN_V4SF, P10_BUILTIN_VREPLACE_UN_UV2DI, P10_BUILTIN_VREPLACE_UN_V2DI, P10_BUILTIN_VREPLACE_UN_V2DF, P10_BUILTIN_VSLDB_V16QI, P10_BUILTIN_VSLDB_V16QI, P10_BUILTIN_VSLDB_V8HI, P10_BUILTIN_VSLDB_V4SI, P10_BUILTIN_VSLDB_V2DI, P10_BUILTIN_VXXSPLTIW_V4SI, P10_BUILTIN_VXXSPLTIW_V4SF, P10_BUILTIN_VXXSPLTID, P10_BUILTIN_VXXSPLTI32DX_V4SI, P10_BUILTIN_VXXSPLTI32DX_V4SF, P10_BUILTIN_VXXBLEND_V16QI, P10_BUILTIN_VXXBLEND_V8HI, P10_BUILTIN_VXXBLEND_V4SI, P10_BUILTIN_VXXBLEND_V2DI, P10_BUILTIN_VXXBLEND_V4SF, P10_BUILTIN_VXXBLEND_V2DF, P10_BUILTIN_VSRDB_V16QI, P10_BUILTIN_VSRDB_V8HI, P10_BUILTIN_VSRDB_V4SI, P10_BUILTIN_VSRDB_V2DI, P10_BUILTIN_VSTRIBL, P10_BUILTIN_VSTRIHL, P10_BUILTIN_VSTRIBL_P, P10_BUILTIN_VSTRIHL_P, P10_BUILTIN_VSTRIBR, P10_BUILTIN_VSTRIHR, P10_BUILTIN_VSTRIBR_P, P10_BUILTIN_VSTRIHR_P, P10_BUILTIN_MTVSRBM, P10_BUILTIN_MTVSRHM, P10_BUILTIN_MTVSRWM, P10_BUILTIN_MTVSRDM, P10_BUILTIN_MTVSRQM, P10_BUILTIN_VCNTMBB, P10_BUILTIN_VCNTMBH, P10_BUILTIN_VCNTMBW, P10_BUILTIN_VCNTMBD, P10_BUILTIN_VEXPANDMB, P10_BUILTIN_VEXPANDMH, P10_BUILTIN_VEXPANDMW, P10_BUILTIN_VEXPANDMD, P10_BUILTIN_VEXPANDMQ, P10_BUILTIN_VEXTRACTMB, P10_BUILTIN_VEXTRACTMH, P10_BUILTIN_VEXTRACTMW, P10_BUILTIN_VEXTRACTMD, P10_BUILTIN_VEXTRACTMQ, P10_BUILTIN_XVTLSBB_ZEROS, P10_BUILTIN_XVTLSBB_ONES): Replace with P10V_BUILTIN_VCLRLB, P10V_BUILTIN_VCLRLB, P10V_BUILTIN_VCLRRB, P10V_BUILTIN_VGNB, P10V_BUILTIN_XXEVAL, P10V_BUILTIN_VXXPERMX, P10V_BUILTIN_VEXTRACTBL, P10V_BUILTIN_VEXTRACTHL, P10V_BUILTIN_VEXTRACTWL, P10V_BUILTIN_VEXTRACTDL, P10V_BUILTIN_VINSERTGPRHL, P10V_BUILTIN_VINSERTGPRWL, P10V_BUILTIN_VINSERTGPRDL, P10V_BUILTIN_VINSERTVPRBL,P10V_BUILTIN_VINSERTVPRHL, P10V_BUILTIN_VEXTRACTBR, P10V_BUILTIN_VEXTRACTHR P10V_BUILTIN_VEXTRACTWR, P10V_BUILTIN_VEXTRACTDR, P10V_BUILTIN_VINSERTGPRBR, P10V_BUILTIN_VINSERTGPRHR, P10V_BUILTIN_VINSERTGPRWR, P10V_BUILTIN_VINSERTGPRDR, P10V_BUILTIN_VINSERTVPRBR, P10V_BUILTIN_VINSERTVPRHR, P10V_BUILTIN_VINSERTVPRWR, P10V_BUILTIN_VREPLACE_ELT_UV4SI, P10V_BUILTIN_VREPLACE_ELT_V4SI, P10V_BUILTIN_VREPLACE_ELT_UV2DI, P10V_BUILTIN_VREPLACE_ELT_V2DI, P10V_BUILTIN_VREPLACE_ELT_V2DF, P10V_BUILTIN_VREPLACE_UN_UV4SI, P10V_BUILTIN_VREPLACE_UN_V4SI, P10V_BUILTIN_VREPLACE_UN_V4SF, P10V_BUILTIN_VREPLACE_UN_UV2DI, P10V_BUILTIN_VREPLACE_UN_V2DI, P10V_BUILTIN_VREPLACE_UN_V2DF, P10V_BUILTIN_VSLDB_V16QI, P10V_BUILTIN_VSLDB_V16QI, P10V_BUILTIN_VSLDB_V8HI, P10V_BUILTIN_VSLDB_V4SI, P10V_BUILTIN_VSLDB_V2DI, P10V_BUILTIN_VXXSPLTIW_V4SI, P10V_BUILTIN_VXXSPLTIW_V4SF, P10V_BUILTIN_VXXSPLTID, P10V_BUILTIN_VXXSPLTI32DX_V4SI, P10V_BUILTIN_VXXSPLTI32DX_V4SF, P10V_BUILTIN_VXXBLEND_V16QI, P10V_BUILTIN_VXXBLEND_V8HI, P10V_BUILTIN_VXXBLEND_V4SI, P10V_BUILTIN_VXXBLEND_V2DI, P10V_BUILTIN_VXXBLEND_V4SF, P10V_BUILTIN_VXXBLEND_V2DF, P10V_BUILTIN_VSRDB_V16QI, P10V_BUILTIN_VSRDB_V8HI, P10V_BUILTIN_VSRDB_V4SI, P10V_BUILTIN_VSRDB_V2DI, P10V_BUILTIN_VSTRIBL, P10V_BUILTIN_VSTRIHL, P10V_BUILTIN_VSTRIBL_P, P10V_BUILTIN_VSTRIHL_P, P10V_BUILTIN_VSTRIBR, P10V_BUILTIN_VSTRIHR, P10V_BUILTIN_VSTRIBR_P, P10V_BUILTIN_VSTRIHR_P, P10V_BUILTIN_MTVSRBM, P10V_BUILTIN_MTVSRHM, P10V_BUILTIN_MTVSRWM, P10V_BUILTIN_MTVSRDM, P10V_BUILTIN_MTVSRQM, P10V_BUILTIN_VCNTMBB, P10V_BUILTIN_VCNTMBH, P10V_BUILTIN_VCNTMBW, P10V_BUILTIN_VCNTMBD, P10V_BUILTIN_VEXPANDMB, P10V_BUILTIN_VEXPANDMH, P10V_BUILTIN_VEXPANDMW, P10V_BUILTIN_VEXPANDMD, P10V_BUILTIN_VEXPANDMQ, P10V_BUILTIN_VEXTRACTMB, P10V_BUILTIN_VEXTRACTMH, P10V_BUILTIN_VEXTRACTMW, P10V_BUILTIN_VEXTRACTMD, P10V_BUILTIN_VEXTRACTMQ, P10V_BUILTIN_XVTLSBB_ZEROS, P10V_BUILTIN_XVTLSBB_ONES respectively. * config/rs6000/rs6000-call.c: Ditto above, change P10_BUILTIN_name to P10V_BUILTIN_name. (P10_BUILTIN_XVCVSPBF16, P10_BUILTIN_XVCVBF16SP): Change to P10V_BUILTIN_XVCVSPBF16, P10V_BUILTIN_XVCVBF16SP respectively.
2020-08-19rs6000: Enable more sibcalls when TOC is not preservedBill Schmidt2-21/+28
A function compiled with the PC-relative addressing model does not require r2 to contain a TOC pointer, and does not guarantee that r2 will be preserved for its caller. Such a function can make sibcalls without restriction based on TOC preservation rules. However, a caller that does preserve r2 cannot make a sibcall to a callee that does not. 2020-08-19 Bill Schmidt <wschmidt@linux.ibm.com> gcc/ * config/rs6000/rs6000-logue.c (rs6000_decl_ok_for_sibcall): Sibcalls are always legal when the caller doesn't preserve r2. gcc/testsuite/ * gcc.target/powerpc/pcrel-sibcall-1.c: Adjust.
2020-08-19i386: Use code_for_ instead of gen_ for parameterized names more.Uros Bizjak1-17/+19
Some builtins are better expanded to patterns with parametrized names via code_for_ than gen_ helpers. No functional changes. 2020-08-19 Uroš Bizjak <ubizjak@gmail.com> gcc/ChangeLog: * config/i386/i386-expand.c (ix86_expand_builtin) [case IX86_BUILTIN_ENQCMD, case IX86_BUILTIN_ENQCMDS]: Rewrite expansion to use code_for_enqcmd. [case IX86_BUILTIN_WRSSD, case IX86_BUILTIN_WRSSQ]: Rewrite expansion to use code_for_wrss. [case IX86_BUILTIN_WRUSSD, case IX86_BUILTIN_WRUSSD]: Rewrite expansion to use code_for_wrss.
2020-08-19tree-optimization/94234 - add pattern for ptr-diff on addresses with same offsetFeng Xue2-0/+18
2020-08-19 Feng Xue <fxue@os.amperecomputing.com> gcc/ PR tree-optimization/94234 * match.pd ((PTR_A + OFF) - (PTR_B + OFF)) -> (PTR_A - PTR_B): New simplification. gcc/testsuite/ PR tree-optimization/94234 * gcc.dg/pr94234-1.c: New test.
2020-08-19x86: Detect Rocket Lake and Alder LakeH.J. Lu1-0/+10
From arch/x86/include/asm/intel-family.h on Linux kernel master branch: #define INTEL_FAM6_ROCKETLAKE 0xA7 #define INTEL_FAM6_ALDERLAKE 0x97 * common/config/i386/cpuinfo.h (get_intel_cpu): Detect Rocket Lake and Alder Lake.
2020-08-19AArch64: Remove "fndecl && TREE_PUBLIC (fndecl)" in aarch64_init_cumulative_argsPeixin Qiao2-1/+11
This check will prevent the function type check of static funtion or calling via a funtion pointer. The function type should be checked no matter if the function has external linkage. gcc/ChangeLog: * config/aarch64/aarch64.c (aarch64_init_cumulative_args): Remove "fndecl && TREE_PUBLIC (fndecl)" check since it prevents the funtion type check when calling via a function pointer or when calling a static function. gcc/testsuite/ChangeLog: * gcc.target/aarch64/mgeneral-regs_7.c: New test.
2020-08-19testsuite: require c99 runtime for trigonometric optimisation testsPat Bernardi3-1/+4
A number of optimisation that simplify trigonometric expressions are only performed when the compiler knows the target has a C99 libm available. Since targets like *-elf may not have such a libm, a C99 runtime requirement is added to these tests. 2020-08-19 Pat Bernardi <bernardi@adacore.com> gcc/testsuite/ChangeLog * gcc.dg/sinatan-2.c: Add dg-require-effective-target c99_runtime. * gcc.dg/sinhovercosh-1.c: Likewise. * gcc.dg/tanhbysinh.c: Likewise.
2020-08-19[testsuite, nvptx] Add effective target sync_int_long_stackTom de Vries2-2/+14
The nvptx target currently doesn't support effective target sync_int_long, although it has support for 32-bit and 64-bit atomic. When enabling sync_int_long for nvptx, we run into a failure in gcc.dg/pr86314.c: ... nvptx-run: error getting kernel result: operation not supported on \ global/shared address space ... due to a ptx restriction: accesses to local memory are illegal, and the test-case does an atomic operation on a stack address, which is mapped to local memory. Fix this by adding a target sync_int_long_stack, wich returns false for nvptx, which can be used to mark test-cases that require sync_int_long support for stack addresses. Build on nvptx and tested with make check-gcc. gcc/testsuite/ChangeLog: PR target/96494 * lib/target-supports.exp (check_effective_target_sync_int_long): Return 1 for nvptx. (check_effective_target_sync_int_long_stack): New proc. * gcc.dg/pr86314.c: Require effective target sync_int_long_stack.
2020-08-18options: Make --help= see overridden valuesKewen Lin1-2/+8
Options "-Q --help=params" don't show the final values after target option overriding, instead it emits the default values in params.opt (without any explicit param settings). This patch makes it see overridden values. gcc/ChangeLog: * opts-global.c (decode_options): Call target_option_override_hook before it prints for --help=*.
2020-08-18analyzer: consider initializers for globals [PR96651]David Malcolm7-29/+224
PR analyzer/96651 reports a false positive in which a global that can't have been touched yet is checked in "main". The analyzer fails to reject code paths in which the initial value of the global makes the path condition impossible. This patch detects cases where the code path begins at the entrypoint of "main", and extracts values from initializers for globals that can't have been touched yet, rather than using a symbolic "INIT_VAL(REG)", fixing the false positive. gcc/analyzer/ChangeLog: PR analyzer/96651 * region-model.cc (region_model::called_from_main_p): New. (region_model::get_store_value): Move handling for globals into... (region_model::get_initial_value_for_global): ...this new function, and add logic for extracting values from decl initializers. * region-model.h (decl_region::get_svalue_for_constructor): New decl. (decl_region::get_svalue_for_initializer): New decl. (region_model::called_from_main_p): New decl. (region_model::get_initial_value_for_global): New. * region.cc (decl_region::maybe_get_constant_value): Move logic for getting an svalue from a CONSTRUCTOR node to... (decl_region::get_svalue_for_constructor): ...this new function. (decl_region::get_svalue_for_initializer): New. * store.cc (get_svalue_for_ctor_val): Rewrite in terms of region_model::get_rvalue. * store.h (binding_cluster::get_map): New accessor. gcc/testsuite/ChangeLog: PR analyzer/96651 * gcc.dg/analyzer/pr96651-1.c: New test. * gcc.dg/analyzer/pr96651-2.c: New test.
2020-08-18analyzer: fix ICE with negative bit offsets [PR96648]David Malcolm2-1/+38
PR analyzer/96648 reports an ICE within get_field_at_bit_offset due to a negative bit offset, arising due to pointer arithmetic. This patch replaces an assertion with handling for this case, fixing the ICE. gcc/analyzer/ChangeLog: PR analyzer/96648 * region.cc (get_field_at_bit_offset): Gracefully handle negative values for bit_offset. gcc/testsuite/ChangeLog: PR analyzer/96648 * gcc.dg/analyzer/pr96648.c: New test.
2020-08-19Daily bump.GCC Administrator8-1/+204
2020-08-18c++: alias template template_info settingNathan Sidwell2-8/+25
During the construction of alias templates we can alter its template_info. This is really weird, because that's morally immutable data. In this case it's ok, but let's not create a duplicate template_info, and add asserts to make sure it is changing in exactly the way we expect. gcc/cp/ * cp-tree.h (SET_TYPE_TEMPLTE_INFO): Do not deal with ALIAS templates. * pt.c (lookup_template_class_1): Special-case alias template template_info setting.
2020-08-18rs6000: Rename instruction xvcvbf16sp to xvcvbf16spnPeter Bergner5-8/+8
The xvcvbf16sp mnemonic, which was just added in ISA 3.1 has been renamed to xvcvbf16spn, to make it consistent with the other non-signaling conversion instructions which all end with "n". The only use of this instruction is in an MMA conversion built-in function, so there is little to no compatibility issue. gcc/ * config/rs6000/rs6000-builtin.def (BU_VSX_1): Rename xvcvbf16sp to xvcvbf16spn. * config/rs6000/rs6000-call.c (builtin_function_type): Likewise. * config/rs6000/vsx.md: Likewise. * doc/extend.texi: Likewise. gcc/testsuite/ * gcc.target/powerpc/mma-builtin-3.c: Rename xvcvbf16sp to xvcvbf16spn.
2020-08-18c++: Rewrite members for all deduction guides. [PR96199]Jason Merrill4-4/+71
After the last patch, it occurred to me that we could run into the specialization issue with non-alias deduction guides as well, so this patch extends the rewriting to C++17 mode. Doing this revealed that we weren't properly pushing into class scope for normalization. gcc/cp/ChangeLog: PR c++/96199 * pt.c (tsubst_aggr_type): Rewrite in C++17, too. (maybe_dependent_member_ref): Likewise. (build_deduction_guide): Re-substitute template parms. * cp-tree.h (struct push_nested_class_guard): New. * constraint.cc (get_normalized_constraints_from_decl): Use it. gcc/testsuite/ChangeLog: PR c++/96199 * g++.dg/cpp1z/class-deduction-spec1.C: New test.
2020-08-18c++: Handle enumerator in C++20 alias CTAD. [PR96199]Jason Merrill2-0/+87
To form a deduction guide for an alias template, we substitute the template arguments from the pattern into the deduction guide for the underlying class. In the case of B(A1<X>), that produces B(A1<B<T,1>::X>) -> B<T,1>. But since an enumerator doesn't have its own template info, and B<T,1> is a dependent scope, trying to look up B<T,1>::X fails and we crash. So we need to produce a SCOPE_REF instead. And trying to use the members of the template class is wrong for other members, as well, as it gives a nonsensical result if the class is specialized. gcc/cp/ChangeLog: PR c++/96199 * pt.c (maybe_dependent_member_ref): New. (tsubst_copy) [CONST_DECL]: Use it. [VAR_DECL]: Likewise. (tsubst_aggr_type): Handle nested type. gcc/testsuite/ChangeLog: PR c++/96199 * g++.dg/cpp2a/class-deduction-alias4.C: New test.
2020-08-18PR fortran/96613,96686 - Fix type/kind issues, temporaries evaluating MIN/MAXHarald Anlauf6-8/+69
When evaluating functions of the MIN/MAX variety inline, use a temporary of appropriate type and kind, and convert to the result type at the end. In the case of allowing for the GNU extensions to MIN/MAX, derive the result kind consistently during simplificaton. Furthermore, the Fortran standard requires type and kind of arguments to the MIN/MAX intrinsics to all have the same type and kind. While a GNU extension accepts kind differences for integer and real arguments which seems to have been used in legacy code, there is no reason to allow different character kinds. We now reject the latter unconditionally. gcc/fortran/ChangeLog: * check.c (check_rest): Reject MIN/MAX character arguments of different kind. * simplify.c (min_max_choose): The simplification result shall have the highest kind value of the arguments. * trans-intrinsic.c (gfc_conv_intrinsic_minmax): Choose type and kind of intermediate by looking at all arguments, not the result. gcc/testsuite/ChangeLog: * gfortran.dg/minmax_char_3.f90: New test. * gfortran.dg/min_max_kind.f90: New test. * gfortran.dg/pr96613.f90: New test.
2020-08-18rs6000: unaligned VSX in memcpy/memmove expansionAaron Sawdey3-16/+105
This patch adds a few new instructions to inline expansion of memcpy/memmove. Generation of all these are controlled by the option -mblock-ops-unaligned-vsx which is set on by default if the target has TARGET_EFFICIENT_UNALIGNED_VSX. * unaligned vsx load/store (V2DImode) * unaligned vsx pair load/store (POImode) which is also controlled by -mblock-ops-vector-pair in case it is not wanted at some point. The default for -mblock-ops-vector-pair is for it to be on if the target has TARGET_MMA and TARGET_EFFICIENT_UNALIGNED_VSX. This is redundant, but nice for the future to clearly specify what is required. * unaligned vsx lxvl/stxvl but generally only to do the remainder of a copy/move we stated with some vsx loads/stores, and also prefer to use lb/lh/lw/ld if the remainder is 1/2/4/8 bytes. Testing of this is actually accomplished by gcc.dg/memcmp-1.c which does two memcpy() for each memcmp(). If the memcpy() calls don't do the right thing then the memcmp() will fail unexpectedly. gcc/ChangeLog: * config/rs6000/rs6000-string.c (gen_lxvl_stxvl_move): Helper function. (expand_block_move): Add lxvl/stxvl, vector pair, and unaligned VSX. * config/rs6000/rs6000.c (rs6000_option_override_internal): Default value for -mblock-ops-vector-pair. * config/rs6000/rs6000.opt: Add -mblock-ops-vector-pair.
2020-08-18Decouple adjust_range_from_scev from vr_values and value_range_equiv.Aldy Hernandez2-89/+103
gcc/ChangeLog: * vr-values.c (check_for_binary_op_overflow): Change type of store to range_query. (vr_values::adjust_range_with_scev): Abstract most of the code... (range_of_var_in_loop): ...here. Remove value_range_equiv uses. (simplify_using_ranges::simplify_using_ranges): Change type of store to range_query. * vr-values.h (class range_query): New. (class simplify_using_ranges): Use range_query. (class vr_values): Add OVERRIDE to get_value_range. (range_of_var_in_loop): New.
2020-08-18PR middle-end/96665 - memcmp of a constant string not foldedMartin Sebor2-8/+91
Related: PR middle-end/78257 - missing memcmp optimization with constant arrays gcc/ChangeLog: PR middle-end/96665 PR middle-end/78257 * expr.c (convert_to_bytes): Replace statically allocated buffer with a dynamically allocated one of sufficient size. gcc/testsuite/ChangeLog: PR middle-end/96665 PR middle-end/78257 * gcc.dg/memcmp-5.c: New test.
2020-08-18Fix PR tree-optimization/96670 - ICE on memchr with an empty initializer.Martin Sebor3-1/+89
gcc/ChangeLog: PR tree-optimization/96670 PR middle-end/78257 * gimple-fold.c (gimple_fold_builtin_memchr): Call byte_representation to get it, not string_constant. gcc/testsuite/ChangeLog: PR tree-optimization/96670 * gcc.dg/memchr-2.c: New test. * gcc.dg/memcmp-6.c: New test.
2020-08-18doc: add return type for functions in gimple.texiHu Jiangping1-3/+3
gcc/ * doc/gimple.texi (gimple_debug_begin_stmt_p): Add return type. (gimple_debug_inline_entry_p, gimple_debug_nonbind_marker_p): Likewise.
2020-08-18Update native_encode_expr description.Martin Sebor1-5/+6
gcc/ChangeLog: * fold-const.c (native_encode_expr): Update comment.
2020-08-18i386: Rewrite restore_stack_nonlocal expander [PR96536].Uros Bizjak1-72/+43
-fcf-protection code in restore_stack_nonlocal uses a branch based on a clobber result. The patch adds missing compare and completely rewrites the expander to use high-level functions in RTL construction. 2020-08-18 Uroš Bizjak <ubizjak@gmail.com> gcc/ChangeLog: PR target/96536 * config/i386/i386.md (restore_stack_nonlocal): Add missing compare RTX. Rewrite expander to use high-level functions in RTL construction.
2020-08-18New tests for PR rtl-optimization/96298.Roger Sayle2-0/+36
Tests to confirm PR rtl-optimization is now fixed, remains so. 2020-08-18 Roger Sayle <roger@nextmovesoftware.com> Zdenek Sojka <zsojka@seznam.cz> gcc/testsuite/ChangeLog PR rtl-optimization/96298 * gcc.dg/pr96298.c: New test. * gcc.target/i386/pr96298.c: New test.
2020-08-18c++: Move hidden-lambda entity lookup checkingNathan Sidwell1-12/+10
Hidden lambda entities only occur in block and class scopes. There's no need to check for them on every lookup. So moving that particular piece of validation to lookup_name_1, which cares. Also reordered the namespace and type checking, as that is also simpler. gcc/cp/ * name-lookup.c (qualify_lookup): Drop lambda checking here. Reorder namespace & type checking. (lookup_name_1): Do hidden lambda checking here.
2020-08-18d: Fix ICE Segmentation fault during RTL pass: expand on armhf/armel/s390xIain Buclaw4-6/+92
gcc/d/ChangeLog: PR d/96301 * decl.cc (DeclVisitor::visit (FuncDeclaration *)): Only return non-trivial structs by invisible reference. gcc/testsuite/ChangeLog: PR d/96301 * gdc.dg/pr96301a.d: New test. * gdc.dg/pr96301b.d: New test. * gdc.dg/pr96301c.d: New test.
2020-08-18Don't use pinsr/pextr for struct initialization/extraction.liuhongt2-2/+81
gcc/ PR target/96562 PR target/93897 * config/i386/i386-expand.c (ix86_expand_pinsr): Don't use pinsr for TImode. (ix86_expand_pextr): Don't use pextr for TImode. gcc/testsuite/ * gcc.target/i386/pr96562-1.c: New test.
2020-08-18c: Fix -Wunused-but-set-* warning with _Generic [PR96571]Jakub Jelinek2-6/+46
The following testcase shows various problems with -Wunused-but-set* warnings and _Generic construct. I think it is best to treat the selector and the ignored expressions as (potentially) read, because when they are parsed, the vars in there are already marked as TREE_USED. 2020-08-18 Jakub Jelinek <jakub@redhat.com> PR c/96571 * c-parser.c (c_parser_generic_selection): Change match_found from bool to int, holding index of the match. Call mark_exp_read on the selector expression and on expressions other than the selected one. * gcc.dg/Wunused-var-4.c: New test.
2020-08-18Adjust testcase.liuhongt1-7/+3
Since This testcase is used to check generation of AVX512 vector comparison, scan-assembler for vmov instruction could be deleted, also -mprefer-vector-width=512 is added to avoid impact of different default arch/tune of GCC. gcc/testsuite PR target/96574 * gcc.target/i386/pr92865-1.c: Adjust testcase.
2020-08-17analyzer: fix name of local in region_model::get_rvalue_1David Malcolm1-2/+2
gcc/analyzer/ChangeLog: * region-model.cc (region_model::get_rvalue_1): Fix name of local.
2020-08-17analyzer: fix ICE on unhandled tree codes in get_rvalue_1 [PR96641]David Malcolm2-1/+19
The old implementation of region_model::get_rvalue_1 gracefully handled tree codes it didn't understand, returning "UNKNOWN", whereas the new implementation (r11-2694-g808f4dfeb3a95f50f15e71148e5c1067f90a126d) had an assertion left over from development, leading to ICEs. This patch restores the old behavior for these cases. gcc/analyzer/ChangeLog: PR analyzer/96641 * region-model.cc (region_model::get_rvalue_1): Handle unrecognized tree codes by returning "UNKNOWN. gcc/testsuite/ChangeLog: PR analyzer/96641 * g++.dg/analyzer/pr96641.C: New test.
2020-08-17analyzer: fix ICE on unhandled tree codes in gassign [PR96640]David Malcolm1-2/+20
PR analyzer/96640 reports a ICE within region_model::on_assignment when failing to handle a WIDEN_MULT_EVEN_EXPR, and various other tree codes. The old implementation of region_model::on_assignment gracefully handled tree codes it didn't understand, returning "UNKNOWN", whereas the new implementation (r11-2694-g808f4dfeb3a95f50f15e71148e5c1067f90a126d) had a "sorry_at" and an assertion left over from development, leading to ICEs. This patch restores the old behavior for these cases, and marks various vector operations as leading to unknown results. gcc/analyzer/ChangeLog: PR analyzer/96640 * region-model.cc (region_model::get_gassign_result): Handle various VEC_* tree codes by returning UNKNOWN. (region_model::on_assignment): Handle unrecognized tree codes by setting lhs to an unknown value, rather than issuing a "sorry" and asserting.
2020-08-18Daily bump.GCC Administrator5-1/+105
2020-08-17compiler: export thunks referenced by inline functionsIan Lance Taylor3-9/+10
The test case is https://golang.org/cl/248637. Fixes golang/go#40252 Reviewed-on: https://go-review.googlesource.com/c/gofrontend/+/248638
2020-08-17analyzer: fix ICE on NULL dereference [PR96644]David Malcolm2-2/+26
gcc/analyzer/ChangeLog: PR analyzer/96644 * region-model-manager.cc (get_region_for_unexpected_tree_code): Handle ctxt being NULL. gcc/testsuite/ChangeLog: PR analyzer/96644 * gcc.dg/analyzer/pr96644.c: New test.
2020-08-17analyzer: fix ICE due to NULL type [PR96639]David Malcolm2-1/+11
gcc/analyzer/ChangeLog: PR analyzer/96639 * region.cc (region::get_subregions_for_binding): Check for "type" being NULL. gcc/testsuite/ChangeLog: PR analyzer/96639 * gcc.dg/analyzer/pr96639.c: New test.
2020-08-17analyzer: handle &STRING_CST in constant pool initializers [PR96642]David Malcolm2-3/+28
In r11-2708-g2867118ddda9b56d991c16022f7d3d634ed08313 I added support to the analyzer for initialization from var_decls in the global constant pool. However, that commit didn't support initialization from ADDR_EXPR of a STRING_CST leading to an ICE seen in data-model-1.c and pr94639.c on arm and powerpc64 at least, and as PR analyzer/96642 on x86_64 at least. This patch adds support for such initializers, fixing the ICE. gcc/analyzer/ChangeLog: PR analyzer/96642 * store.cc (get_svalue_for_ctor_val): New. (binding_map::apply_ctor_to_region): Call it. gcc/testsuite/ChangeLog: PR analyzer/96642 * gcc.dg/analyzer/pr96642.c: New test.
2020-08-17i386: Use parametrized pattern names some more.Uros Bizjak6-68/+52
Use parameterized pattern names to simplify calling of named patterns. 2020-08-15 Uroš Bizjak <ubizjak@gmail.com> gcc/ChangeLog: * config/i386/i386-builtin.def (__builtin_ia32_bextri_u32) (__builtin_ia32_bextri_u64): Use CODE_FOR_nothing. * config/i386/i386.md (@tbm_bextri_<mode>): Implement as parametrized name pattern. (@rdrand<mode>): Ditto. (@rdseed<mode>): Ditto. * config/i386/i386-expand.c (ix86_expand_builtin) [case IX86_BUILTIN_BEXTRI32, case IX86_BUILTIN_BEXTRI64]: Update for parameterized name patterns. [case IX86_BUILTIN_RDRAND16_STEP, case IX86_BUILTIN_RDRAND32_STEP] [case IX86_BUILTIN_RDRAND64_STEP]: Ditto. [case IX86_BUILTIN_RDSEED16_STEP, case IX86_BUILTIN_RDSEED32_STEP] [case IX86_BUILTIN_RDSEED64_STEP]: Ditto. gcc/testsuite/ChangeLog: * gcc.target/i386/rdrand-1.c (dg-final): Update scan string. * gcc.target/i386/rdrand-2.c (dg-final): Ditto. * gcc.target/i386/rdrand-3.c (dg-final): Ditto.
2020-08-17opnemp: add static assert for clause_names.Martin Liska1-6/+2
gcc/fortran/ChangeLog: * openmp.c (resolve_omp_clauses): Add static assert for OMP_LIST_NUM and size of clause_names array. Remove check that is always true.
2020-08-17Add statement context to get_value_range.Aldy Hernandez2-32/+35
This is in line with the statement context that we have for get_value() in the substitute_and_fold_engine class. gcc/ChangeLog: * vr-values.c (vr_values::get_value_range): Add stmt param. (vr_values::extract_range_from_comparison): Same. (vr_values::extract_range_from_assignment): Pass stmt to extract_range_from_comparison. (vr_values::adjust_range_with_scev): Pass stmt to get_value_range. (simplify_using_ranges::vrp_evaluate_conditional): Add stmt param. Pass stmt to get_value_range. (simplify_using_ranges::vrp_visit_cond_stmt): Pass stmt to get_value_range. (simplify_using_ranges::simplify_abs_using_ranges): Same. (simplify_using_ranges::simplify_div_or_mod_using_ranges): Same. (simplify_using_ranges::simplify_bit_ops_using_ranges): Same. (simplify_using_ranges::simplify_cond_using_ranges_1): Same. (simplify_using_ranges::simplify_switch_using_ranges): Same. (simplify_using_ranges::simplify_float_conversion_using_ranges): Same. * vr-values.h (class vr_values): Add stmt arg to vrp_evaluate_conditional_warnv_with_ops. Add stmt arg to extract_range_from_comparison and get_value_range. (simplify_using_ranges::get_value_range): Add stmt arg.
2020-08-17openmp: fix UBSAN error at gcc/fortran/openmp.c:4737Martin Liska1-1/+2
Since 21cfe724cbdc30612bf1ef59b26f19ada2210832 there's a new OMP_LIST_NONTEMPORAL value, but it was missing in resolve_omp_clauses static array that is defined at the function beginning: ./xgcc -B. /home/marxin/Programming/gcc/gcc/testsuite/gfortran.dg/gomp/nontemporal-1.f90 -fopenmp -c ../../gcc/fortran/openmp.c:4737:28: runtime error: index 21 out of bounds for type 'char *[21]' #0 0xbdb956 in resolve_omp_clauses ../../gcc/fortran/openmp.c:4737 #1 0xbeb076 in resolve_omp_do ../../gcc/fortran/openmp.c:6139 #2 0xbf029a in gfc_resolve_omp_directive(gfc_code*, gfc_namespace*) ../../gcc/fortran/openmp.c:6792 #3 0xcb6363 in gfc_resolve_code(gfc_code*, gfc_namespace*) ../../gcc/fortran/resolve.c:12185 #4 0xcef8cf in resolve_codes ../../gcc/fortran/resolve.c:17303 gcc/fortran/ChangeLog: * openmp.c (resolve_omp_clauses): Add NONTEMPORAL to clause names.
2020-08-17Force ENDBR immediate into memory.liuhongt3-0/+235
gcc/ PR target/96350 * config/i386/i386.c (ix86_legitimate_constant_p): Return false for ENDBR immediate. (ix86_legitimate_address_p): Ditto. * config/i386/predicates.md (x86_64_immediate_operand): Exclude ENDBR immediate. (x86_64_zext_immediate_operand): Ditto. (x86_64_dwzext_immediate_operand): Ditto. (ix86_endbr_immediate_operand): New predicate. gcc/testsuite * gcc.target/i386/endbr_immediate.c: New test.
generated by cgit v1.1 at 2025-08-09 16:06:50 +0000