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11 daysRISC-V: Add pattern for vector-scalar widening floating-point addPaul-Antoine Arras12-3/+74
This pattern enables the combine pass (or late-combine, depending on the case) to merge a float_extend'ed vec_duplicate into a plus RTL instruction. Before this patch, we have four instructions, e.g.: fcvt.d.s fa0,fa0 vsetvli a5,zero,e64,m1,ta,ma vfmv.v.f v3,fa0 vfwadd.wv v1,v3,v2 After, we get only one: vfwadd.vf v1,v2,fa0 gcc/ChangeLog: * config/riscv/autovec-opt.md (*vfwadd_vf_<mode>): New pattern to combine float_extend + vec_duplicate + vfwadd.vv into vfwadd.vf. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c: Add vfwadd. * gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf_binop.h (DEF_VF_BINOP_WIDEN_CASE_0): Fix OP. * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwadd-run-1-f16.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwadd-run-1-f32.c: New test.
11 daysRISC-V: Adjust tt-ascalon-d8 branch costAnton Blanchard1-1/+1
If-conversion isn't being applied to this nbench code: #include <stdint.h> #define INTERNAL_FPF_PRECISION 4 typedef uint16_t u16; void ShiftMantLeft1(u16 *carry, u16 *mantissa) { int i; int new_carry; u16 accum; for(i=INTERNAL_FPF_PRECISION-1;i>=0;i--) { accum=mantissa[i]; new_carry=accum & 0x8000; accum=accum<<1; if(*carry) accum|=1; *carry=new_carry; mantissa[i]=accum; } return; } Bumping branch_cost from 3 to 4 triggers if-conversion, improving the nbench FP EMULATION result on Ascalon significantly. There's a risk that more aggressive use of conditional zero instructions will negatively impact workloads that predict well, but we haven't seen anything obvious. gcc/ChangeLog: * config/riscv/riscv.cc (tt_ascalon_d8_tune_info): Increase branch_cost from 3 to 4.
11 daystree-optimization/121830 - SLP cycle detection confused by nested cycleRichard Biener3-3/+16
The SLP reduc-index computation is confused by having an outer reduction inner loop nested cycle fed by another non-reduction nested cycle. Instead of undoing the unfortunate mixing of outer reduction inner cycles with general nested cycles the following instead distinguishes them by not setting STMT_VINFO_REDUC_DEF on the non-reduction nested cycles. PR tree-optimization/121830 * tree-vect-loop.cc (vect_analyze_scalar_cycles_1): Only set STMT_VINFO_REDUC_DEF on reductions. * tree-vect-slp.cc (vect_build_slp_tree_2): Identify reduction PHIs by a set STMT_VINFO_REDUC_DEF instead of their def type. * gcc.dg/vect/pr121830.c: New testcase.
11 daystree-optimization/121829 - bogus CFG with asm gotoRichard Biener2-15/+39
When the vectorizer removes a forwarder created earlier by split_edge it uses redirect_edge_pred for convenience and efficiency. That breaks down when the edge split is originating from an asm goto as that is a jump that needs adjustments from redirect_edge_and_branch. The following factores a simple vect_remove_forwarder handling this situation appropriately. PR tree-optimization/121829 * tree-vect-loop-manip.cc (vect_remove_forwarder): New function. (slpeel_tree_duplicate_loop_to_edge_cfg): Use it. * gcc.dg/torture/pr121829.c: New testcase.
11 daysdoc: Document the -folding option for -fdump-tree-* [PR114892]Alex Coplan1-0/+3
I noticed that the -fdump-tree-*-folding flag isn't documented in the Developer options section of invoke.texi; this patch fixes that. gcc/ChangeLog: PR tree-optimization/114892 * doc/invoke.texi (Developer Options): Document -folding option for -fdump-tree-*.
11 days[AutoFDO] Check count initialization to fix ICE with AutoFDOKugan Vivekanandarajah1-1/+2
Fix ICE with AutoFDO by adding initialization check before accessing IPA counts to avoid issues with uninitialized profile counts in self-recursive clone processing. gcc/ChangeLog: 2025-09-08 Kugan Vivekanandarajah <kvivekananda@nvidia.com> * ipa-cp.cc (gather_count_of_non_rec_edges): Check count initialization before adding to total. Signed-off-by: Kugan Vivekanandarajah <kvivekananda@nvidia.com>
11 daysRISC-V: Add pattern for vector-scalar single-width floating-point reverse subPaul-Antoine Arras17-0/+234
This pattern enables the combine pass (or late-combine, depending on the case) to merge a vec_duplicate into a minus RTL instruction. The vec_duplicate is the minuend operand. Before this patch, we have two instructions, e.g.: vfmv.v.f v2,fa0 vfsub.vv v1,v2,v1 After, we get only one: vfrsub.vf v1,v1,fa0 gcc/ChangeLog: * config/riscv/autovec-opt.md (*vfrsub_vf_<mode>): New pattern to combine vec_duplicate + vfsub.vv into vfrsub.vf. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c: Add vfrsub. * gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_data.h: Add data for vfrsub. * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfrsub-run-1-f16.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfrsub-run-1-f32.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfrsub-run-1-f64.c: New test.
11 daysRISC-V: Add pattern for vector-scalar single-width floating-point subPaul-Antoine Arras19-7/+239
This pattern enables the combine pass (or late-combine, depending on the case) to merge a vec_duplicate into a minus RTL instruction. The vec_duplicate is the subtrahend operand. Before this patch, we have two instructions, e.g.: vfmv.v.f v2,fa0 vfsub.vv v1,v1,v2 After, we get only one: vfsub.vf v1,v1,fa0 gcc/ChangeLog: * config/riscv/autovec-opt.md (*vfsub_vf_<mode>): New pattern to combine vec_duplicate + vfsub.vv into vfsub.vf. * config/riscv/vector.md (@pred_<optab><mode>_scalar): Allow VLS modes. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vls/floating-point-sub-2.c: Adjust scan dumps. * gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c: Add vfsub. * gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_data.h: Add data for vfsub. * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfsub-run-1-f16.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfsub-run-1-f32.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfsub-run-1-f64.c: New test.
11 daysRISC-V: Add pattern for vector-scalar single-width floating-point addPaul-Antoine Arras20-3/+236
This pattern enables the combine pass (or late-combine, depending on the case) to merge a vec_duplicate into a plus RTL instruction. Before this patch, we have two instructions, e.g.: vfmv.v.f v2,fa0 vfadd.vv v1,v1,v2 After, we get only one: vfadd.vf v1,v1,fa0 gcc/ChangeLog: * config/riscv/autovec-opt.md (*vfadd_vf_<mode>): New pattern to combine vec_duplicate + vfadd.vv into vfadd.vf. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vls/floating-point-add-2.c: Adjust scan dump. * gcc.target/riscv/rvv/autovec/vls/floating-point-add-3.c: Likewise. * gcc.target/riscv/rvv/autovec/vls/floating-point-sub-3.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c: Add vfadd. * gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_data.h: Add data for vfadd. * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfadd-run-1-f16.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfadd-run-1-f32.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfadd-run-1-f64.c: New test.
11 daysRISC-V: Add pattern for vector-scalar widening floating-point multiplyPaul-Antoine Arras14-6/+139
This pattern enables the combine pass (or late-combine, depending on the case) to merge a float_extend'ed vec_duplicate into a mult RTL instruction. Before this patch, we have six instructions, e.g.: fcvt.d.s fa0,fa0 vsetvli a5,zero,e64,m1,ta,ma vfmv.v.f v3,fa0 vfwcvt.f.f.v v1,v2 vsetvli zero,zero,e64,m1,ta,ma vfmul.vv v1,v3,v1 After, we get only one: vfwmul.vf v1,v2,fa0 gcc/ChangeLog: * config/riscv/autovec-opt.md (*vfwmul_vf_<mode>): New pattern to combine float_extend + vec_duplicate + vfmul.vv into vfmul.vf. * config/riscv/vector.md (*@pred_dual_widen_<optab><mode>_scalar): Swap operands to match the RTL emitted by expand, i.e. first float_extend then vec_duplicate. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c: Add vfwmul. * gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf_binop.h: Add support for widening variants. * gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_widen_run.h: New test helper. * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmul-run-1-f16.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmul-run-1-f32.c: New test.
11 daysRISC-V: Add patterns for vector-scalar IEEE floating-point maxPaul-Antoine Arras13-10/+32
These patterns enable the combine pass (or late-combine, depending on the case) to merge a vec_duplicate into an unspec_vfmax RTL instruction. Before this patch, we have two instructions, e.g.: vfmv.v.f v2,fa0 vfmax.vv v1,v2,v1 After, we get only one: vfmax.vf v1,v1,fa0 In some cases, it also shaves off one vsetvli. gcc/ChangeLog: * config/riscv/autovec-opt.md (*vfmin_vf_ieee_<mode>): Rename into... (*v<ieee_fmaxmin_op>_vf_<mode>): New pattern to combine vec_duplicate + vf{max,min}.vv (unspec) into vf{max,min}.vf. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f16.c: Add vfmax. * gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f32.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f64.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f16.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f32.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f64.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f16.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f32.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f64.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f16.c: Add vfmax. Also add missing -fno-fast-math. * gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f32.c: Likewise. * gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f64.c: Likewise.
11 dayslibstdc++: Fix up <ext/pointer.h> [PR121827]Jakub Jelinek2-1/+1
During the tests mentioned in https://gcc.gnu.org/pipermail/gcc-patches/2025-August/692482.html (but dunno why I haven't noticed it back in August but only when testing https://gcc.gnu.org/pipermail/gcc-patches/2025-September/694527.html ) I've noticed two ext header problems. One is that #include <ext/pointer.h> got broken with the r13-3037-g18f176d0b25591e28 change and since then is no longer self-contained, as it includes iosfwd only if _GLIBCXX_HOSTED is defined but doesn't actually include bits/c++config.h to make sure it is defined, then includes a bunch of headers which do include bits/c++config.h and finally uses in #if _GLIBCXX_HOSTED guarded code what is declared in iosfwd. The other problem is that ext/cast.h is also not a self-contained header, but that one has /** @file ext/cast.h * This is an internal header file, included by other library headers. * Do not attempt to use it directly. @headername{ext/pointer.h} */ comment, so I think we just shouldn't include it in extc++.h and let ext/pointer.h include it. 2025-09-08 Jakub Jelinek <jakub@redhat.com> PR libstdc++/121827 * include/precompiled/extc++.h: Don't include ext/cast.h which is an internal header. * include/ext/pointer.h: Include bits/c++config.h before #if _GLIBCXX_HOSTED.
11 dayslibstdc++: Update link to "Tunables" in Glibc manualGerald Pfeifer2-2/+2
libstdc++-v3: * doc/xml/manual/using_exceptions.xml: Update link to "Tunables" section in the Glibc manual. * doc/html/manual/using_exceptions.html: Regenerate.
11 daysdoc: Remove references to Binutils 2.7 requirementsGerald Pfeifer1-5/+1
GNU Binutils 2.7 was released in 1996, no realistic need to point it out as a minimal requirement. gcc: * doc/extend.texi (SH Function Attributes): Remove reference to GNU Binutils 2.7 requirement. (H8/300 Variable Attributes): Ditto.
11 dayscompare_tests: Report non-unique test namesChristophe Lyon1-1/+25
Test "names" (the string after 'PASS:' or 'FAIL:' etc... is expected to be unique, otherwise this will confuse comparison scripts. This patch displays the lists of non-unique test names in the 'before' and in the 'now' results. contrib/ChangeLog: * compare_tests: Report non-unique test names.
11 dayslibstdc++: Adjust span/mdspan CTAD for P2781R9.Luc Grosheintz4-15/+53
A usecase for P2781R9 is more ergonomic creation of span and mdspan with mixed static and dynamic extents, e.g.: span(ptr, cw<3>) extents(cw<3>, 5, cw<7>) mdspan(ptr, cw<3>, 5, cw<7>) should be deduced as: span<..., 3> extents<..., 3, dyn, 7> mdspan<..., extents<..., 3, dyn, 7>> The change required is to strip cv-qualifiers and references from `_Tp::value`, because of: template<_CwFixedValue _X, typename> struct constant_wrapper : _CwOperators { static constexpr const auto& value = _X._M_data; libstdc++-v3/ChangeLog: * include/std/span (__integral_constant_like): Allow the member `value` of a constant wrapping type to be a const reference of an integer. * testsuite/23_containers/mdspan/extents/misc.cc: Add test for cw and constant_wrapper. * testsuite/23_containers/mdspan/mdspan.cc: Ditto. * testsuite/23_containers/span/deduction.cc: Ditto. Reviewed-by: Jonathan Wakely <jwakely@redhat.com> Reviewed-by: Tomasz Kamiński <tkaminsk@redhat.com> Signed-off-by: Luc Grosheintz <luc.grosheintz@gmail.com>
11 dayslibstdc++: Implement constant_wrapper, cw from P2781R9.Luc Grosheintz11-0/+1584
This is a partial implementation of P2781R9. It adds std::cw and std::constant_wrapper, but doesn't modify __integral_constant_like for span/mdspan. libstdc++-v3/ChangeLog: * include/bits/version.def (constant_wrapper): Add. * include/bits/version.h: Regenerate. * include/std/type_traits (_CwFixedValue): New class. (_IndexSequence): New struct. (_BuildIndexSequence): New struct. (_ConstExprParam): New concept. (_CwOperators): New struct. (constant_wrapper): New struct. (cw): New global constant. * src/c++23/std.cc.in (constant_wrapper): Add. (cw): Add. * testsuite/20_util/constant_wrapper/adl.cc: New test. * testsuite/20_util/constant_wrapper/ex.cc: New test. * testsuite/20_util/constant_wrapper/generic.cc: New test. * testsuite/20_util/constant_wrapper/instantiate.cc: New test. * testsuite/20_util/constant_wrapper/op_comma_neg.cc: New test. * testsuite/20_util/constant_wrapper/version.cc: New test. Reviewed-by: Jonathan Wakely <jwakely@redhat.com> Co-authored-by: Tomasz Kamiński <tkaminsk@redhat.com> Signed-off-by: Luc Grosheintz <luc.grosheintz@gmail.com> Signed-off-by: Tomasz Kamiński <tkaminsk@redhat.com>
11 daysFortran: Correct variable typespec in PDT specification exprs [PR84008]Paul Thomas2-0/+32
2025-09-08 Paul Thomas <pault@gcc.gnu.org> gcc/fortran PR fortran/84008 * decl.cc (insert_parameter_exprs): Correct the typespec of new variable declarations, where the type is set to BT_PROCEDURE as a precaution for resolution of the whole program unit. gcc/testsuite/ PR fortran/84008 * gfortran.dg/pdt_45.f03: New test.
11 daysstrlen: Handle empty constructor as memset for combining with malloc to ↵Andrew Pinski4-5/+111
calloc [PR87900] This was noticed when turning memset (with constant size) into a store of an empty constructor but can be reproduced without that. In this case we have the following IR: ``` p_3 = __builtin_malloc (4096); *p_3 = {}; ``` Which we can treat the store as a memset. So this patch adds the similar optimization as memset/malloc now for malloc/constructor. This patch is on top of https://gcc.gnu.org/pipermail/gcc-patches/2025-April/681439.html (it calls allow_memset_malloc_to_calloc but that can be removed if that patch is rejected). Changes since v1: * v2: Correctly return false from handle_assign after removing stmt. Bootstrapped and tested on x86_64-linux-gnu. PR tree-optimization/87900 gcc/ChangeLog: * tree-ssa-strlen.cc (strlen_pass::handle_assign): Add RHS argument. For empty constructor RHS, see if can combine with a previous malloc into a calloc. (strlen_pass::check_and_optimize_call): Update call to handle_assign; passing NULL_TREE for RHS. (strlen_pass::check_and_optimize_stmt): Update call to handle_assign. gcc/testsuite/ChangeLog: * gcc.dg/tree-ssa/calloc-10.c: New test. * gcc.dg/tree-ssa/calloc-11.c: New test. * gcc.dg/tree-ssa/calloc-12.c: New test. Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
11 daysstrlen: Don't do the malloc+memset->calloc optimization in some cases [PR83022]Andrew Pinski5-0/+169
This fixes a long standing (since GCC 5) issue where the malloc+memset->calloc optimization would happen even if the memset was not always executed. This is a varient of Nathan's patch: https://inbox.sourceware.org/gcc-patches/f4b5d106-8176-b7bd-709b-d435188783b0@acm.org/ Jeff Law had suggested to look at probabilities of the basic blocks to see if it is profitable or not; I am not totally convinced that is a good idea. Though this is an extended version of Nathan's patch as it uses post domination to see if the memset is always called after the condition of null-ness. PR tree-optimization/83022 gcc/ChangeLog: * tree-ssa-strlen.cc (last_stmt_ptr_check): New function. (allow_memset_malloc_to_calloc): New function. (strlen_pass::handle_builtin_memset): Check to see if it is a good idea to do the malloc+memset->calloc optimization. (printf_strlen_execute): Free post dom info. gcc/testsuite/ChangeLog: * gcc.dg/tree-ssa/calloc-6.c: New test. * gcc.dg/tree-ssa/calloc-7.c: New test. * gcc.dg/tree-ssa/calloc-8.c: New test. * gcc.dg/tree-ssa/calloc-9.c: New test. Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
11 daysgcc: regenerate common.opt.urlsSam James1-0/+3
Needed to add -fdep-fusion. gcc/ChangeLog: * common.opt.urls: Regenerate.
11 daysDaily bump.GCC Administrator5-1/+175
11 daysforwprop: Improve rejection of overlapping for copyprop of aggregates [PR121841]Andrew Pinski2-3/+30
Here we have: tmp = src1[0]; dest1[0] = tmp; where src1 and dest1 are decls. We currently reject this as the bases are different but since the bases are decls we know they won't overlap. This adds the extra check to allow this. Bootstrapped and tested on x86_64-linux-gnu. PR tree-optimization/121841 gcc/ChangeLog: * tree-ssa-forwprop.cc (optimize_agr_copyprop_1): Allow two different decls as bases as non-overlapping bases. gcc/testsuite/ChangeLog: * gcc.dg/tree-ssa/copy-prop-aggregate-struct-1.c: New test. Signed-off-by: Andrew Pinski <andrew.pinski@oss.qualcomm.com>
11 daysgcc: introduce the dep_fusion passJeff Law1-3/+3
>> + >> + // opt_pass methods: >> + opt_pass *clone () override { return new pass_dep_fusion (m_ctxt); } >> + bool gate (function *) override; >> + unsigned int execute (function *) override; > > Wouldn't it be better to add 'final' along with 'override' to opt_pass > vfuncs? > (See commit 725793af78064fa605ea6d9376aaf99ecb71467b, etc.)Yea. It's easily missed. Fixed in the obvious way. Bootstrapped and regression tested on x86_64. Pushed to the trunk. gcc/ * dep-fusion.cc: Mark clone, gate and execute methods as final.
11 daysRISC-V: Add support for the XAndesvdot ISA extension.Kuan-Lin Chen20-3/+2488
This extension defines vector instructions to calculae of the signed/unsigned dot product of four SEW/4-bit data and accumulate the result into a SEWbit element for all elements in a vector register. gcc/ChangeLog: * config/riscv/andes-vector-builtins-bases.cc (nds_vd4dot): New class. (class nds_vd4dotsu): New class. * config/riscv/andes-vector-builtins-bases.h: New def. * config/riscv/andes-vector-builtins-functions.def (nds_vd4dots): Ditto. (nds_vd4dotsu): Ditto. (nds_vd4dotu): Ditto. * config/riscv/andes-vector.md (@pred_nds_vd4dot<su><mode>): New pattern. (@pred_nds_vd4dotsu<mode>): New pattern. * config/riscv/genrvv-type-indexer.cc (main): Modify sew of QUAD_FIX, QUAD_FIX_SIGNED and QUAD_FIX_UNSIGNED. * config/riscv/riscv-vector-builtins.cc (qexti_vvvv_ops): New operand information. (qexti_su_vvvv_ops): New operand information. (qextu_vvvv_ops): New operand information. * config/riscv/riscv-vector-builtins.h (XANDESVDOT_EXT): New def. (required_ext_to_isa_name): Add case XANDESVDOT_EXT. (required_extensions_specified): Ditto. (struct function_group_info): Ditto. * config/riscv/vector-iterators.md (NDS_QUAD_FIX): New iterator. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/xandesvector/non-policy/non-overloaded/nds_vd4dots.c: New test. * gcc.target/riscv/rvv/xandesvector/non-policy/non-overloaded/nds_vd4dotsu.c: New test. * gcc.target/riscv/rvv/xandesvector/non-policy/non-overloaded/nds_vd4dotu.c: New test. * gcc.target/riscv/rvv/xandesvector/non-policy/overloaded/nds_vd4dots.c: New test. * gcc.target/riscv/rvv/xandesvector/non-policy/overloaded/nds_vd4dotsu.c: New test. * gcc.target/riscv/rvv/xandesvector/non-policy/overloaded/nds_vd4dotu.c: New test. * gcc.target/riscv/rvv/xandesvector/policy/non-overloaded/nds_vd4dots.c: New test. * gcc.target/riscv/rvv/xandesvector/policy/non-overloaded/nds_vd4dotsu.c: New test. * gcc.target/riscv/rvv/xandesvector/policy/non-overloaded/nds_vd4dotu.c: New test. * gcc.target/riscv/rvv/xandesvector/policy/overloaded/nds_vd4dots.c: New test. * gcc.target/riscv/rvv/xandesvector/policy/overloaded/nds_vd4dotsu.c: New test. * gcc.target/riscv/rvv/xandesvector/policy/overloaded/nds_vd4dotu.c: New test.
11 days[RISC-V] Fix ordering of pipeline modelsJeff Law1-1/+1
I missed that the new ascalon pipeline description was put into the wrong place during review. The net is tests which wanted to use generic-ooo explicitly for stability in the test output ended up getting a different pipeline model and different codegen than the test expected. This tripped a small number of vsetvl failures in the testsuite. This has spun on riscv64-elf and riscv32-elf in my tester and fixes the regression. I'm going to go ahead and push it as I'm likely offline this afternoon/evening and don't want anyone else to waste their time chasing the regression down. gcc/ * config/riscv/riscv-opts.h (riscv_microarchitecture_type): Fix ordering.
11 dayslibphobos: enable for more hppa tuplesSam James1-1/+1
Gentoo uses hppa1.1*-*-linux* and hppa2.0*-*-linux* instead of Debian's hppa-*-linux*. libphobos/ChangeLog: * configure.tgt: Add hppa[12]*-*-linux* as a supported target.
11 daysRISC-V: Add support for the XAndesvpackfph ISA extension.Kuan-Lin Chen19-1/+1381
This extension defines vector instructions to extract a pair of FP16 data from a floating-point register. Multiply the top FP16 data with the FP16 elements and add the result with the bottom FP16 data. gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Turn on VECTOR_ELEN_FP_16 for XAndesvpackfph. * config/riscv/andes-vector-builtins-bases.cc (nds_vfpmad): New class. * config/riscv/andes-vector-builtins-bases.h: New def. * config/riscv/andes-vector-builtins-functions.def (nds_vfpmadt): Ditto. (nds_vfpmadb): Ditto. (nds_vfpmadt_frm): Ditto. (nds_vfpmadb_frm): Ditto. * config/riscv/andes-vector.md (@pred_nds_vfpmad<nds_tb><mode>): New pattern. * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_F16_OPS): New def. * config/riscv/riscv-vector-builtins.cc (f16_ops): Ditto * config/riscv/riscv-vector-builtins.def (float32_type_node): Ditto. * config/riscv/riscv-vector-builtins.h (XANDESVPACKFPH_EXT): Ditto. (required_ext_to_isa_name): Add case XANDESVPACKFPH_EXT. (required_extensions_specified): Ditto. * config/riscv/vector-iterators.md (VHF): New iterator. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/xandesvector/non-policy/non-overloaded/nds_vfpmadb.c: New test. * gcc.target/riscv/rvv/xandesvector/non-policy/non-overloaded/nds_vfpmadt.c: New test. * gcc.target/riscv/rvv/xandesvector/non-policy/overloaded/nds_vfpmadb.c: New test. * gcc.target/riscv/rvv/xandesvector/non-policy/overloaded/nds_vfpmadt.c: New test. * gcc.target/riscv/rvv/xandesvector/policy/non-overloaded/nds_vfpmadb.c: New test. * gcc.target/riscv/rvv/xandesvector/policy/non-overloaded/nds_vfpmadt.c: New test. * gcc.target/riscv/rvv/xandesvector/policy/overloaded/nds_vfpmadb.c: New test. * gcc.target/riscv/rvv/xandesvector/policy/overloaded/nds_vfpmadt.c: New test.
12 daysc++: Update TLS model after processing a TLS variableH.J. Lu5-4/+61
Set a tentative TLS model in grokvardecl and update TLS mode with the default TLS access model after a TLS variable has been fully processed if the default TLS access model is stronger. gcc/cp/ PR c++/107393 * decl.cc (grokvardecl): Set a tentative TLS model which will be updated by cplus_decl_attributes later. * decl2.cc (cplus_decl_attributes): Update TLS model with the default TLS access model if the default TLS access model is stronger. * pt.cc (tsubst_decl): Set TLS model only after processing a variable. gcc/testsuite/ PR c++/107393 * g++.dg/tls/pr107393-1.C: New test. * g++.dg/tls/pr107393-2.C: Likewise. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
12 daysAVR: ad target/121794 - Invoke zero_reg less.Georg-Johann Lay1-5/+5
gcc/ PR target/121794 * config/avr/avr.md (cmpqi3): Use cpi R,0 if possible.
12 dayslibphobos: enable for powerpc64le-linux-gnuMatthias Klose1-0/+9
libphobos/ChangeLog: * configure.tgt: Add powerpc64le-linux-gnu as a supported target when configured with --with-long-double-format=ieee.
12 daysRISC-V: Add test for vec_duplicate + vnmsub.vv unsigned combine with GR2VR ↵Pan Li16-0/+76
cost 0, 1 and 15 Add asm dump check and run test for vec_duplicate + vnmsub.vvm combine to vnmsub.vx, with the GR2VR cost is 0, 2 and 15. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c: Add asm check for vnmsub.vx. * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-u16.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-u32.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-u64.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-u8.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
12 daysRISC-V: Add test for vec_duplicate + vnmsub.vv signed combine with GR2VR ↵Pan Li18-0/+446
cost 0, 1 and 15 Add asm dump check and run test for vec_duplicate + vnmsub.vv combine to vnmsub.vx, with the GR2VR cost is 0, 2 and 15. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c: Add asm check for vnmsub.vx. * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary.h: Add test helper macros. * gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary_data.h: Add test data for run test. * gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-i16.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-i32.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-i64.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-i8.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
12 daysRISC-V: Combine vec_duplicate + vnmsub.vv to vnmsub.vx on GR2VR costPan Li2-27/+31
This patch would like to combine the vec_duplicate + vnmsub.vv to the vnmsub.vx. From example as below code. The related pattern will depend on the cost of vec_duplicate from GR2VR. Then the late-combine will take action if the cost of GR2VR is zero, and reject the combination if the GR2VR cost is greater than zero. Assume we have example code like below, GR2VR cost is 0. Before this patch: 11 │ beq a3,zero,.L8 12 │ vsetvli a5,zero,e32,m1,ta,ma 13 │ vmv.v.x v2,a2 ... 16 │ .L3: 17 │ vsetvli a5,a3,e32,m1,ta,ma ... 22 │ vnmsub.vv v1,v2,v3 ... 25 │ bne a3,zero,.L3 After this patch: 11 │ beq a3,zero,.L8 ... 14 │ .L3: 15 │ vsetvli a5,a3,e32,m1,ta,ma ... 20 │ vnmsub.vx v1,a2,v3 ... 23 │ bne a3,zero,.L3 gcc/ChangeLog: * config/riscv/autovec-opt.md (*vnmsac_vx_<mode>): Rename from. (*mul_minus_vx_<mode>): Rename to and add nmsub support. * config/riscv/vector.md (@pred_vnmsac_vx_<mode>): Rename from. (@pred_mul_minus_vx_<mode>): Rename to and add nmsub support. (*pred_nmsac_<mode>_scalar_undef): Rename from. (*pred_mul_minus_vx<mode>_undef): Rename to and add nmsub support. Signed-off-by: Pan Li <pan2.li@intel.com>
12 daysDaily bump.GCC Administrator6-1/+229
12 daysdoc: drop verify-canonical-types=1 refSam James1-2/+1
--param verify-canonical-types was removed back in r0-81986-g7313518b90b280. The same verification is controlled via our generic checking framework these days. gcc/ChangeLog: * doc/generic.texi (TYPE_CANONICAL): Don't mention long-removed --param verify-canonical-types.
12 daysdep_fusion: Fix if target does not have macro fusion [PR121835]Andrew Pinski1-0/+4
This new pass will ICE if the target does not define the macro_fusion_pair_p pass. The pass will not be useful in that case so it is best to return early. Pushed as obvious after a bootstrap on x86_64-linux-gnu. PR rtl-optimization/121835 gcc/ChangeLog: * dep-fusion.cc (pass_dep_fusion::execute): Return early if macro_fusion_pair_p is null. Signed-off-by: Andrew Pinski <andrew.pinski@oss.qualcomm.com>
12 daysgcc: introduce the dep_fusion passArtemiy Volkov7-3/+169
Presently, the scheduler code only considers consecutive instructions for macro-op fusion (see sched-deps.cc::sched_macro_fuse_insns () for details). This patch introduces the new dep_fusion pass, which is intended to uncover more fusion opportunities by reordering eligible instructions to form fusible pairs (based solely on the value of the TARGET_SCHED_MACRO_FUSION_PAIR_P hook). This is achieved by using the RTL-SSA framework, and only the single-use instructions are considered for the first instruction of a pair. Aside from reordering instructions, this pass also sets the SCHED_GROUP flag for the second instruction so that following passes can implement special handling of the fused pairs. For instance, RA and regrename should make use of this information to preserve single-output property for some of such pairs. Accordingly, in passes.def, this patch adds two invocations of the new pass: just before IRA and just before regrename. The new pass is enabled at -O2+ and -Os. gcc/ChangeLog: * Makefile.in (OBJS): Add dep-fusion.o. * common.opt (fdep-fusion): Add option. * dep-fusion.cc: New pass. * doc/invoke.texi: Document it. * opts.cc (default_options_table): Enable it at -O2+ and -Os. * passes.def: Insert two instances of dep_fusion. * tree-pass.h (make_pass_dep_fusion): Declare new function.
12 daysdoc: fix -momit-leaf-frame-pointer typoSam James1-1/+1
For x86, the option is -momit-leaf-frame-pointer, not -fomit-leaf-frame-pointer. gcc/ChangeLog: * doc/invoke.texi (x86 Options): Fix '-momit-leaf-frame-pointer' typo.
12 daysforwprop: Factor out the memcpy followed by memset optimizationAndrew Pinski1-198/+212
As simplify_builtin_call adds more and more optimization, it is getting bigger and bigger and easier to misunderstand, so this factors out the memcpy followed by memset optimization (which was the original optimization added). Bootstrapped and tested on x86_64-linux-gnu. gcc/ChangeLog: * tree-ssa-forwprop.cc (simplify_builtin_call): Factor out the memcpy followed by a memset optimization to ... (simplify_builtin_memcpy_memset): Here. New function. Signed-off-by: Andrew Pinski <andrew.pinski@oss.qualcomm.com>
12 daysforwprop: Factor out memchr optimization to its own functionAndrew Pinski1-60/+70
As more optimizations are added to forwprop's simplify_builtin_call, this function is becoming harder and harder to understand. To help simplify things, this factors out the memchr optimization to its own function like what was done when memcmp optimization was added. Bootstrapped and tested on x86_64-linux-gnu. gcc/ChangeLog: * tree-ssa-forwprop.cc (simplify_builtin_call): Factor out the memchr optimization to ... (simplify_builtin_memchr): Here. New function. Signed-off-by: Andrew Pinski <andrew.pinski@oss.qualcomm.com>
12 daysipa: Fix build on MacOSSimon Martin1-0/+1
The build is broken on MacOS since r16-3581-g1da3c4d90e678a because ipa-inline-transform.cc uses std::max but does not include <algorithm>. This patch fixes it by defining INCLUDE_ALGORITHM in that file. gcc/ChangeLog: * ipa-inline-transform.cc: Define INCLUDE_ALGORITHM.
12 daysinstall: Properly capitalize GNU BinutilsGerald Pfeifer1-12/+12
gcc: PR target/69374 * doc/install.texi (Prerequisites): Properly capitalize GNU Binutils. (Configuration): Ditto. (Building): Ditto. (Specific): Ditto.
12 daysdoc: consistently say 'whole-program' where appropriateSam James1-4/+4
Unchanged instances are deliberate. gcc/ChangeLog: * doc/invoke.texi: Say 'whole-program' consistently where appropriate.
12 daysdoc: consistently spell 'GNU Binutils'Sam James1-2/+2
gcc/ChangeLog: * doc/invoke.texi: Capitalize 'GNU Binutils' consistently.
12 daysdoc: update incremental link vs binutils informationSam James1-7/+6
GNU Binutils now supports linking LTO and non-LTO objects into a single mixed object file as of 2.44. Update the text to reflect this and fix some minor grammar issues while at it. gcc/ChangeLog: PR ipa/116410 * doc/invoke.texi (Link Options): Update -flinker-output= text to reflect GNU Binutils changes. Fix grammar.
12 daysRISC-V: Add support for the XAndesvsintload ISA extension.Kuan-Lin Chen13-1/+468
This extension defines vector load instructions to move sign-extended or zero-extended INT4 data into 8-bit vector register elements. gcc/ChangeLog: * config/riscv/andes-vector-builtins-bases.cc (nds_nibbleload): New class. * config/riscv/andes-vector-builtins-bases.h (nds_vln8): New def. (nds_vlnu8): Ditto. * config/riscv/andes-vector-builtins-functions.def (nds_vln8): Ditto. (nds_vlnu8): Ditto. * config/riscv/andes-vector.md (@pred_intload_mov<su><mode>): New pattern. * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_Q_OPS): New def. (DEF_RVV_QU_OPS): Ditto. * config/riscv/riscv-vector-builtins.cc (q_v_void_const_ptr_ops): New operand information. (qu_v_void_const_ptr_ops): Ditto. * config/riscv/riscv-vector-builtins.def (void_const_ptr): New def. * config/riscv/riscv-vector-builtins.h (enum required_ext): Ditto. (required_ext_to_isa_name): Add case XANDESVSINTLOAD_EXT. (required_extensions_specified): Ditto. * config/riscv/vector-iterators.md (NDS_QVI): New iterator. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/xandesvector/non-policy/non-overloaded/nds_vln8.c: New test. * gcc.target/riscv/rvv/xandesvector/non-policy/overloaded/nds_vln8.c: New test. * gcc.target/riscv/rvv/xandesvector/policy/non-overloaded/nds_vln8.c: New test. * gcc.target/riscv/rvv/xandesvector/policy/overloaded/nds_vln8.c: New test.
12 daysRISC-V: Add support for the XAndesvbfhcvt ISA extension.Kuan-Lin Chen23-3/+648
This patch add support for XAndesvbfhcvt ISA extension. This extension defines instructions to perform vector floating-point conversion between the BFLOAT16 floating-point data and the IEEE-754 32-bit single-precision floating-point (SP) data in a vector register. gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Turn on VECTOR_ELEN_BF_16 for XAndesvbfhcvt. * config.gcc: Add extra_objs andes-vector-builtins-bases.o and extra_headers andes_vector.h. * config/riscv/riscv-vector-builtins-shapes.cc (BASE_NAME_MAX_LEN): Increase size to 20. * config/riscv/riscv-vector-builtins.cc (f32_to_bf16_nf_w_ops): New operand information. (f32_to_bf16_nf_w_ops): New operand information. (DEF_RVV_FUNCTION): New def. * config/riscv/riscv-vector-builtins.def (bf16): Ditto. * config/riscv/riscv-vector-builtins.h (enum required_ext): Ditto. (required_ext_to_isa_name): Add case XANDESVBFHCVT_EXT. (required_extensions_specified): Ditto. * config/riscv/t-riscv: Add andes-vector-builtins-functions.def, andes-vector-builtins-bases.h and andes-vector-builtins-bases.o. * config/riscv/vector-iterators.md (NDS_VWEXTBF): New iterator. (NDS_V_DOUBLE_TRUNC_BF): New attr. * config/riscv/andes-vector-builtins-bases.cc: New file. * config/riscv/andes-vector-builtins-bases.h: New file. * config/riscv/andes-vector-builtins-functions.def: New file. * config/riscv/andes_vector.h: New file. * config/riscv/andes-vector.md: New file. * config/riscv/vector.md: Include andes_vector.md. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/rvv.exp: Add regression for xandesvector. * gcc.target/riscv/rvv/xandesvector/non-policy/non-overloaded/nds_vfncvtbf16s.c: New test. * gcc.target/riscv/rvv/xandesvector/non-policy/non-overloaded/nds_vfwcvtsbf16.c: New test. * gcc.target/riscv/rvv/xandesvector/non-policy/overloaded/nds_vfncvtbf16s.c: New test. * gcc.target/riscv/rvv/xandesvector/non-policy/overloaded/nds_vfwcvtsbf16.c: New test. * gcc.target/riscv/rvv/xandesvector/policy/non-overloaded/nds_vfncvtbf16s.c: New test. * gcc.target/riscv/rvv/xandesvector/policy/non-overloaded/nds_vfwcvtsbf16.c: New test. * gcc.target/riscv/rvv/xandesvector/policy/overloaded/nds_vfncvtbf16s.c: New test. * gcc.target/riscv/rvv/xandesvector/policy/overloaded/nds_vfwcvtsbf16.c: New test.
12 daysRISC-V: Add tt-ascalon-d8 pipeline descriptionAnton Blanchard4-2/+357
Add pipeline description for the Tenstorrent Ascalon 8 wide CPU. gcc/ChangeLog * config/riscv/riscv-cores.def (RISCV_TUNE): Update. * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type): Add tt_ascalon_d8. * config/riscv/riscv.md: Update tune attribute and include tt-ascalon-d8.md. * config/riscv/tt-ascalon-d8.md: New file.
12 daysFortran: Implement correct form of PDT constructors [PR84119]Paul Thomas2-23/+45
2025-09-06 Paul Thomas <pault@gcc.gnu.org> gcc/fortran PR fortran/84119 * resolve.cc (reset_array_ref_to_scalar): New function using chunk broken out from gfc_resolve_ref. (gfc_resolve_ref): Call the new function, the first time for PDT type parameters and the second time for LEN inquiry refs. gcc/testsuite/ PR fortran/84119 * gfortran.dg/pdt_20.f03: Modify to deal with scalar type parm.
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