aboutsummaryrefslogtreecommitdiff
path: root/gcc/config/avr/avr-fixed.md
diff options
context:
space:
mode:
Diffstat (limited to 'gcc/config/avr/avr-fixed.md')
-rw-r--r--gcc/config/avr/avr-fixed.md129
1 files changed, 40 insertions, 89 deletions
diff --git a/gcc/config/avr/avr-fixed.md b/gcc/config/avr/avr-fixed.md
index ce46beb..22061fc 100644
--- a/gcc/config/avr/avr-fixed.md
+++ b/gcc/config/avr/avr-fixed.md
@@ -62,10 +62,8 @@
"<FIXED_B:MODE>mode != <FIXED_A:MODE>mode"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (fract_convert:FIXED_A
- (match_dup 1)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*fract<FIXED_B:mode><FIXED_A:mode>2"
[(set (match_operand:FIXED_A 0 "register_operand" "=r")
@@ -86,10 +84,8 @@
"<FIXED_B:MODE>mode != <FIXED_A:MODE>mode"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (unsigned_fract_convert:FIXED_A
- (match_dup 1)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*fractuns<FIXED_B:mode><FIXED_A:mode>2"
[(set (match_operand:FIXED_A 0 "register_operand" "=r")
@@ -124,10 +120,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (ss_addsub:ALL124S (match_dup 1)
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*<code_stdname><mode>3"
[(set (match_operand:ALL124S 0 "register_operand" "=??d,d")
@@ -149,10 +143,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (us_addsub:ALL124U (match_dup 1)
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*<code_stdname><mode>3"
[(set (match_operand:ALL124U 0 "register_operand" "=??r,d")
@@ -189,9 +181,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (ss_neg:QQ (match_dup 1)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*ssnegqq2"
[(set (match_operand:QQ 0 "register_operand" "=r")
@@ -207,9 +198,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (ss_abs:QQ (match_dup 1)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*ssabsqq2"
[(set (match_operand:QQ 0 "register_operand" "=r")
@@ -241,9 +231,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:ALL2S 24)
- (ss_abs_neg:ALL2S (reg:ALL2S 24)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*<code_stdname><mode>2"
[(set (reg:ALL2S 24)
@@ -261,9 +250,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:ALL4S 22)
- (ss_abs_neg:ALL4S (reg:ALL4S 22)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*<code_stdname><mode>2"
[(set (reg:ALL4S 22)
@@ -296,10 +284,8 @@
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (mult:QQ (match_dup 1)
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*mulqq3_enh"
[(set (match_operand:QQ 0 "register_operand" "=r")
@@ -317,10 +303,8 @@
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (mult:UQQ (match_dup 1)
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*muluqq3_enh"
[(set (match_operand:UQQ 0 "register_operand" "=r")
@@ -377,12 +361,8 @@
"!AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (reg:QQ 23)
- (mult:QQ (reg:QQ 24)
- (reg:QQ 25)))
- (clobber (reg:QI 22))
- (clobber (reg:HI 24))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*mulqq3.call"
[(set (reg:QQ 23)
@@ -425,11 +405,8 @@
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (reg:ALL2QA 24)
- (mult:ALL2QA (reg:ALL2QA 18)
- (reg:ALL2QA 26)))
- (clobber (reg:HI 22))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*mul<mode>3.call"
[(set (reg:ALL2QA 24)
@@ -468,10 +445,8 @@
"AVR_HAVE_MUL"
"#"
"&& reload_completed"
- [(parallel [(set (reg:ALL4A 24)
- (mult:ALL4A (reg:ALL4A 16)
- (reg:ALL4A 20)))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*mul<mode>3.call"
[(set (reg:ALL4A 24)
@@ -514,11 +489,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:ALL1Q 24)
- (usdiv:ALL1Q (reg:ALL1Q 25)
- (reg:ALL1Q 22)))
- (clobber (reg:QI 25))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*<code><mode>3.call"
[(set (reg:ALL1Q 24)
@@ -560,12 +532,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:ALL2QA 24)
- (usdiv:ALL2QA (reg:ALL2QA 26)
- (reg:ALL2QA 22)))
- (clobber (reg:HI 26))
- (clobber (reg:QI 21))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*<code><mode>3.call"
[(set (reg:ALL2QA 24)
@@ -608,12 +576,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:ALL4A 22)
- (usdiv:ALL4A (reg:ALL4A 24)
- (reg:ALL4A 18)))
- (clobber (reg:HI 26))
- (clobber (reg:HI 30))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*<code><mode>3.call"
[(set (reg:ALL4A 22)
@@ -684,12 +648,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0)
- (unspec:ALL124QA [(match_dup 1)
- (match_dup 2)
- (const_int 0)]
- UNSPEC_ROUND))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*round<mode>3_const"
[(set (match_operand:ALL124QA 0 "register_operand" "=d")
@@ -714,11 +674,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:ALL1Q 24)
- (unspec:ALL1Q [(reg:ALL1Q 22)
- (reg:QI 24)] UNSPEC_ROUND))
- (clobber (reg:ALL1Q 22))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*round<mode>3.libgcc"
[(set (reg:ALL1Q 24)
@@ -740,11 +697,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:ALL2QA 24)
- (unspec:ALL2QA [(reg:ALL2QA 22)
- (reg:QI 24)] UNSPEC_ROUND))
- (clobber (reg:ALL2QA 22))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*round<mode>3.libgcc"
[(set (reg:ALL2QA 24)
@@ -766,11 +720,8 @@
""
"#"
"&& reload_completed"
- [(parallel [(set (reg:ALL4QA 22)
- (unspec:ALL4QA [(reg:ALL4QA 18)
- (reg:QI 24)] UNSPEC_ROUND))
- (clobber (reg:ALL4QA 18))
- (clobber (reg:CC REG_CC))])])
+ [(scratch)]
+ { DONE_ADD_CCC })
(define_insn "*round<mode>3.libgcc"
[(set (reg:ALL4QA 22)
generated by cgit v1.1 at 2025-09-27 09:53:01 +0000