diff options
33 files changed, 506 insertions, 29 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index e09e56a..a75b0c8 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,50 @@ +2025-07-18 Pan Li <pan2.li@intel.com> + + * config/riscv/autovec.md (avg<mode>3_ceil): Add new pattern + of avg3_ceil for RVV DImode + +2025-07-18 Martin Jambor <mjambor@suse.cz> + + PR tree-optimization/117423 + * tree-sra.cc (analyze_access_subtree): Fix computation of grp_covered + flag. + +2025-07-18 Richard Biener <rguenther@suse.de> + + PR tree-optimization/121126 + * tree-vect-stmts.cc (vect_analyze_stmt): Analyze the + live lane extract for LC PHIs that are vect_internal_def. + +2025-07-18 Richard Biener <rguenther@suse.de> + + * tree-vect-loop.cc (vectorizable_live_operation_1): + Remove stmt_info and ncopies parameters. Remove !slp_node + paths. + (vectorizable_live_operation): Remove !slp_node paths. + +2025-07-18 Richard Biener <rguenther@suse.de> + + PR tree-optimization/120924 + * params.opt (uninit-max-chain-len): Up from 8 to 12. + +2025-07-18 Richard Biener <rguenther@suse.de> + + PR tree-optimization/121048 + * tree-vect-loop.cc (vect_determine_vectype_for_stmt_1): + Remove rejecting vector(1) vector types. + (vect_set_stmts_vectype): Likewise. + * tree-vect-slp.cc (vect_make_slp_decision): Only + count instances with non-vector(1) root towards whether + we have any interesting instances to vectorize. + +2025-07-18 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/121131 + * gimple-fold.cc (fold_nonarray_ctor_reference): Use + TREE_INT_CST_LOW (TYPE_SIZE ()) instead of + GET_MODE_BITSIZE (SCALAR_INT_TYPE_MODE ()) for BLKmode BITINT_TYPEs. + Don't compute encoding_size at all for little endian targets. + 2025-07-17 Andrew Pinski <quic_apinski@quicinc.com> PR middle-end/121095 diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 9866b70..c64e486 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20250718 +20250719 diff --git a/gcc/ada/ChangeLog b/gcc/ada/ChangeLog index b66c7ba..7da159e 100644 --- a/gcc/ada/ChangeLog +++ b/gcc/ada/ChangeLog @@ -1,3 +1,58 @@ +2025-07-18 Steve Baird <baird@adacore.com> + + * sem_ch12.adb (Validate_Derived_Type_Instance): Cope with the case + where the ancestor type for a formal derived type is declared in + an earlier formal package but Get_Instance_Of does not return the + corresponding type from the corresponding actual package. + +2025-07-18 Bob Duff <duff@adacore.com> + + * tbuild.adb (Unchecked_Convert_To): Back out + change. + +2025-07-18 Marc Poulhiès <poulhies@adacore.com> + Eric Botcazou <botcazou@adacore.com> + + * exp_ch6.adb (Convert): Do not call Expand_Inlined_Call for + unsupported cases. + * inline.adb (Expand_Inlined_Call): Add assert to catch unsupported + case. + +2025-07-18 Gary Dismukes <dismukes@adacore.com> + + * einfo.ads: Document new field Overridden_Inherited_Operation and + list it as a field for the entity kinds that it applies to. + * gen_il-fields.ads (type Opt_Field_Enum): Add new literal + Overridden_Inherited_Operation to the type. + * gen_il-gen-gen_entities.adb: Add Overridden_Inherited_Operation as + a field of entities of kinds E_Enumeration_Literal and Subprogram_Kind. + * sem_ch4.adb (Is_Callable_Private_Overriding): Change name (was + Is_Private_Overriding). Replace Is_Hidden test on Overridden_Operation + with test of Is_Hidden on the new field Overridden_Inherited_Operation. + * sem_ch6.adb (New_Overloaded_Entity): Set the new field + Overridden_Inherited_Operation on an operation derived from + an interface to refer to the inherited operation of a private + extension that's overridden by the derived operation. Also set + that field in the more common cases of an explicit subprogram + that overrides, to refer to the inherited subprogram that is + overridden. (Contrary to its name, the Overridden_Operation + field of the overriding subprogram, which is also set in these + places, refers to the *parent* subprogram from which the inherited + subprogram is derived.) Also, remove a redundant Present (Alias (S)) + test in an if_statement and the dead "else" part of that statement. + +2025-07-18 Piotr Trojanek <trojanek@adacore.com> + + * sem_util.adb (Build_Elaboration_Entity): Set ghost mode to none + before creating the elaboration entity; restore the ghost mode + afterwards. + +2025-07-18 Javier Miranda <miranda@adacore.com> + + * exp_aggr.adb (Gen_Assign): Code cleanup. + (Initialize_Component): Do not adjust the tag when the type of + the aggregate components is a mutably tagged type. + 2025-07-14 Eric Botcazou <ebotcazou@adacore.com> PR ada/121056 diff --git a/gcc/config/avr/avr-passes.cc b/gcc/config/avr/avr-passes.cc index 284f49d..6a88a27 100644 --- a/gcc/config/avr/avr-passes.cc +++ b/gcc/config/avr/avr-passes.cc @@ -4120,9 +4120,8 @@ avr_optimize_casesi (rtx_insn *insns[5], rtx *xop) JUMP_LABEL (cbranch) = xop[4]; ++LABEL_NUSES (xop[4]); - rtx_insn *seq1 = get_insns (); rtx_insn *last1 = get_last_insn (); - end_sequence (); + rtx_insn *seq1 = end_sequence (); emit_insn_after (seq1, insns[2]); @@ -4141,9 +4140,8 @@ avr_optimize_casesi (rtx_insn *insns[5], rtx *xop) emit_insn (pat_4); - rtx_insn *seq2 = get_insns (); rtx_insn *last2 = get_last_insn (); - end_sequence (); + rtx_insn *seq2 = end_sequence (); emit_insn_after (seq2, insns[3]); diff --git a/gcc/config/pru/pru-pragma.cc b/gcc/config/pru/pru-pragma.cc index c3f3d33..9338780 100644 --- a/gcc/config/pru/pru-pragma.cc +++ b/gcc/config/pru/pru-pragma.cc @@ -46,21 +46,24 @@ pru_pragma_ctable_entry (cpp_reader *) enum cpp_ttype type; type = pragma_lex (&ctable_index); - if (type == CPP_NUMBER && tree_fits_uhwi_p (ctable_index)) + if (type == CPP_NUMBER && tree_fits_shwi_p (ctable_index)) { type = pragma_lex (&base_addr); - if (type == CPP_NUMBER && tree_fits_uhwi_p (base_addr)) + if (type == CPP_NUMBER && tree_fits_shwi_p (base_addr)) { - unsigned HOST_WIDE_INT i = tree_to_uhwi (ctable_index); - unsigned HOST_WIDE_INT base = tree_to_uhwi (base_addr); + HOST_WIDE_INT i = tree_to_shwi (ctable_index); + HOST_WIDE_INT base = sext_hwi (tree_to_shwi (base_addr), + POINTER_SIZE); type = pragma_lex (&base_addr); if (type != CPP_EOF) error ("junk at end of %<#pragma CTABLE_ENTRY%>"); - else if (i >= ARRAY_SIZE (pru_ctable)) + else if (!IN_RANGE (i, 0, ARRAY_SIZE (pru_ctable) - 1)) error ("%<CTABLE_ENTRY%> index %wd is not valid", i); else if (pru_ctable[i].valid && pru_ctable[i].base != base) error ("redefinition of %<CTABLE_ENTRY %wd%>", i); + else if (!IN_RANGE (base, INT32_MIN, INT32_MAX)) + error ("%<CTABLE_ENTRY%> base address does not fit in 32-bits"); else { if (base & 0xff) diff --git a/gcc/config/pru/pru-protos.h b/gcc/config/pru/pru-protos.h index c73fad8..4750f0e 100644 --- a/gcc/config/pru/pru-protos.h +++ b/gcc/config/pru/pru-protos.h @@ -23,7 +23,7 @@ struct pru_ctable_entry { bool valid; - unsigned HOST_WIDE_INT base; + HOST_WIDE_INT base; }; extern struct pru_ctable_entry pru_ctable[32]; @@ -66,9 +66,9 @@ pru_regno_ok_for_index_p (int regno, bool strict_p) return pru_regno_ok_for_base_p (regno, strict_p); } -extern int pru_get_ctable_exact_base_index (unsigned HOST_WIDE_INT caddr); -extern int pru_get_ctable_base_index (unsigned HOST_WIDE_INT caddr); -extern int pru_get_ctable_base_offset (unsigned HOST_WIDE_INT caddr); +extern int pru_get_ctable_exact_base_index (HOST_WIDE_INT caddr); +extern int pru_get_ctable_base_index (HOST_WIDE_INT caddr); +extern int pru_get_ctable_base_offset (HOST_WIDE_INT caddr); extern int pru_symref2ioregno (rtx op); diff --git a/gcc/config/pru/pru.cc b/gcc/config/pru/pru.cc index 47e5f24..322e319 100644 --- a/gcc/config/pru/pru.cc +++ b/gcc/config/pru/pru.cc @@ -1428,7 +1428,7 @@ pru_valid_const_ubyte_offset (machine_mode mode, HOST_WIDE_INT offset) /* Recognize a CTABLE base address. Return CTABLE entry index, or -1 if base was not found in the pragma-filled pru_ctable. */ int -pru_get_ctable_exact_base_index (unsigned HOST_WIDE_INT caddr) +pru_get_ctable_exact_base_index (HOST_WIDE_INT caddr) { unsigned int i; @@ -1444,7 +1444,7 @@ pru_get_ctable_exact_base_index (unsigned HOST_WIDE_INT caddr) /* Check if the given address can be addressed via CTABLE_BASE + UBYTE_OFFS, and return the base CTABLE index if possible. */ int -pru_get_ctable_base_index (unsigned HOST_WIDE_INT caddr) +pru_get_ctable_base_index (HOST_WIDE_INT caddr) { unsigned int i; @@ -1461,7 +1461,7 @@ pru_get_ctable_base_index (unsigned HOST_WIDE_INT caddr) /* Return the offset from some CTABLE base for this address. */ int -pru_get_ctable_base_offset (unsigned HOST_WIDE_INT caddr) +pru_get_ctable_base_offset (HOST_WIDE_INT caddr) { int i; @@ -2004,7 +2004,7 @@ pru_print_operand_address (FILE *file, machine_mode mode, rtx op) case CONST_INT: { - unsigned HOST_WIDE_INT caddr = INTVAL (op); + HOST_WIDE_INT caddr = INTVAL (op); int base = pru_get_ctable_base_index (caddr); int offs = pru_get_ctable_base_offset (caddr); if (base < 0) diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md index f372f0e..12217c0 100644 --- a/gcc/config/riscv/autovec-opt.md +++ b/gcc/config/riscv/autovec-opt.md @@ -1844,3 +1844,54 @@ } [(set_attr "type" "vfwmuladd")] ) + +;; vfwnmacc.vf +(define_insn_and_split "*vfwnmacc_vf_<mode>" + [(set (match_operand:VWEXTF 0 "register_operand") + (minus:VWEXTF + (mult:VWEXTF + (neg:VWEXTF + (vec_duplicate:VWEXTF + (float_extend:<VEL> + (match_operand:<VSUBEL> 2 "register_operand")))) + (float_extend:VWEXTF + (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand"))) + (match_operand:VWEXTF 1 "register_operand")))] + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] + { + rtx ops[] = {operands[0], operands[1], operands[2], operands[3]}; + riscv_vector::emit_vlmax_insn( + code_for_pred_widen_mul_neg_scalar(MINUS, <MODE>mode), + riscv_vector::WIDEN_TERNARY_OP_FRM_DYN, ops); + DONE; + } + [(set_attr "type" "vfwmuladd")] +) + +;; vfwnmsac.vf +(define_insn_and_split "*vfwnmsac_vf_<mode>" + [(set (match_operand:VWEXTF 0 "register_operand") + (minus:VWEXTF + (match_operand:VWEXTF 1 "register_operand") + (mult:VWEXTF + (float_extend:VWEXTF + (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand")) + (vec_duplicate:VWEXTF + (float_extend:<VEL> + (match_operand:<VSUBEL> 2 "register_operand"))))))] + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] + { + rtx ops[] = {operands[0], operands[1], operands[2], operands[3]}; + riscv_vector::emit_vlmax_insn( + code_for_pred_widen_mul_neg_scalar (PLUS, <MODE>mode), + riscv_vector::WIDEN_TERNARY_OP_FRM_DYN, ops); + DONE; + } + [(set_attr "type" "vfwmuladd")] +) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 1275b03..cb9fe31 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -3969,11 +3969,14 @@ get_vector_binary_rtx_cost (rtx x, int scalar2vr_cost) rtx op_0 = XEXP (x, 0); rtx op_1 = XEXP (x, 1); + rtx neg; if (GET_CODE (op_0) == VEC_DUPLICATE || GET_CODE (op_1) == VEC_DUPLICATE) return (scalar2vr_cost + 1) * COSTS_N_INSNS (1); - else if (GET_CODE (op_0) == NEG && GET_CODE (op_1) == VEC_DUPLICATE) + else if (GET_CODE (neg = op_0) == NEG + && (GET_CODE (op_1) == VEC_DUPLICATE + || GET_CODE (XEXP (neg, 0)) == VEC_DUPLICATE)) return (scalar2vr_cost + 1) * COSTS_N_INSNS (1); else return COSTS_N_INSNS (1); @@ -10359,10 +10362,10 @@ riscv_macro_fusion_pair_p (rtx_insn *prev, rtx_insn *curr) bool simple_sets_p = prev_set && curr_set && !any_condjump_p (curr); bool sched1 = can_create_pseudo_p (); - unsigned int prev_dest_regno = (REG_P (SET_DEST (prev_set)) + unsigned int prev_dest_regno = (prev_set && REG_P (SET_DEST (prev_set)) ? REGNO (SET_DEST (prev_set)) : FIRST_PSEUDO_REGISTER); - unsigned int curr_dest_regno = (REG_P (SET_DEST (curr_set)) + unsigned int curr_dest_regno = (curr_set && REG_P (SET_DEST (curr_set)) ? REGNO (SET_DEST (curr_set)) : FIRST_PSEUDO_REGISTER); diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog index 33e12f1..8330846 100644 --- a/gcc/fortran/ChangeLog +++ b/gcc/fortran/ChangeLog @@ -1,3 +1,9 @@ +2025-07-18 Harald Anlauf <anlauf@gmx.de> + + PR fortran/121145 + * trans-expr.cc (gfc_conv_procedure_call): Do not create pointer + check for proc-pointer actual passed to optional dummy. + 2025-07-16 Paul Thomas <pault@gcc.gnu.org> PR fortran/121060 diff --git a/gcc/fortran/trans-expr.cc b/gcc/fortran/trans-expr.cc index 082987f..6fa52d0 100644 --- a/gcc/fortran/trans-expr.cc +++ b/gcc/fortran/trans-expr.cc @@ -8159,7 +8159,8 @@ gfc_conv_procedure_call (gfc_se * se, gfc_symbol * sym, msg = xasprintf ("Pointer actual argument '%s' is not " "associated", e->symtree->n.sym->name); else if (attr.proc_pointer && !e->value.function.actual - && (fsym == NULL || !fsym_attr.proc_pointer)) + && (fsym == NULL + || (!fsym_attr.proc_pointer && !fsym_attr.optional))) msg = xasprintf ("Proc-pointer actual argument '%s' is not " "associated", e->symtree->n.sym->name); else diff --git a/gcc/m2/ChangeLog b/gcc/m2/ChangeLog index f7254f9..fa93dfe 100644 --- a/gcc/m2/ChangeLog +++ b/gcc/m2/ChangeLog @@ -1,3 +1,9 @@ +2025-07-18 Gaius Mulley <gaiusmod2@gmail.com> + + PR modula2/121164 + * gm2-libs/ARRAYOFCHAR.mod (Write): Rename 2nd parameter + name a to str. + 2025-07-01 Gaius Mulley <gaiusmod2@gmail.com> PR modula2/120912 diff --git a/gcc/m2/gm2-libs/ARRAYOFCHAR.mod b/gcc/m2/gm2-libs/ARRAYOFCHAR.mod index f27378a..41aaf68 100644 --- a/gcc/m2/gm2-libs/ARRAYOFCHAR.mod +++ b/gcc/m2/gm2-libs/ARRAYOFCHAR.mod @@ -34,14 +34,14 @@ IMPORT StrLib ; Write - writes a string to file f. *) -PROCEDURE Write (f: File; a: ARRAY OF CHAR) ; +PROCEDURE Write (f: File; str: ARRAY OF CHAR) ; VAR len, i: CARDINAL ; BEGIN - len := StrLib.StrLen (a) ; + len := StrLib.StrLen (str) ; i := 0 ; WHILE i < len DO - WriteChar (f, a[i]) ; + WriteChar (f, str[i]) ; INC (i) END END Write ; diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 0818631..ad467e6 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,40 @@ +2025-07-18 Harald Anlauf <anlauf@gmx.de> + + PR fortran/121145 + * gfortran.dg/pointer_check_15.f90: New test. + +2025-07-18 Andrew Pinski <quic_apinski@quicinc.com> + + PR testsuite/121153 + * gcc.dg/vect/vect-reduc-cond-1.c: Require vect_condition. + * gcc.dg/vect/vect-reduc-cond-2.c: Likewise. + +2025-07-18 Pan Li <pan2.li@intel.com> + + * gcc.target/riscv/rvv/autovec/avg_data.h: Adjust the test data. + * gcc.target/riscv/rvv/autovec/avg_ceil-1-i64-from-i128.c: New test. + * gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i64-from-i128.c: New test. + +2025-07-18 Martin Jambor <mjambor@suse.cz> + + PR tree-optimization/117423 + * gcc.dg/tree-ssa/pr117423.c: New test. + +2025-07-18 Richard Biener <rguenther@suse.de> + + PR tree-optimization/121126 + * gcc.dg/vect/pr121126.c: New testcase. + +2025-07-18 Richard Biener <rguenther@suse.de> + + PR tree-optimization/120924 + * gcc.dg/uninit-pr120924.c: New testcase. + +2025-07-18 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/121131 + * gcc.dg/bitint-124.c: New test. + 2025-07-17 Jason Merrill <jason@redhat.com> PR c++/87097 diff --git a/gcc/testsuite/gcc.dg/vect/vect-reduc-cond-1.c b/gcc/testsuite/gcc.dg/vect/vect-reduc-cond-1.c index d8356b4..258f17e 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-reduc-cond-1.c +++ b/gcc/testsuite/gcc.dg/vect/vect-reduc-cond-1.c @@ -1,4 +1,5 @@ /* { dg-require-effective-target vect_int } */ +/* { dg-require-effective-target vect_condition } */ #include <stdarg.h> #include "tree-vect.h" diff --git a/gcc/testsuite/gcc.dg/vect/vect-reduc-cond-2.c b/gcc/testsuite/gcc.dg/vect/vect-reduc-cond-2.c index 80c1dba..126a50f 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-reduc-cond-2.c +++ b/gcc/testsuite/gcc.dg/vect/vect-reduc-cond-2.c @@ -1,4 +1,5 @@ /* { dg-require-effective-target vect_int } */ +/* { dg-require-effective-target vect_condition } */ /* { dg-additional-options "-fdump-tree-ifcvt-details" } */ #include <stdarg.h> diff --git a/gcc/testsuite/gcc.target/pru/pragma-ctable_entry-2.c b/gcc/testsuite/gcc.target/pru/pragma-ctable_entry-2.c new file mode 100644 index 0000000..a1c707d --- /dev/null +++ b/gcc/testsuite/gcc.target/pru/pragma-ctable_entry-2.c @@ -0,0 +1,22 @@ +/* Test for base addresses with bit 31 set (PR121124). */ + +/* { dg-do compile } */ +/* { dg-options "-O1" } */ + +/* -O1 in the options is significant. Without it LBCO/SBCO operations may + not be optimized to the respective instructions. */ + + +#pragma ctable_entry 12 0x80beef00 + +unsigned int +test_ctable (unsigned int val1, unsigned int val2) +{ + ((volatile unsigned short int *)0x80beef00)[0] = val2; + ((volatile unsigned int *)0x80beef00)[val1] = val2; + return ((volatile unsigned int *)0x80beef00)[5]; +} + +/* { dg-final { scan-assembler "sbco\\tr15.b\[012\]?, 12, 0, 2" } } */ +/* { dg-final { scan-assembler "sbco\\tr15.b0, 12, r14, 4" } } */ +/* { dg-final { scan-assembler "lbco\\tr14.b0, 12, 20, 4" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c index b17fd8e..811f26c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c @@ -13,6 +13,8 @@ DEF_VF_MULOP_ACC_CASE_0 (_Float16, +, -, nacc) DEF_VF_MULOP_ACC_CASE_0 (_Float16, -, -, nsac) DEF_VF_MULOP_WIDEN_CASE_0 (_Float16, float, +, +, acc) DEF_VF_MULOP_WIDEN_CASE_0 (_Float16, float, -, +, sac) +DEF_VF_MULOP_WIDEN_CASE_0 (_Float16, float, +, -, nacc) +DEF_VF_MULOP_WIDEN_CASE_0 (_Float16, float, -, -, nsac) /* { dg-final { scan-assembler-times {vfmadd.vf} 1 } } */ /* { dg-final { scan-assembler-times {vfmsub.vf} 1 } } */ @@ -24,3 +26,5 @@ DEF_VF_MULOP_WIDEN_CASE_0 (_Float16, float, -, +, sac) /* { dg-final { scan-assembler-times {vfnmsac.vf} 1 } } */ /* { dg-final { scan-assembler-times {vfwmacc.vf} 1 } } */ /* { dg-final { scan-assembler-times {vfwmsac.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfwnmacc.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfwnmsac.vf} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c index efd887d..ca82ead 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c @@ -13,6 +13,8 @@ DEF_VF_MULOP_ACC_CASE_0 (float, +, -, nacc) DEF_VF_MULOP_ACC_CASE_0 (float, -, -, nsac) DEF_VF_MULOP_WIDEN_CASE_0 (float, double, +, +, acc) DEF_VF_MULOP_WIDEN_CASE_0 (float, double, -, +, sac) +DEF_VF_MULOP_WIDEN_CASE_0 (float, double, +, -, nacc) +DEF_VF_MULOP_WIDEN_CASE_0 (float, double, -, -, nsac) /* { dg-final { scan-assembler-times {vfmadd.vf} 1 } } */ /* { dg-final { scan-assembler-times {vfmsub.vf} 1 } } */ @@ -24,3 +26,5 @@ DEF_VF_MULOP_WIDEN_CASE_0 (float, double, -, +, sac) /* { dg-final { scan-assembler-times {vfnmsac.vf} 1 } } */ /* { dg-final { scan-assembler-times {vfwmacc.vf} 1 } } */ /* { dg-final { scan-assembler-times {vfwmsac.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfwnmacc.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfwnmsac.vf} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c index 84987a9..3a39303 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c @@ -13,5 +13,7 @@ /* { dg-final { scan-assembler-not {vfnmsac.vf} } } */ /* { dg-final { scan-assembler-not {vfwmacc.vf} } } */ /* { dg-final { scan-assembler-not {vfwmsac.vf} } } */ -/* { dg-final { scan-assembler-times {fcvt.s.h} 2 } } */ -/* { dg-final { scan-assembler-times {vfmv.v.f} 10 } } */ +/* { dg-final { scan-assembler-not {vfwnmacc.vf} } } */ +/* { dg-final { scan-assembler-not {vfwnmsac.vf} } } */ +/* { dg-final { scan-assembler-times {fcvt.s.h} 4 } } */ +/* { dg-final { scan-assembler-times {vfmv.v.f} 12 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c index dbd3d02..b4618bae 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c @@ -13,5 +13,7 @@ /* { dg-final { scan-assembler-not {vfnmsac.vf} } } */ /* { dg-final { scan-assembler-not {vfwmacc.vf} } } */ /* { dg-final { scan-assembler-not {vfwmsac.vf} } } */ -/* { dg-final { scan-assembler-times {fcvt.d.s} 2 } } */ -/* { dg-final { scan-assembler-times {vfmv.v.f} 10 } } */ +/* { dg-final { scan-assembler-not {vfwnmacc.vf} } } */ +/* { dg-final { scan-assembler-not {vfwnmsac.vf} } } */ +/* { dg-final { scan-assembler-times {fcvt.d.s} 4 } } */ +/* { dg-final { scan-assembler-times {vfmv.v.f} 12 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c index 5f0d758..58afaa4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c @@ -13,6 +13,8 @@ DEF_VF_MULOP_ACC_CASE_1 (_Float16, +, -, nacc, VF_MULOP_ACC_BODY_X128) DEF_VF_MULOP_ACC_CASE_1 (_Float16, -, -, nsac, VF_MULOP_ACC_BODY_X128) DEF_VF_MULOP_WIDEN_CASE_1 (_Float16, float, +, +, acc) DEF_VF_MULOP_WIDEN_CASE_1 (_Float16, float, -, +, sac) +DEF_VF_MULOP_WIDEN_CASE_1 (_Float16, float, +, -, nacc) +DEF_VF_MULOP_WIDEN_CASE_1 (_Float16, float, -, -, nsac) /* { dg-final { scan-assembler {vfmadd.vf} } } */ /* { dg-final { scan-assembler {vfmsub.vf} } } */ @@ -24,3 +26,5 @@ DEF_VF_MULOP_WIDEN_CASE_1 (_Float16, float, -, +, sac) /* { dg-final { scan-assembler {vfnmsac.vf} } } */ /* { dg-final { scan-assembler {vfwmacc.vf} } } */ /* { dg-final { scan-assembler {vfwmsac.vf} } } */ +/* { dg-final { scan-assembler {vfwnmacc.vf} } } */ +/* { dg-final { scan-assembler {vfwnmsac.vf} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c index 951b0ef..0e95774 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c @@ -13,6 +13,8 @@ DEF_VF_MULOP_ACC_CASE_1 (float, +, -, nacc, VF_MULOP_ACC_BODY_X128) DEF_VF_MULOP_ACC_CASE_1 (float, -, -, nsac, VF_MULOP_ACC_BODY_X128) DEF_VF_MULOP_WIDEN_CASE_1 (float, double, +, +, acc) DEF_VF_MULOP_WIDEN_CASE_1 (float, double, -, +, sac) +DEF_VF_MULOP_WIDEN_CASE_1 (float, double, +, -, nacc) +DEF_VF_MULOP_WIDEN_CASE_1 (float, double, -, -, nsac) /* { dg-final { scan-assembler {vfmadd.vf} } } */ /* { dg-final { scan-assembler {vfmsub.vf} } } */ @@ -24,3 +26,5 @@ DEF_VF_MULOP_WIDEN_CASE_1 (float, double, -, +, sac) /* { dg-final { scan-assembler {vfnmsac.vf} } } */ /* { dg-final { scan-assembler {vfwmacc.vf} } } */ /* { dg-final { scan-assembler {vfwmsac.vf} } } */ +/* { dg-final { scan-assembler {vfwnmacc.vf} } } */ +/* { dg-final { scan-assembler {vfwnmsac.vf} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c index a4edd92..559df6c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c @@ -13,4 +13,6 @@ /* { dg-final { scan-assembler-not {vfnmsac.vf} } } */ /* { dg-final { scan-assembler-not {vfwmacc.vf} } } */ /* { dg-final { scan-assembler-not {vfwmsac.vf} } } */ +/* { dg-final { scan-assembler-not {vfwnmacc.vf} } } */ +/* { dg-final { scan-assembler-not {vfwnmsac.vf} } } */ /* { dg-final { scan-assembler {fcvt.s.h} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c index 4eb28e5..03f9c5a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c @@ -13,4 +13,6 @@ /* { dg-final { scan-assembler-not {vfnmsac.vf} } } */ /* { dg-final { scan-assembler-not {vfwmacc.vf} } } */ /* { dg-final { scan-assembler-not {vfwmsac.vf} } } */ +/* { dg-final { scan-assembler-not {vfwnmacc.vf} } } */ +/* { dg-final { scan-assembler-not {vfwnmsac.vf} } } */ /* { dg-final { scan-assembler {fcvt.d.s} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f16.c new file mode 100644 index 0000000..6be7d72 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f16.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-march=rv64gcv_zvfh --param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" + +#define T1 _Float16 +#define T2 float +#define NAME nacc +#define OP + +#define NEG - + +DEF_VF_MULOP_WIDEN_CASE_0_WRAP (T1, T2, OP, NEG, NAME) + +#define TEST_RUN(T1, T2, NAME, out, in, f, n) RUN_VF_MULOP_WIDEN_CASE_0_WRAP(T1, T2, NAME, out, in, f, n) +#define LIMIT -32768 + +#include "vf_mulop_widen_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f32.c new file mode 100644 index 0000000..851c335 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f32.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" + +#define T1 float +#define T2 double +#define NAME nacc +#define OP + +#define NEG - + +DEF_VF_MULOP_WIDEN_CASE_0_WRAP (T1, T2, OP, NEG, NAME) + +#define TEST_RUN(T1, T2, NAME, out, in, f, n) RUN_VF_MULOP_WIDEN_CASE_0_WRAP(T1, T2, NAME, out, in, f, n) +#define LIMIT -2147483648 + +#include "vf_mulop_widen_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f16.c new file mode 100644 index 0000000..dd28234 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f16.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-march=rv64gcv_zvfh --param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" + +#define T1 _Float16 +#define T2 float +#define NAME nsac +#define OP - +#define NEG - + +DEF_VF_MULOP_WIDEN_CASE_0_WRAP (T1, T2, OP, NEG, NAME) + +#define TEST_RUN(T1, T2, NAME, out, in, f, n) RUN_VF_MULOP_WIDEN_CASE_0_WRAP(T1, T2, NAME, out, in, f, n) +#define LIMIT -32768 + +#include "vf_mulop_widen_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f32.c new file mode 100644 index 0000000..9eacace --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f32.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" + +#define T1 float +#define T2 double +#define NAME nsac +#define OP - +#define NEG - + +DEF_VF_MULOP_WIDEN_CASE_0_WRAP (T1, T2, OP, NEG, NAME) + +#define TEST_RUN(T1, T2, NAME, out, in, f, n) RUN_VF_MULOP_WIDEN_CASE_0_WRAP(T1, T2, NAME, out, in, f, n) +#define LIMIT -2147483648 + +#include "vf_mulop_widen_run.h" diff --git a/gcc/testsuite/gfortran.dg/pointer_check_15.f90 b/gcc/testsuite/gfortran.dg/pointer_check_15.f90 new file mode 100644 index 0000000..13c6820 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/pointer_check_15.f90 @@ -0,0 +1,46 @@ +! { dg-do run } +! { dg-additional-options "-O -fcheck=pointer -fdump-tree-original" } +! +! PR fortran/121145 +! Erroneous runtime error: Proc-pointer actual argument 'ptr' is not associated +! +! Contributed by Federico Perini. + +module m + implicit none + + abstract interface + subroutine fun(x) + real, intent(in) :: x + end subroutine fun + end interface + +contains + + subroutine with_fun(sub) + procedure(fun), optional :: sub + if (present(sub)) stop 1 + end subroutine + + subroutine with_non_optional(sub) + procedure(fun) :: sub + end subroutine + +end module m + +program p + use m + implicit none + + procedure(fun), pointer :: ptr1 => null() + procedure(fun), pointer :: ptr2 => null() + + call with_fun() + call with_fun(sub=ptr1) ! no runtime check here + + if (associated (ptr2)) then + call with_non_optional(sub=ptr2) ! runtime check here + end if +end + +! { dg-final { scan-tree-dump-times "Proc-pointer actual argument .'ptr2.'" 1 "original" } } diff --git a/libgomp/ChangeLog b/libgomp/ChangeLog index 4f52a19..4978c9c 100644 --- a/libgomp/ChangeLog +++ b/libgomp/ChangeLog @@ -1,3 +1,10 @@ +2025-07-18 Andrew Stubbs <ams@baylibre.com> + + PR target/121156 + * config/gcn/bar.c (gomp_team_barrier_wait_end): Remove unused + "generation" variable. + (gomp_team_barrier_wait_cancel_end): Likewise. + 2025-07-17 Thomas Schwinge <tschwinge@baylibre.com> PR target/119692 diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog index 013b16a..b60a96f 100644 --- a/libstdc++-v3/ChangeLog +++ b/libstdc++-v3/ChangeLog @@ -1,3 +1,102 @@ +2025-07-18 Jonathan Wakely <jwakely@redhat.com> + + * include/bits/stl_iterator_base_types.h (__any_input_iterator): + Only define when __cpp_lib_concepts is defined. + +2025-07-18 Jonathan Wakely <jwakely@redhat.com> + + * doc/xml/manual/appendix_contributing.xml: Remove Paolo from + list of maintainers to contact about contributing. + * doc/html/manual/appendix_contributing.html: Regenerate. + +2025-07-18 Jonathan Wakely <jwakely@redhat.com> + + * doc/xml/manual/build_hacking.xml: Document that + windows_zones-map.h is a generated file. + * doc/html/manual/appendix_porting.html: Regenerate. + +2025-07-18 Tomasz Kamiński <tkaminsk@redhat.com> + + PR libstdc++/119137 + * include/std/inplace_vector (inplace_vector::operator=): + Qualify call to std::addressof. + +2025-07-18 Tomasz Kamiński <tkaminsk@redhat.com> + + PR libstdc++/121154 + * include/bits/chrono_io.h (_ChronoSpec::_M_time_point): Remove. + (_ChronoSpec::_M_needs_ok_check): Define + (__formatter_chrono::_M_parse): Set _M_needs_ok_check. + (__formatter_chrono::_M_check_ok): Check values also for debug mode, + and return __string_view. + (__formatter_chrono::_M_format_to): Handle results of _M_check_ok. + (__formatter_chrono::_M_wi, __formatter_chrono::_M_a_A) + (__formatter_chrono::_M_b_B, __formatter_chrono::_M_C_y_Y) + (__formatter_chrono::_M_d_e, __formatter_chrono::_M_F): + Removed handling of _M_debug. + (__formatter_chrono::__M_m): Print zero unpadded in _M_debug mode. + (__formatter_duration::_S_spec_for): Remove _M_time_point refernce. + (__formatter_duration::_M_parse): Override _M_needs_ok_check. + * testsuite/std/time/month/io.cc: Test for localized !ok() values. + * testsuite/std/time/weekday/io.cc: Test for localized !ok() values. + +2025-07-18 Jonathan Wakely <jwakely@redhat.com> + + PR libstdc++/121150 + * testsuite/20_util/hash/int128.cc: Cast expected values to + size_t. + +2025-07-18 Jonathan Wakely <jwakely@redhat.com> + + * include/bits/unicode.h (_Utf_iterator::operator--): Reorder + conditions and update position after reading a code unit. + (_Utf_iterator::_M_read_reverse): Define. + (_Utf_iterator::_M_read_utf8): Return extracted code point. + (_Utf_iterator::_M_read_reverse_utf8): Define. + (_Utf_iterator::_M_read_reverse_utf16): Define. + (_Utf_iterator::_M_read_reverse_utf32): Define. + * testsuite/ext/unicode/view.cc: Add checks for reversed views + and reverse iteration. + +2025-07-18 Jonathan Wakely <jwakely@redhat.com> + + * include/bits/unicode.h (_Utf_iterator): Reorder data members + to be more compact. + +2025-07-18 Jonathan Wakely <jwakely@redhat.com> + Tomasz Kamiński <tkaminsk@redhat.com> + + PR libstdc++/119137 + * doc/doxygen/user.cfg.in (INPUT): Add new header. + * include/Makefile.am: Add new header. + * include/Makefile.in: Regenerate. + * include/bits/stl_iterator_base_types.h (__any_input_iterator): + Define. + * include/bits/version.def (inplace_vector): Define. + * include/bits/version.h: Regenerate. + * include/precompiled/stdc++.h: Include new header. + * src/c++23/std.cc.in: Export contents if new header. + * include/std/inplace_vector: New file. + * testsuite/23_containers/inplace_vector/access/capacity.cc: New file. + * testsuite/23_containers/inplace_vector/access/elem.cc: New file. + * testsuite/23_containers/inplace_vector/access/elem_neg.cc: New file. + * testsuite/23_containers/inplace_vector/cons/1.cc: New file. + * testsuite/23_containers/inplace_vector/cons/from_range.cc: New file. + * testsuite/23_containers/inplace_vector/cons/throws.cc: New file. + * testsuite/23_containers/inplace_vector/copy.cc: New file. + * testsuite/23_containers/inplace_vector/erasure.cc: New file. + * testsuite/23_containers/inplace_vector/modifiers/assign.cc: New file. + * testsuite/23_containers/inplace_vector/modifiers/erase.cc: New file. + * testsuite/23_containers/inplace_vector/modifiers/multi_insert.cc: + New file. + * testsuite/23_containers/inplace_vector/modifiers/single_insert.cc: + New file. + * testsuite/23_containers/inplace_vector/move.cc: New file. + * testsuite/23_containers/inplace_vector/relops.cc: New file. + * testsuite/23_containers/inplace_vector/version.cc: New file. + * testsuite/util/testsuite_iterators.h (input_iterator_wrapper::base): + Define. + 2025-07-17 Jonathan Wakely <jwakely@redhat.com> PR libstdc++/96710 diff --git a/libstdc++-v3/include/bits/stl_iterator_base_types.h b/libstdc++-v3/include/bits/stl_iterator_base_types.h index 71da909..0c34ad7 100644 --- a/libstdc++-v3/include/bits/stl_iterator_base_types.h +++ b/libstdc++-v3/include/bits/stl_iterator_base_types.h @@ -258,11 +258,13 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION concept __has_input_iter_cat = is_convertible_v<__iter_category_t<_InIter>, input_iterator_tag>; +#ifdef __cpp_lib_concepts // Is a Cpp17InputIterator or satisfies std::input_iterator. template<typename _InIterator> concept __any_input_iterator = input_iterator<_InIterator> || __has_input_iter_cat<_InIterator>; #endif +#endif template<typename _It, typename _Cat = __iter_category_t<_It>> |