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authorJonathan Wright <jonathan.wright@arm.com>2021-03-04 12:36:09 +0000
committerJonathan Wright <jonathan.wright@arm.com>2021-05-19 14:44:10 +0100
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parent3eddaad02dcce21fb67c42cc6e1e8f951a630ac1 (diff)
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aarch64: Relax aarch64_<sur>q<r>shr<u>n2_n<mode> RTL pattern
Implement saturating right-shift and narrow high Neon intrinsic RTL patterns using a vec_concat of a register_operand and a VQSHRN_N unspec - instead of just a VQSHRN_N unspec. This more relaxed pattern allows for more aggressive combinations and ultimately better code generation. gcc/ChangeLog: 2021-03-04 Jonathan Wright <jonathan.wright@arm.com> * config/aarch64/aarch64-simd.md (aarch64_<sur>q<r>shr<u>n2_n<mode>): Implement as an expand emitting a big/little endian instruction pattern. (aarch64_<sur>q<r>shr<u>n2_n<mode>_insn_le): Define. (aarch64_<sur>q<r>shr<u>n2_n<mode>_insn_be): Define.
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