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| author | Andrew Stubbs <ams@codesourcery.com> | 2023-11-10 09:43:21 +0000 |
|---|---|---|
| committer | Andrew Stubbs <ams@codesourcery.com> | 2023-11-10 17:57:04 +0000 |
| commit | cc84a60af0c76d15cf3c2508238ba3616b943f13 (patch) | |
| tree | 023abbf6998e833e50609c8f0aff43e68c91f5c4 /gcc | |
| parent | 3312ab3b34bfcb63aac21c8aef992f373850fe45 (diff) | |
| download | gcc-cc84a60af0c76d15cf3c2508238ba3616b943f13.zip gcc-cc84a60af0c76d15cf3c2508238ba3616b943f13.tar.gz gcc-cc84a60af0c76d15cf3c2508238ba3616b943f13.tar.bz2 | |
amdgcn: Fix vector min/max ICE
The DImode min/max instructions need a clobber that SImode does not, so
add the special case to the reduction expand code.
gcc/ChangeLog:
* config/gcn/gcn.cc (gcn_expand_reduc_scalar): Add clobber to DImode
min/max instructions.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog.omp | 8 | ||||
| -rw-r--r-- | gcc/config/gcn/gcn.cc | 10 |
2 files changed, 17 insertions, 1 deletions
diff --git a/gcc/ChangeLog.omp b/gcc/ChangeLog.omp index c0a30ee..02f3ac2 100644 --- a/gcc/ChangeLog.omp +++ b/gcc/ChangeLog.omp @@ -3,6 +3,14 @@ Backport from mainline: Andrew Stubbs <ams@codesourcery.com> + * config/gcn/gcn.cc (gcn_expand_reduc_scalar): Add clobber to DImode + min/max instructions. + +2023-11-10 Andrew Stubbs <ams@codesourcery.com> + + Backport from mainline: + Andrew Stubbs <ams@codesourcery.com> + * config/gcn/gcn-valu.md (vec_extract<V_1REG:mode><V_1REG_ALT:mode>_nop): Mention "operands" in condition to silence the warnings. diff --git a/gcc/config/gcn/gcn.cc b/gcc/config/gcn/gcn.cc index 02964b0..eb1232a 100644 --- a/gcc/config/gcn/gcn.cc +++ b/gcc/config/gcn/gcn.cc @@ -5553,7 +5553,15 @@ gcn_expand_reduc_scalar (machine_mode mode, rtx src, int unspec) { rtx tmp = gen_reg_rtx (mode); emit_insn (gen_dpp_move (mode, tmp, in, shift_val)); - emit_insn (gen_rtx_SET (out, gen_rtx_fmt_ee (code, mode, tmp, in))); + rtx insn = gen_rtx_SET (out, gen_rtx_fmt_ee (code, mode, tmp, in)); + if (scalar_mode == DImode) + { + rtx clobber = gen_rtx_CLOBBER (VOIDmode, + gen_rtx_REG (DImode, VCC_REG)); + insn = gen_rtx_PARALLEL (VOIDmode, + gen_rtvec (2, insn, clobber)); + } + emit_insn (insn); } else { |