s390: Rework signbit optab

Currently for a signbit operation instructions tc{f,d,x}b + ipm + srl
are emitted.  If the source operand is a MEM, then a load precedes the
sequence.  A faster implementation is by issuing a load either from a
REG or MEM into a GPR followed by a shift.

In spirit of the signbit function of the C standard, the signbit optab
only guarantees that the resulting value is nonzero if the signbit is
set.  The common code implementation computes a value where the signbit
is stored in the most significant bit, i.e., all other bits are just
masked out, whereas the current implementation of s390 results in a
value where the signbit is stored in the least significant bit.
Although, there is no guarantee where the signbit is stored, keep the
current behaviour and, therefore, implement the signbit optab manually.

Since z10, instruction lgdr can be effectively used for a 64-bit
FPR-to-GPR load.  However, there exists no 32-bit pendant.  Thus, for
target z10 make use of post-reload splitters which emit either a 64-bit
or a 32-bit load depending on whether the source operand is a REG or a
MEM and a corresponding 63 or 31-bit shift.  We can do without
post-reload splitter in case of vector extensions since there we also
have a 32-bit VR-to-GPR load via instruction vlgvf.

gcc/ChangeLog:

	* config/s390/s390.md (signbit_tdc): Rename expander.
	(signbit<mode>2): New expander.
	(signbit<mode>2_z10): New expander.

gcc/testsuite/ChangeLog:

	* gcc.target/s390/isfinite-isinf-isnormal-signbit-2.c: Adapt
	scan assembler directives.
	* gcc.target/s390/isfinite-isinf-isnormal-signbit-3.c: Ditto.
	* gcc.target/s390/signbit-1.c: New test.
	* gcc.target/s390/signbit-2.c: New test.
	* gcc.target/s390/signbit-3.c: New test.
	* gcc.target/s390/signbit-4.c: New test.
	* gcc.target/s390/signbit-5.c: New test.
	* gcc.target/s390/signbit.h: New test.

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