RISC-V: Support load/store in mov<mode> pattern for RVV modes.

gcc/ChangeLog:

	* config.gcc (riscv*): Add riscv-v.o to extra_objs.
	* config/riscv/constraints.md (vu): New constraint.
	(vi): Ditto.
	(Wc0): Ditto.
	(Wc1): Ditto.
	* config/riscv/predicates.md (vector_length_operand): New.
	(reg_or_mem_operand): Ditto.
	(vector_move_operand): Ditto.
	(vector_mask_operand): Ditto.
	(vector_merge_operand): Ditto.
	* config/riscv/riscv-protos.h (riscv_regmode_natural_size) New.
	(riscv_vector::const_vec_all_same_in_range_p): Ditto.
	(riscv_vector::legitimize_move): Ditto.
	(tail_policy): Ditto.
	(mask_policy): Ditto.
	* config/riscv/riscv-v.cc: New.
	* config/riscv/riscv-vector-builtins-bases.cc
	(vsetvl::expand): Refactor how LMUL encoding.
	* config/riscv/riscv.cc (riscv_print_operand): Update how LMUL
	print and mask operand print.
	(riscv_regmode_natural_size): New.
	* config/riscv/riscv.h (REGMODE_NATURAL_SIZE): New.
	* config/riscv/riscv.md (mode): Add vector modes.
	* config/riscv/t-riscv (riscv-v.o) New.
	* config/riscv/vector-iterators.md: New.
	* config/riscv/vector.md (vundefined<mode>): New.
	(mov<mode>): New.
	(*mov<mode>): New.
	(@vsetvl<mode>_no_side_effects): New.
	(@pred_mov<mode>): New.

gcc/testsuite/ChangeLog:
	* gcc.target/riscv/rvv/base/mov-1.c: New.
	* gcc.target/riscv/rvv/base/mov-10.c: New.
	* gcc.target/riscv/rvv/base/mov-11.c: New.
	* gcc.target/riscv/rvv/base/mov-12.c: New.
	* gcc.target/riscv/rvv/base/mov-13.c: New.
	* gcc.target/riscv/rvv/base/mov-2.c: New.
	* gcc.target/riscv/rvv/base/mov-3.c: New.
	* gcc.target/riscv/rvv/base/mov-4.c: New.
	* gcc.target/riscv/rvv/base/mov-5.c: New.
	* gcc.target/riscv/rvv/base/mov-6.c: New.
	* gcc.target/riscv/rvv/base/mov-7.c: New.
	* gcc.target/riscv/rvv/base/mov-8.c: New.
	* gcc.target/riscv/rvv/base/mov-9.c: New.

1 files changed, 1 insertions, 1 deletions

diff --git a/gcc/config.gcc b/gcc/config.gcc
index 52f9e98..e8fe623 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -516,7 +516,7 @@ pru-*-*)
 	;;
 riscv*)
 	cpu_type=riscv
-	extra_objs="riscv-builtins.o riscv-c.o riscv-sr.o riscv-shorten-memrefs.o riscv-selftests.o"
+	extra_objs="riscv-builtins.o riscv-c.o riscv-sr.o riscv-shorten-memrefs.o riscv-selftests.o riscv-v.o"
 	extra_objs="${extra_objs} riscv-vector-builtins.o riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o"
 	d_target_objs="riscv-d.o"
 	extra_headers="riscv_vector.h"