RISC-V: Combine vec_duplicate + vaadd.vv to vaadd.vx on GR2VR cost

This patch would like to combine the vec_duplicate + vaadd.vv to the
vaadd.vx.  From example as below code.  The related pattern will depend
on the cost of vec_duplicate from GR2VR.  Then the late-combine will
take action if the cost of GR2VR is zero, and reject the combination
if the GR2VR cost is greater than zero.

Assume we have example code like below, GR2VR cost is 0.

  #define DEF_AVG_FLOOR(NT, WT)        \
  NT                                   \
  test_##NT##_avg_floor(NT x, NT y)    \
  {                                    \
    return (NT)(((WT)x + (WT)y) >> 1); \
  }

  #define AVG_FLOOR_FUNC(T)      test_##T##_avg_floor

  DEF_AVG_FLOOR(int32_t, int64_t)
  DEF_VX_BINARY_CASE_2_WRAP(T, AVG_FLOOR_FUNC(T), avg_floor)

Before this patch:
  11   │     beq a3,zero,.L8
  12   │     vsetvli a5,zero,e32,m1,ta,ma
  13   │     vmv.v.x v2,a2
  14   │     slli    a3,a3,32
  15   │     srli    a3,a3,32
  16   │ .L3:
  17   │     vsetvli a5,a3,e32,m1,ta,ma
  18   │     vle32.v v1,0(a1)
  19   │     slli    a4,a5,2
  20   │     sub a3,a3,a5
  21   │     add a1,a1,a4
  22   │     vaadd.vv v1,v1,v2
  23   │     vse32.v v1,0(a0)
  24   │     add a0,a0,a4
  25   │     bne a3,zero,.L3

After this patch:
  11   │     beq a3,zero,.L8
  12   │     slli    a3,a3,32
  13   │     srli    a3,a3,32
  14   │ .L3:
  15   │     vsetvli a5,a3,e32,m1,ta,ma
  16   │     vle32.v v1,0(a1)
  17   │     slli    a4,a5,2
  18   │     sub a3,a3,a5
  19   │     add a1,a1,a4
  20   │     vaadd.vx v1,v1,a2
  21   │     vse32.v v1,0(a0)
  22   │     add a0,a0,a4
  23   │     bne a3,zero,.L3

gcc/ChangeLog:

	* config/riscv/riscv-v.cc (expand_vx_binary_vxrm_vec_vec_dup):
	Add new case UNSPEC_VAADD.
	(expand_vx_binary_vxrm_vec_dup_vec): Ditto.
	* config/riscv/riscv.cc (riscv_rtx_costs): Ditto.
	* config/riscv/vector-iterators.md: Add new case UNSPEC_VAADD to
	iterator.

Signed-off-by: Pan Li <pan2.li@intel.com>

3 files changed, 7 insertions, 4 deletions

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 54eb8c6..c9c8328 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -5693,6 +5693,7 @@ expand_vx_binary_vxrm_vec_vec_dup (rtx op_0, rtx op_1, rtx op_2, int unspec,
 
   switch (unspec)
     {
+    case UNSPEC_VAADD:
     case UNSPEC_VAADDU:
       icode = code_for_pred_scalar (unspec, mode);
       break;
@@ -5717,6 +5718,7 @@ expand_vx_binary_vxrm_vec_dup_vec (rtx op_0, rtx op_1, rtx op_2, int unspec,
 
   switch (unspec)
     {
+    case UNSPEC_VAADD:
     case UNSPEC_VAADDU:
       icode = code_for_pred_scalar (unspec, mode);
       break;
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index b4f2d13..0a9fcef 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -4040,6 +4040,7 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
 			switch (XINT (op, 1))
 			  {
 			  case UNSPEC_VAADDU:
+			  case UNSPEC_VAADD:
 			    *total
 			      = get_vector_binary_rtx_cost (op, scalar2vr_cost);
 			    break;
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index dbb48a4..aa3b6fb 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -4014,11 +4014,11 @@
 			      UNSPEC_VSSRL UNSPEC_VSSRA])
 
 (define_int_iterator VSAT_VX_OP_V_VDUP [
-  UNSPEC_VAADDU
+  UNSPEC_VAADDU UNSPEC_VAADD
 ])
 
 (define_int_iterator VSAT_VX_OP_VDUP_V [
-  UNSPEC_VAADDU
+  UNSPEC_VAADDU UNSPEC_VAADD
 ])
 
 (define_int_iterator VSAT_ARITH_OP [UNSPEC_VAADDU UNSPEC_VAADD
@@ -4056,11 +4056,11 @@
 				(UNSPEC_VNCLIPU "vnclip")])
 
 (define_int_attr sat_op_v_vdup [
-  (UNSPEC_VAADDU "aaddu")
+  (UNSPEC_VAADDU "aaddu") (UNSPEC_VAADD "aadd")
 ])
 
 (define_int_attr sat_op_vdup_v [
-  (UNSPEC_VAADDU "aaddu")
+  (UNSPEC_VAADDU "aaddu") (UNSPEC_VAADD "aadd")
 ])
 
 (define_int_attr misc_op [(UNSPEC_VMSBF "sbf") (UNSPEC_VMSIF "sif") (UNSPEC_VMSOF "sof")