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| author | Pan Li <pan2.li@intel.com> | 2025-07-25 22:11:13 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2025-07-27 11:12:34 +0800 |
| commit | 62f8a246bbaa1a1f5aedba4c84f7fe4c7eca799f (patch) | |
| tree | b6458e4bf3baeac246e3d55a88bdbb21677672c6 | |
| parent | fb9e54393dc12f3d87abad454651262061736e9c (diff) | |
| download | gcc-62f8a246bbaa1a1f5aedba4c84f7fe4c7eca799f.zip gcc-62f8a246bbaa1a1f5aedba4c84f7fe4c7eca799f.tar.gz gcc-62f8a246bbaa1a1f5aedba4c84f7fe4c7eca799f.tar.bz2 | |
RISC-V: Fix another vf FP16 combine run test failures
Like Robin's fix for vf combine f16.c run tests, there is still
another failures similar. This patch would like to fix it as
previous.
will commit it directly if the CI agrees.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f16.c:
Add zvfh requirements and options.
* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f16.c:
Ditto.
Signed-off-by: Pan Li <pan2.li@intel.com>
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f16.c | 6 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f16.c | 6 |
2 files changed, 10 insertions, 2 deletions
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f16.c index 6be7d72..ddf49d5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f16.c @@ -1,5 +1,9 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-march=rv64gcv_zvfh --param=fpr2vr-cost=0" } */ +/* { dg-require-effective-target riscv_v_ok } */ +/* { dg-require-effective-target riscv_zvfh } */ +/* { dg-add-options "riscv_v" } */ +/* { dg-add-options "riscv_zvfh" } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ #include "vf_mulop.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f16.c index dd28234..a874991 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f16.c @@ -1,5 +1,9 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-march=rv64gcv_zvfh --param=fpr2vr-cost=0" } */ +/* { dg-require-effective-target riscv_v_ok } */ +/* { dg-require-effective-target riscv_zvfh } */ +/* { dg-add-options "riscv_v" } */ +/* { dg-add-options "riscv_zvfh" } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ #include "vf_mulop.h" |