From 3fd229a447cd28a70bfd921f617bc6c3553b8fdd Mon Sep 17 00:00:00 2001 From: Sudakshina Das Date: Wed, 26 Sep 2018 10:54:07 +0100 Subject: [PATCH, BINUTILS, AARCH64, 5/9] Add DC CVADP instruction This patch is part of the patch series to add support for ARMv8.5-A extensions. (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order/dc-data-cache-operation-an-alias-of-sys) This patch adds the DC CVADP instruction. Since this has a separate identification mechanism a new feature bit is added. *** include/ChangeLog *** 2018-10-09 Sudakshina Das * opcode/aarch64.h (AARCH64_FEATURE_CVADP): New. *** opcodes/ChangeLog *** 2018-10-09 Sudakshina Das * aarch64-opc.c (aarch64_sys_regs_dc): New entry for cvadp. (aarch64_sys_ins_reg_supported_p): New check for above. *** gas/ChangeLog *** 2018-10-09 Sudakshina Das * testsuite/gas/aarch64/sysreg-4.s: Test instruction. * testsuite/gas/aarch64/sysreg-4.d: Likewise. * testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise. --- include/opcode/aarch64.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'include/opcode') diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 7b542c9..7656a57 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -72,6 +72,8 @@ typedef uint32_t aarch64_insn; #define AARCH64_FEATURE_SB 0x10000000000ULL /* Execution and Data Prediction Restriction instructions. */ #define AARCH64_FEATURE_PREDRES 0x20000000000ULL +/* DC CVADP. */ +#define AARCH64_FEATURE_CVADP 0x40000000000ULL /* Architectures are the sum of the base and extensions. */ #define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \ @@ -100,7 +102,8 @@ typedef uint32_t aarch64_insn; | AARCH64_FEATURE_FLAGMANIP \ | AARCH64_FEATURE_FRINTTS \ | AARCH64_FEATURE_SB \ - | AARCH64_FEATURE_PREDRES) + | AARCH64_FEATURE_PREDRES \ + | AARCH64_FEATURE_CVADP) #define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0) -- cgit v1.1