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2022-03-16Delete PowerPC macro insn supportAlan Modra1-18/+0
Let's hope this stays dead, but it's here as a patch separate from those that removed use of powerpc_macros just in case it needs to be resurrected. include/ * opcode/ppc.h (struct powerpc_macro): Delete declaration. (powerpc_macros, powerpc_num_macros): Likewise.. opcodes/ * ppc-opc.c (powerpc_macros, powerpc_num_macros): Delete. gas/ * config/tc-ppc.c (ppc_macro): Delete function. (ppc_macro_hash): Delete. (ppc_setup_opcodes, md_assemble): Delete macro support.
2022-03-16PowerPC SPE/SPE2 aliases in powerpc_macrosAlan Modra1-30/+27
* ppc-opc.c (powerpc_macros): Move "evsadd", "evssub", "evsabs", "evsnabs", "evsneg", "evsmul", "evsdiv", "evscmpgt", "evsgmplt", "evsgmpeq", "evscfui", "evscfsi", "evscfuf", "evscfsf", "evsctui", "evsctsi", "evsctuf", "evsctsf", "evsctuiz", "evsctsiz", "evststgt", "evststlt", "evststeq".. (powerpc_opcodes): ..to here. (powerpc_macros): Move "evdotphsssi", "evdotphsssia", "evdotpwsssi", and "evdotpwsssia".. (spe2_opcodes): ..to here.
2022-03-16PowerPC VLE extended instructions in powerpc_macrosAlan Modra1-13/+10
This moves VLE insn out of the macro table. "e_slwi" and "e_srwi" already exist in vle_opcodes as distinct instructions rather than encodings of e_rlwinm. opcodes/ * ppc-opc.c (vle_opcodes): Typo fix e_rlwinm operand. Add "e_inslwi", "e_insrwi", "e_rotlwi", "e_rotrwi", "e_clrlwi", "e_clrrwi", "e_extlwi", "e_extrwi", and "e_clrlslwi". (powerpc_macros): Delete same. Delete "e_slwi" and "e_srwi" too. gas/ * testsuite/gas/ppc/vle-simple-5.d: Update.
2022-03-16PowerPC32 extended instructions in powerpc_macrosAlan Modra1-25/+296
As for PowerPC64, move instructions to the main opcode table. opcodes/ * ppc-opc.c (insert_crwn, extract_crwn, insert_elwn, extract_elwn), (insert_erwn, extract_erwn, insert_erwb, extract_erwb), (insert_cslwn, extract_cslwb, insert_ilwb, extract_ilwn), (insert_irwb, extract_irwn, insert_rrwn, extract_rrwn), (insert_slwn, extract_slwn, insert_srwn, extract_srwn): New functions. (CRWn, ELWn, ERWn, ERWb, CSLWb, CSLWn, ILWn, ILWb, IRWn, IRWb), (RRWn, SLWn, SRWn): Define and add powerpc_operands entries. (MMB_MASK, MME_MASK, MSHMB_MASK): Define. (powerpc_opcodes): Add "inslwi", "insrwi", "rotrwi", "clrrwi", "slwi", "srwi", "extlwi", "extrwi", "sli", "sri" and corresponding record (ie. dot suffix) forms. (powerpc_macros): Delete same. gas/ * testsuite/gas/ppc/476.d: Update. * testsuite/gas/ppc/simpshft.d: Update.
2022-03-16PowerPC64 extended instructions in powerpc_macrosAlan Modra1-19/+245
The extended instructions implemented in powerpc_macros aren't used by the disassembler. That means instructions like "sldi r3,r3,2" appear in disassembly as "rldicr r3,r3,2,61", which is annoying since many other extended instructions are shown. Note that some of the instructions moved out of the macro table to the opcode table won't appear in disassembly, because they are aliases rather than a subset of the underlying raw instruction. If enabled, rotrdi, extrdi, extldi, clrlsldi, and insrdi would replace all occurrences of rotldi, rldicl, rldicr, rldic and rldimi. (Or many occurrences in the case of clrlsldi if n <= b was added to the extract functions.) The patch also fixes a small bug in opcode sanity checking. include/ * opcode/ppc.h (PPC_OPSHIFT_SH6): Define. opcodes/ * ppc-opc.c (insert_erdn, extract_erdn, insert_eldn, extract_eldn), (insert_crdn, extract_crdn, insert_rrdn, extract_rrdn), (insert_sldn, extract_sldn, insert_srdn, extract_srdn), (insert_erdb, extract_erdb, insert_csldn, extract_csldb), (insert_irdb, extract_irdn): New functions. (ELDn, ERDn, ERDn, RRDn, SRDn, ERDb, CSLDn, CSLDb, IRDn, IRDb): Define and add associated powerpc_operands entries. (powerpc_opcodes): Add "rotrdi", "srdi", "extrdi", "clrrdi", "sldi", "extldi", "clrlsldi", "insrdi" and corresponding record (ie. dot suffix) forms. (powerpc_macros): Delete same from here. gas/ * config/tc-ppc.c (insn_validate): Don't modify value passed to operand->insert for PPC_OPERAND_PLUS1 when calculating mask. Handle PPC_OPSHIFT_SH6. * testsuite/gas/ppc/prefix-reloc.d: Update. * testsuite/gas/ppc/simpshft.d: Update. ld/ * testsuite/ld-powerpc/elfv2so.d: Update. * testsuite/ld-powerpc/notoc.d: Update. * testsuite/ld-powerpc/notoc3.d: Update. * testsuite/ld-powerpc/tlsdesc2.d: Update. * testsuite/ld-powerpc/tlsget.d: Update. * testsuite/ld-powerpc/tlsget2.d: Update. * testsuite/ld-powerpc/tlsopt5.d: Update. * testsuite/ld-powerpc/tlsopt6.d: Update.
2022-03-14PR28959, obdump doesn't disassemble mftb instructionAlan Modra1-2/+3
Without a -M cpu option given, powerpc objdump defaults currently to -Mpower10 but -Many is also given. Commit 1ff6a3b8e562 regressed -Many disassembly of instructions that are encoded differently depending on cpu, such as mftb which has pre- and post-power4 encodings. PR 28959 * ppc-dis.c (lookup_powerpc): Revert 2021-05-28 change. Instead only look at deprecated PPC_OPCODE_RAW bit when -Many.
2022-03-06MIPS/opcodes: Fix alias annotation for branch instructionsMaciej W. Rozycki3-7/+16
Correct issues with INSN2_ALIAS annotation for branch instructions: - regular MIPS BEQZ/L and BNEZ/L assembly instructions are idioms for BEQ/L and BNE/L respectively with the `rs' operand equal to $0, - microMIPS 32-bit BEQZ and BNEZ assembly instructions are idioms for BEQ and BNE respectively with the `rt' operand equal to $0, - regular MIPS BAL assembly instruction is an idiom for architecture levels of up to the MIPSr5 ISA and a machine instruction on its own from the MIPSr6 ISA up. Add missing annotation to BEQZ/L and BNEZ/L accordingly then and add a new entry for BAL for the MIPSr6 ISA, correcting a disassembly bug: $ mips-linux-gnu-objdump -m mips:isa64r6 -M no-aliases -d bal.o bal.o: file format elf32-tradlittlemips Disassembly of section .text: 00000000 <foo>: 0: 04110000 0x4110000 ... $ Add test cases accordingly. Parts for regular MIPS BEQZ/L and BNEZ/L instructions from Sagar Patel. 2022-03-06 Maciej W. Rozycki <macro@orcam.me.uk> binutils/ * testsuite/binutils-all/mips/mips1-branch-alias.d: New test. * testsuite/binutils-all/mips/mips1-branch-noalias.d: New test. * testsuite/binutils-all/mips/mips2-branch-alias.d: New test. * testsuite/binutils-all/mips/mips2-branch-noalias.d: New test. * testsuite/binutils-all/mips/mips32r6-branch-alias.d: New test. * testsuite/binutils-all/mips/mips32r6-branch-noalias.d: New test. * testsuite/binutils-all/mips/micromips-branch-alias.d: New test. * testsuite/binutils-all/mips/micromips-branch-noalias.d: New test. * testsuite/binutils-all/mips/mips-branch-alias.s: New test source. * testsuite/binutils-all/mips/micromips-branch-alias.s: New test source. * testsuite/binutils-all/mips/mips.exp: Run the new tests. 2022-03-06 Sagar Patel <sagarmp@cs.unc.edu> Maciej W. Rozycki <macro@orcam.me.uk> opcodes/ * mips-opc.c (mips_builtin_opcodes): Fix INSN2_ALIAS annotation for "bal", "beqz", "beqzl", "bnez" and "bnezl" instructions. * micromips-opc.c (micromips_opcodes): Likewise for "beqz" and "bnez" instructions.
2022-02-25RISC-V: Fix mask for some fcvt instructionsTsukasa OI1-4/+4
This commit fixes incorrect uses of mask values in 'fcvt' instruction family. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Fix incorrect uses of mask values in 'fcvt' instruction family.
2022-02-17Updated Serbian translations for the bfd, gold, ld and opcodes directoriesNick Clifton2-235/+275
2022-02-15x86: Add has_sib to struct instr_infoH.J. Lu1-8/+9
Add has_sib to struct instr_info and use SIB info only if ins->has_sib is true. PR binutils/28892 * i386-dis.c (instr_info): Add has_sib. (get_sib): Set has_sib. (OP_E_memory): Replace havesib with ins->has_sib. (OP_VEX): Use ins->sib.index only if ins->has_sib is true.
2022-02-14microblaze: fix fsqrt collicion to build on glibc-2.35Sergei Trofimovich3-2/+8
* microblaze-opcm.h: Renamed 'fsqrt' to 'microblaze_fsqrt'. * microblaze-opc.h: Follow 'fsqrt' rename.
2022-01-24Update Bulgarian, French, Romaniam and Ukranian translation for some of the ↵Nick Clifton4-923/+2834
sub-directories
2022-01-23Regenerate Makefile.in files with automake 1.15.1H.J. Lu1-1/+0
Regenerate Makefile.in files with the unmodified automake 1.15.1 to remove runstatedir = @runstatedir@ bfd/ * Makefile.in: Regenerate. binutils/ * Makefile.in: Regenerate. gas/ * Makefile.in: Regenerate. gold/ * Makefile.in: Regenerate. * testsuite/Makefile.in: Likewise. gprof/ * Makefile.in: Regenerate. ld/ * Makefile.in: Regenerate. opcodes/ * Makefile.in: Regenerate.
2022-01-23Regenerate configure files with autoconf 2.69H.J. Lu1-15/+3
Regenerate configure files with the unmodified autoconf 2.69 to remove --runstatedir=DIR modifiable per-process data [LOCALSTATEDIR/run] bfd/ * configure: Regenerate. binutils/ * configure: Regenerate. gas/ * configure: Regenerate. gold/ * configure: Regenerate. gprof/ * configure: Regenerate. ld/ * configure: Regenerate. opcodes/ * configure: Regenerate.
2022-01-22Change version number to 2.38.50 and regenerate filesNick Clifton3-14/+31
2022-01-22Add markers for 2.38 branchNick Clifton1-0/+4
2022-01-21drop old unused stamp-h.in fileMike Frysinger1-1/+0
This was needed by ancient versions of automake, but that hasn't been the case since at least automake-1.5, so punt this from the tree.
2022-01-17Update the config.guess and config.sub files from the master repository and ↵Nick Clifton3-208/+244
regenerate files.
2022-01-17x86: adjust struct instr_info field typesJan Beulich1-36/+39
Now that this lives on the stack, let's have it be a little less wasteful in terms of space. Switch boolean fields to "bool" (also when this doesn't change their size) and also limit the widths of "rex", "rex_used", "op_ad", and "op_index". Do a little bit of re-ordering as well to limit the number of padding holes.
2022-01-17x86: drop index16 fieldJan Beulich1-5/+3
There's a single use on a generally infrequently taken code path. Put the necessary conditional there instead.
2022-01-17x86: drop most Intel syntax register name arraysJan Beulich1-230/+119
By making use of, in particular, oappend_maybe_intel() there's no need for this redundant set of static data.
2022-01-17x86: fold variables in memory operand index handlingJan Beulich1-19/+15
There's no real need for the pseudo-boolean "haveindex" or for separate 32-bit / 64-bit index pointers. Fold them into a single "indexes" and set that uniformly to AT&T names, compensating by emitting the register name via oappend_maybe_intel().
2022-01-17x86: constify disassembler static dataJan Beulich1-58/+58
Now that the code is intended to be largely thread-safe, we'd better not have any writable static objects.
2022-01-14x86: drop ymmxmm_modeJan Beulich1-16/+0
This enumerator is not used by any table entry.
2022-01-14x86: share yet more VEX table entries with EVEX decodingJan Beulich4-209/+69
On top of prior similar work more opportunities have appeared in the meantime. Note that this also happens to address the prior lack of decoding of EVEX.L'L for VMOV{L,H}P{S,D} and VMOV{LH,HL}PS.
2022-01-14x86: consistently use scalar_mode for AVX512-FP16 scalar insnsJan Beulich2-31/+31
For some reason the original AVFX512F insns were not taken as a basis here, causing unnecessary divergence. While not an active issue, it is still relevant to note that OP_XMM() has special treatment of e.g. scalar_mode (marking broadcast as invalid). Such would better be consistent for all sufficiently similar insns.
2022-01-14x86: record further wrong uses of EVEX.bJan Beulich1-0/+8
For one EVEX.W set does not imply EVEX.b is uniformly valid. Reject it for modes which occur for insns allowing for EVEX.W to be set (noticed with VMOV{H,L}PD and VMOVDDUP, and only in AT&T mode, but not checked whether further insns would also have been impacted; I expect e.g. VCMPSD would have had the same issue). And then the present concept of broadcast makes no sense at all when the memory operand of an insn is the destination.
2022-01-14x86: reduce AVX512 FP set of insns decoded through vex_w_table[]Jan Beulich5-268/+42
Like for AVX512-FP16, there's not that many FP insns where going through this table is easier / cheaper than using suitable macros. Utilize %XS and %XD more to eliminate a fair number of table entries. While doing this I noticed a few anomalies. Where lines get touched / moved anyway, these are being addressed right here: - vmovshdup used EXx for its 2nd operand, thus displaying seemingly valid broadcast when EVEX.b is set with a memory operand; use EXEvexXNoBcst instead just like vmovsldup already does - vmovlhps used EXx for its 3rd operand, when all sibling entries use EXq; switch to EXq there for consistency (the two differ only for memory operands)
2022-01-14x86: reduce AVX512-FP16 set of insns decoded through vex_w_table[]Jan Beulich4-137/+77
Like already indicated during review of the original submission, there's really only very few insns where going through this table is easier / cheaper than using suitable macros. Utilize %XH more and introduce similar %XS and %XD (which subsequently can be used for further table size reduction). While there also switch to using oappend() in 'XH' macro processing.
2022-01-06aarch64: Add support for new SME instructionsRichard Sandiford2-302/+338
This patch adds support for three new SME instructions: ADDSPL, ADDSVL and RDSVL. They behave like ADDPL, ADDVL and RDVL, but read the streaming vector length instead of the current vector length. opcodes/ * aarch64-tbl.h (aarch64_opcode_table): Add ADDSPL, ADDSVL and RDSVL. * aarch64-dis-2.c: Regenerate. gas/ * testsuite/gas/aarch64/sme.s, testsuite/gas/aarch64/sme.d: Add tests for ADDSPL, ADDSVL and RDSVL.
2022-01-06x86: drop NoAVX insn attributeJan Beulich4-4520/+4516
To avoid issues like that addressed by 6e3e5c9e4181 ("x86: extend SSE check to PCLMULQDQ, AES, and GFNI insns"), base the check on opcode attributes and operand types.
2022-01-06x86: drop NoAVX from POPCNTJan Beulich2-2/+2
With the introduction of CpuPOPCNT the NoAVX attribute has become meaningless for POPCNT.
2022-01-06x86: drop some "comm" template parametersJan Beulich2-90/+90
As already indicated in a remark when introducing these templates, the "commutative" attribute is ignored for legacy encoding templates. Hence it is possible to shorten a number of templates by specifying C directly rather than through a template parameter. I think this helps readability a bit.
2022-01-06x86: templatize FMA insn templatesJan Beulich2-1016/+830
The operand ordering portion of the mnemonics repeats, causing a flurry of almost identical templates. Abstract this out.
2022-01-05opcodes: Make i386-dis.c thread-safeVladimir Mezentsev1-1738/+1774
Improve thread safety in print_insn_i386_att, print_insn_i386_intel and print_insn_i386 by removing the use of static variables. Tested on x86_64-pc-linux-gnu. 2022-01-04 Vladimir Mezentsev <vladimir.mezentsev@oracle.com> * i386-dis.c: Make print_insn_i386_att, print_insn_i386_intel and print_insn_i386 thread-safe
2022-01-02Update year range in copyright notice of binutils filesAlan Modra282-286/+301
The result of running etc/update-copyright.py --this-year, fixing all the files whose mode is changed by the script, plus a build with --enable-maintainer-mode --enable-cgen-maint=yes, then checking out */po/*.pot which we don't update frequently. The copy of cgen was with commit d1dd5fcc38ead reverted as that commit breaks building of bfp opcodes files.
2022-01-01unify 64-bit bfd checksMike Frysinger5-4/+265
Move the 64-bit bfd logic out of bfd/configure.ac and into bfd64.m4 under config so it can be shared between all the other subdirs. This replaces want64 with enable_64_bit_bfd which was already being declared, but not used directly.
2021-12-24RISC-V: Hypervisor ext: support Privileged Spec 1.12Vineet Gupta1-0/+21
This is the Hypervisor Extension 1.0 - Hypervisor Memory-Management Instructions HFENCE.VVMA, HFENCE.GVMA, - Hypervisor Virtual Machine Load and Store Instructions HLV.B, HLV.BU, HSV.B, HLV.H, HLV.HU, HLVX.HU, HSB.H, HLV.W, HLV.WU, HLVX.WU, HSV.W, HLV.D, HSV.D - Hypervisor CSRs (some new, some address changed) hstatus, hedeleg, hideleg, hie, hcounteren, hgeie, htval, hip, hvip, htinst, hgeip, henvcfg, henvcfgh, hgatp, hcontext, htimedelta, htimedeltah, vsstatus, vsie, vstvec, vsscratch, vsepc, vscause, vstval, vsip, vsatp, Note that following were added already as part of svinval extension support: HINVAL.GVMA, HINVAL.VVMA Signed-off-by: Vineet Gupta <vineetg@rivosinc.com> Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com> Reviewed-by: Nelson Chu <nelson.chu@sifive.com> bfd/ * cpu-riscv.c (riscv_priv_specs): Added entry for 1.12. * cpu-riscv.h (enum riscv_spec_class): Added PRIV_SPEC_CLASS_1P12. gas/ * config/tc-riscv.c (abort_version): Updated comment. (validate_riscv_insn): Annotate switch-break. * testsuite/gas/riscv/h-ext-32.d: New testcase for hypervisor. * testsuite/gas/riscv/h-ext-32.s: Likewise. * testsuite/gas/riscv/h-ext-64.d: Likewise. * testsuite/gas/riscv/h-ext-64.s: Likewise. include/ * opcode/riscv-opc.h: Added encodings for hypervisor csrs and instrcutions. opcodes/ * riscv-opc.c (riscv_opcodes): Added hypervisor instrcutions.
2021-12-17x86: Terminate mnemonicendp in swap_operand()Vladimir Mezentsev1-0/+1
Tested on x86_64-pc-linux-gnu. opcodes/ChangeLog: 2021-12-17 Vladimir Mezentsev <vladimir.mezentsev@oracle.com> * i386-dis.c (swap_operand): Terminate mnemonicendp. gas/ChangeLog: 2021-12-17 Vladimir Mezentsev <vladimir.mezentsev@oracle.com> * testsuite/gas/i386/opts-intel.d: Updated expected disassembly. * testsuite/gas/i386/opts.d: Likewise. * testsuite/gas/i386/sse2avx-opts-intel.d: Likewise. * testsuite/gas/i386/sse2avx-opts.d: Likewise. * testsuite/gas/i386/x86-64-opts-intel.d: Likewise. * testsuite/gas/i386/x86-64-opts.d: Likewise. * testsuite/gas/i386/x86-64-sse2avx-opts-intel.d: Likewise. * testsuite/gas/i386/x86-64-sse2avx-opts.d: Likewise.
2021-12-16RISC-V: Support svinval extension with frozen version 1.0.Nelson Chu1-0/+7
According to the privileged spec, there are five new instructions for svinval extension. Two of them (HINVAL.VVMA and HINVAL.GVMA) need to enable the hypervisor extension. But there is no implementation of hypervisor extension in mainline for now, so let's consider the related issues later. 31..25 24..20 19..15 14..12 11...7 6..2 1..0 sinval.vma 0001011 rs2 rs1 000 00000 11100 11 sfence.w.inval 0001100 00000 00000 000 00000 11100 11 sfence.inval.ir 0001100 00001 00000 000 00000 11100 11 hinval.vvma 0010011 rs2 rs1 000 00000 11100 11 hinval.gvma 0110011 rs2 rs1 000 00000 11100 11 This patch is cherry-picked from the riscv integration branch since the svinval extension is frozen for now. Besides, we fix the funct7 encodings of hinval.vvma and hinval.gvma, from 0x0011011 and 0x0111011 to 0x0010011 and 0x0110011. bfd/ * elfxx-riscv.c (riscv_supported_std_s_ext): Added svinval. (riscv_multi_subset_supports): Handle INSN_CLASS_SVINVAL. gas/ * testsuite/gas/riscv/svinval.d: New testcase. * testsuite/gas/riscv/svinval.s: Likewise. include/ * opcode/riscv-opc.h: Added encodings for svinval. * opcode/riscv.h (enum riscv_insn_class): Added INSN_CLASS_SVINVAL. opcodes/ * riscv-opc.c (riscv_opcodes): Added svinval instructions.
2021-12-03aarch64: Fix uninitialised memoryRichard Sandiford2-1/+3
AARCH64_OPDE_EXPECTED_A_AFTER_B and AARCH64_OPDE_A_SHOULD_FOLLOW_B are not paired with an error string, but we had an assert that the error was nonnull. Previously this assert was testing uninitialised memory and so could pass or fail arbitrarily. opcodes/ * aarch64-opc.c (verify_mops_pme_sequence): Initialize the error field to null for AARCH64_OPDE_EXPECTED_A_AFTER_B and AARCH64_OPDE_A_SHOULD_FOLLOW_B. * aarch64-dis.c (print_verifier_notes): Move assert.
2021-12-03Revert "Re: Don't compile some opcodes files when bfd is 32-bit only"Alan Modra2-10/+10
This reverts commit 7a53275579e7cec9389ccb924f5ecf69e8d89d41. The bpf sim doesn't work with a 32-bit bfd after all.
2021-12-02aarch64: Add BC instructionRichard Sandiford2-47/+65
This patch adds support for the Armv8.8-A BC instruction. [https://developer.arm.com/documentation/ddi0596/2021-09/Base-Instructions/BC-cond--Branch-Consistent-conditionally-?lang=en] include/ * opcode/aarch64.h (AARCH64_FEATURE_HBC): New macro. (AARCH64_ARCH_V8_8): Make armv8.8-a imply AARCH64_FEATURE_HBC. opcodes/ * aarch64-tbl.h (aarch64_feature_hbc): New variable. (HBC, HBC_INSN): New macros. (aarch64_opcode_table): Add BC.C. * aarch64-dis-2.c: Regenerate. gas/ * doc/c-aarch64.texi: Document +hbc. * config/tc-aarch64.c (aarch64_features): Add "hbc". * testsuite/gas/aarch64/hbc.s, testsuite/gas/aarch64/hbc.d: New test. * testsuite/gas/aarch64/hbc-invalid.s, testsuite/gas/aarch64/hbc-invalid.l, testsuite/gas/aarch64/hbc-invalid.d: New test.
2021-12-02aarch64: Enforce P/M/E order for MOPS instructionsRichard Sandiford3-15/+127
The MOPS instructions should be used as a triple, such as: cpyfp [x0]!, [x1]!, x2! cpyfm [x0]!, [x1]!, x2! cpyfe [x0]!, [x1]!, x2! The registers should also be the same for each writeback operand. This patch adds a warning for code that doesn't follow this rule, along similar lines to the warning that we already emit for invalid uses of MOVPRFX. include/ * opcode/aarch64.h (C_SCAN_MOPS_P, C_SCAN_MOPS_M, C_SCAN_MOPS_E) (C_SCAN_MOPS_PME): New macros. (AARCH64_OPDE_A_SHOULD_FOLLOW_B): New aarch64_operand_error_kind. (AARCH64_OPDE_EXPECTED_A_AFTER_B): Likewise. (aarch64_operand_error): Make each data value a union between an int and a string. opcodes/ * aarch64-tbl.h (MOPS_CPY_OP1_OP2_INSN): Add scan flags. (MOPS_SET_OP1_OP2_INSN): Likewise. * aarch64-opc.c (set_out_of_range_error): Update after change to aarch64_operand_error. (set_unaligned_error, set_reg_list_error): Likewise. (init_insn_sequence): Use a 3-instruction sequence for MOPS P instructions. (verify_mops_pme_sequence): New function. (verify_constraints): Call it. * aarch64-dis.c (print_verifier_notes): Handle AARCH64_OPDE_A_SHOULD_FOLLOW_B and AARCH64_OPDE_EXPECTED_A_AFTER_B. gas/ * config/tc-aarch64.c (operand_mismatch_kind_names): Add entries for AARCH64_OPDE_A_SHOULD_FOLLOW_B and AARCH64_OPDE_EXPECTED_A_AFTER_B. (operand_error_higher_severity_p): Check that AARCH64_OPDE_A_SHOULD_FOLLOW_B and AARCH64_OPDE_EXPECTED_A_AFTER_B come between AARCH64_OPDE_RECOVERABLE and AARCH64_OPDE_SYNTAX_ERROR; their relative order is not significant. (record_operand_error_with_data): Update after change to aarch64_operand_error. (output_operand_error_record): Likewise. Handle AARCH64_OPDE_A_SHOULD_FOLLOW_B and AARCH64_OPDE_EXPECTED_A_AFTER_B. * testsuite/gas/aarch64/mops_invalid_2.s, testsuite/gas/aarch64/mops_invalid_2.d, testsuite/gas/aarch64/mops_invalid_2.l: New test.
2021-12-02aarch64: Add support for +mopsRichard Sandiford9-32/+1535
This patch adds support for FEAT_MOPS, an Armv8.8-A extension that provides memcpy and memset acceleration instructions. I took the perhaps controversial decision to generate the individual instruction forms using macros rather than list them out individually. This becomes useful with a follow-on patch to check that code follows the correct P/M/E sequence. [https://developer.arm.com/documentation/ddi0596/2021-09/Base-Instructions?lang=en] include/ * opcode/aarch64.h (AARCH64_FEATURE_MOPS): New macro. (AARCH64_ARCH_V8_8): Make armv8.8-a imply AARCH64_FEATURE_MOPS. (AARCH64_OPND_MOPS_ADDR_Rd): New aarch64_opnd. (AARCH64_OPND_MOPS_ADDR_Rs): Likewise. (AARCH64_OPND_MOPS_WB_Rn): Likewise. opcodes/ * aarch64-asm.h (ins_x0_to_x30): New inserter. * aarch64-asm.c (aarch64_ins_x0_to_x30): New function. * aarch64-dis.h (ext_x0_to_x30): New extractor. * aarch64-dis.c (aarch64_ext_x0_to_x30): New function. * aarch64-tbl.h (aarch64_feature_mops): New feature set. (aarch64_feature_mops_memtag): Likewise. (MOPS, MOPS_MEMTAG, MOPS_INSN, MOPS_MEMTAG_INSN) (MOPS_CPY_OP1_OP2_PME_INSN, MOPS_CPY_OP1_OP2_INSN, MOPS_CPY_OP1_INSN) (MOPS_CPY_INSN, MOPS_SET_OP1_OP2_PME_INSN, MOPS_SET_OP1_OP2_INSN) (MOPS_SET_INSN): New macros. (aarch64_opcode_table): Add MOPS instructions. (aarch64_opcode_table): Add entries for AARCH64_OPND_MOPS_ADDR_Rd, AARCH64_OPND_MOPS_ADDR_Rs and AARCH64_OPND_MOPS_WB_Rn. * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_MOPS_ADDR_Rd, AARCH64_OPND_MOPS_ADDR_Rs and AARCH64_OPND_MOPS_WB_Rn. (verify_three_different_regs): New function. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise. gas/ * doc/c-aarch64.texi: Document +mops. * config/tc-aarch64.c (parse_x0_to_x30): New function. (parse_operands): Handle AARCH64_OPND_MOPS_ADDR_Rd, AARCH64_OPND_MOPS_ADDR_Rs and AARCH64_OPND_MOPS_WB_Rn. (aarch64_features): Add "mops". * testsuite/gas/aarch64/mops.s, testsuite/gas/aarch64/mops.d: New test. * testsuite/gas/aarch64/mops_invalid.s, * testsuite/gas/aarch64/mops_invalid.d, * testsuite/gas/aarch64/mops_invalid.l: Likewise.
2021-12-02aarch64: Add Armv8.8-A system registersRichard Sandiford1-0/+5
Armv8.8-A defines two new system registers: allint and icc_nmiar1_el1. Both of them were previously unmapped. allint supports a 0/1 immediate. [https://developer.arm.com/documentation/ddi0595/2021-09/AArch64-Registers/ALLINT--All-Interrupt-Mask-Bit?lang=en] [https://developer.arm.com/documentation/ddi0595/2021-09/AArch64-Registers/ICC-NMIAR1-EL1--Interrupt-Controller-Non-maskable-Interrupt-Acknowledge-Register-1?lang=en] opcodes/ * aarch64-opc.c (SR_V8_8): New macro. (aarch64_sys_regs): Add allint and icc_nmiar1_el1. (aarch64_pstatefields): Add allint. gas/ * testsuite/gas/aarch64/armv8_8-a-sysregs.s, * testsuite/gas/aarch64/armv8_8-a-sysregs.d: New test. * testsuite/gas/aarch64/armv8_8-a-sysregs-invalid.s, * testsuite/gas/aarch64/armv8_8-a-sysregs-invalid.l, * testsuite/gas/aarch64/armv8_8-a-sysregs-invalid.d: New test.
2021-12-02aarch64: Add id_aa64isar2_el1Richard Sandiford1-0/+1
Armv8.8-A defines a read-only system register called id_aa64isar2_el1. The register was previously RES0 and should therefore be accepted at all architecture levels. [https://developer.arm.com/documentation/ddi0595/2021-09/AArch64-Registers/ID-AA64ISAR2-EL1--AArch64-Instruction-Set-Attribute-Register-2?lang=en] opcodes/ * aarch64-opc.c (aarch64_sys_regs): Add id_aa64isar2_el1. gas/ * testsuite/gas/aarch64/sysreg-diagnostic.s: Test writes to id_aa64isar2_el1. * testsuite/gas/aarch64/sysreg-diagnostic.d: Update accordingly. * testsuite/gas/aarch64/sysreg-diagnostic.l: Likewise. * testsuite/gas/aarch64/sysreg.s: Test reads from id_aa64isar2_el1. * testsuite/gas/aarch64/sysreg.d: Update accordingly.
2021-12-02aarch64: Tweak insn sequence codeRichard Sandiford1-26/+22
libopcodes has some code to check constraints across sequences of consecutive instructions. It was added to support MOVPRFX sequences but is going to be useful for the Armv8.8-A MOPS feature as well. Currently the structure has one field to record the instruction that started a sequence and another to record the remaining instructions in the sequence. It's more convenient for the MOPS code if we put the instructions into a single array instead. No functional change intended. include/ * opcode/aarch64.h (aarch64_instr_sequence): Replace num_insns and current_insns with num_added_insns and num_allocated_insns. opcodes/ * aarch64-opc.c (add_insn_to_sequence): New function. (init_insn_sequence): Update for new aarch64_instr_sequence layout. Add the first instruction to the inst array. (verify_constraints): Update for new aarch64_instr_sequence layout. Don't add the last instruction to the array.
2021-12-02aarch64: Add maximum immediate value to aarch64_sys_regRichard Sandiford2-35/+26
The immediate form of MSR has a 4-bit immediate field (in CRm). However, many forms of MSR require a smaller immediate. These cases are identified by value in operand_general_constraint_met_p, but they're now the common case rather than the exception. This patch therefore adds the maximum value to the sys_reg description and gets the range from there. It also enforces the minimum of 0, which avoids a situation in which: msr dit, #2 would give the expected: Error: immediate value out of range 0 to 1 whereas: msr dit, #-1 would give: Error: immediate value out of range 0 to 15 (from the later UIMM4 checking). Also: - we were reporting the first error above against the wrong operand - TCO takes a single-bit immediate, but we previously allowed all 16 values. [https://developer.arm.com/documentation/ddi0596/2021-09/Base-Instructions/MSR--immediate---Move-immediate-value-to-Special-Register-?lang=en] opcodes/ * aarch64-opc.h (F_REG_MAX_VALUE, F_GET_REG_MAX_VALUE): New macros. * aarch64-opc.c (operand_general_constraint_met_p): Read the maximum MSR immediate value from aarch64_pstatefields. (aarch64_pstatefields): Add the maximum immediate value for each register. gas/ * testsuite/gas/aarch64/sysreg-4.s: Use an immediate value of 1 rather than 8 for the TCO test. * testsuite/gas/aarch64/sysreg-4.d: Update accordingly. * testsuite/gas/aarch64/armv8_2-a-illegal.l: Fix operand number in MSR immediate error messages. * testsuite/gas/aarch64/diagnostic.l: Likewise. * testsuite/gas/aarch64/pan-illegal.l: Likewise. * testsuite/gas/aarch64/ssbs-illegal1.l: Likewise. * testsuite/gas/aarch64/illegal-sysreg-4b.s, * testsuite/gas/aarch64/illegal-sysreg-4b.d, * testsuite/gas/aarch64/illegal-sysreg-4b.l: New test.
2021-12-02Allow the --visualize-jumps feature to work with the AVR disassembler.Marcus Nilsson2-5/+37
* avr-dis.c (avr_operand); Pass in disassemble_info and fill in insn_type on branching instructions.
generated by cgit v1.1 at 2024-07-19 13:49:37 +0000