aboutsummaryrefslogtreecommitdiff
path: root/opcodes
AgeCommit message (Expand)AuthorFilesLines
2024-01-08aarch64: Add ite feature system registers.srinath1-0/+4
2024-01-07i386: Correct adcx suffix in disassemblerH.J. Lu1-4/+13
2024-01-05Add AMD znver5 processor supportTejas Joshi2-0/+12
2024-01-05x86: corrections to CPU attribute/flags splittingJan Beulich1-1/+10
2024-01-05RISC-V: T-HEAD: Fix wrong instruction encoding for th.vsetvliJin Ma2-1/+35
2024-01-04Update year range in copyright notice of binutils filesAlan Modra275-336/+340
2024-01-04LoongArch: Fix some macro that cannot be expanded properlyLulu Cai1-12/+12
2023-12-30LoongArch: Commas inside double quotesAlan Modra1-1/+5
2023-12-29LoongArch: opcodes: Add support for tls le relax.changjiachen1-0/+1
2023-12-29RISC-V: THEAD: Add 5 assembly pseudoinstructions for XTheadVector extensionJin Ma1-0/+5
2023-12-28Support APX JMPABS for disassemblerHu, Lin11-2/+35
2023-12-28Support APX pushp/poppCui, Lili5-1061/+1101
2023-12-28Support APX Push2/Pop2Mo, Zewei7-1960/+2064
2023-12-28Support APX NDDkonglin16-413/+1650
2023-12-28Support APX GPR32 with extend evex prefixCui, Lili8-4182/+4772
2023-12-28Created an empty EVEX_MAP4_ sub-table for EVEX instructions.Cui, Lili2-0/+292
2023-12-28Support APX GPR32 with rex2 prefixCui, Lili8-11743/+12227
2023-12-25LoongArch: Add new relocs and macro for TLSDESC.Lulu Cai1-0/+54
2023-12-25Re: LoongArch: Add support for <b ".L1"> and <beq, $t0, $t1, ".L1">Alan Modra1-14/+16
2023-12-20s390: Add suffix to conditional branch instruction descriptionsJens Remus1-34/+44
2023-12-20s390: Optionally print instruction description in disassemblyJens Remus3-39/+55
2023-12-20s390: Use safe string functions and length macros in s390-mkopcJens Remus1-25/+52
2023-12-20s390: Enhance error handling in s390-mkopcJens Remus1-14/+35
2023-12-20s390: Provide IBM z16 (arch14) instruction descriptionsJens Remus1-28/+38
2023-12-20s390: Align letter case of instruction descriptionsJens Remus1-21/+21
2023-12-20s390: Fix build when using EXEEXT_FOR_BUILDJens Remus2-4/+10
2023-12-19aarch64: Add FEAT_ITE supportAndrea Corallo3-2/+12
2023-12-19aarch64: Add FEAT_ECBHB supportAndrea Corallo3-1/+7
2023-12-19aarch64: Add FEAT_SPECRES2 supportAndrea Corallo4-2074/+2083
2023-12-19x86: Remove the restriction for size of the mask register in AVX10Haochen Jiang4-3777/+3762
2023-12-18LoongArch: Add call36 and tail36 pseudo instructions for medium code modelmengqinggang1-0/+11
2023-12-15revert "x86: allow 32-bit reg to be used with U{RD,WR}MSR"Jan Beulich2-4/+4
2023-12-15x86: fold assembly dialect attributesJan Beulich4-7498/+3755
2023-12-15x86: Intel syntax implies Intel mnemonicsJan Beulich3-333/+298
2023-12-14RISC-V: Fix the wrong encoding and operand of the XTheadFmv extension.Jin Ma1-1/+1
2023-12-14Remove redundant Byte, Word, Dword and Qword from insn templates.Cui, Lili1-123/+123
2023-12-13Make const_1_mode print $1 in AT&T syntaxCui, Lili1-0/+2
2023-12-11LoongArch: Add support for <b ".L1"> and <beq, $t0, $t1, ".L1">mengqinggang1-0/+7
2023-12-04s390: Support for jump visualization in disassemblyJens Remus3-42/+88
2023-12-01x86: allow 32-bit reg to be used with U{RD,WR}MSRJan Beulich2-4/+4
2023-12-01RISC-V: Make riscv_is_mapping_symbol stricterPatrick O'Neill1-3/+1
2023-12-01RISC-V: Add SiFive custom vector coprocessor interface instructions v1.0Nelson Chu2-0/+57
2023-12-01RISC-V: Zv*: Add support for Zvkb ISA extensionChristoph Müllner1-10/+10
2023-11-30RISC-V: Avoid updating state until symbol is foundPatrick O'Neill1-12/+31
2023-11-27as: Add new estimated reciprocal instructions in LoongArch v1.1Jiajie Chen1-0/+12
2023-11-27as: Add new atomic instructions in LoongArch v1.1Jiajie Chen1-0/+42
2023-11-24RISC-V: drop leftover match_never() referencesJan Beulich1-4/+4
2023-11-24x86: shrink opcode sets tableJan Beulich2-2347/+302
2023-11-24x86: also prefer VEX encoding over EVEX one for VCVTNEPS2BF16 when possibleJan Beulich1-0/+6
2023-11-24RISC-V: reduce redundancy in sign/zero extension macro insn handlingJan Beulich1-2/+2