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BFD_FAKE_SECTION and its sidekick GLOBAL_SYM_INIT don't need to be
cluttering bfd.h, and probably shouldn't be used outside bfd/. To
make them internal to bfd, make the bfd ecoff small common section
declaration global so it can be used instead of a duplicate in
gas/ecoff.c. Oddly this needs to go in bfd/ecofflink.c rather than
bfd/ecoff.c as the former is compiled for all targets needing the
ecoff small common section (some via a call in gas/config/obj-elf.c to
a function in gas/ecoff.c) while the latter is not.
While doing this rename ecoff_scom_section to _bfd_ecoff_scom_section
and remove support for traditional C from GLOBAL_SYM_INIT.
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It only add one new CSR: `srmcfg`.
Ref: https://github.com/riscv/riscv-ssqosid/releases/tag/v1.0
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The mapping symbol "$x" without an ISA string "means using ISA
configuration from ELF attribute."[1]. Currently the code does not
reset the subset_list. This means that a previous mapping symbol that
overrides the ISA string will continue to be used, rather than the
default string set in the ELF file's .riscv.attributes section. This
can cause incorrect or failed instruction decodings.
In practice, this causes problems when disassembling code generated by
LLVM, which (unlike gas) does not emit explicit mapping symbols at the
start of each section.
This change stores the default architecture string seen at the beginning
of disassembly in the global parse data struct, and restores that to
subset_list whenever a bare "$x" symbol is seen.
[1] https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc#mapping-symbol
Before this patch, the mapping-x.s was dumped as,
00000000 <.text>:
0: 00000013 nop
4: 0001 .insn 2, 0x0001
6: 0001 .insn 2, 0x0001
Which is caused by the definiation of $x was conflict with the psABI.
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The psABI defined $x to the architecture which is same as the file elf
attribute. But GNU defined it to that is same as the previous $x<isa>,
and always generated $x<isa> at the begining of each section. That is
because considering two objects have different architecture in their elf
attributes, then $x will always be wrong after linking since the merged
arch string will be changed. For example, object A with rv32ic and object
B with rv32ia, $x from A is rv32ic and $x from B is rv32ia, but the final
output is rv32ica, so $x from A and B need to be updated to rv32ic and
rv32ia by linker respectively. I think let linker to do this is not good,
so in order to follow the psABI, we will stop generating the $x for now.
Instead, all $x will be replaced with the corresponding $x<isa>. The
dis-assembler will also treat $x like what psABI defined.
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CFI_escape is most commonly used to include DWARF expressions in the
unwind information. One may also use CFI_escape to add OS-specific CFI
opcodes. Up until now, SFrame generation process would skip generating
SFrame FDE at the mere sight of a CFI_escape opcode.
Fine tune the handling of CFI_escape for SFrame generation by explicitly
checking for few "harmless" (in context of SFrame generation)
CFI_escape DWARF info:
- DW_CFA_expression affecting registers of no significance to SFrame
stack trace info
- DW_CFA_value_offset affecting registers of no significance to SFrame
stack trace info
Expose the current cfi_escape_data structure in dw2gencfi.c to the
relevant header file to allow SFrame generation APIs to use it too.
Valid unwind info may be split across multiple .cfi_escape directives.
Conversely, it is also allowed to simply put multiple DWARF expressions
and/or operations in a single .cfi_escape directive. Handling all of
these cases correctly will need parsing/processing that is not deemed
worth the effort in context of SFrame generation; We continue to skip
generating SFrame FDE for these cases and warn the user.
In future, SFrame stack trace format may support non-SP/FP as base
register (albeit in limited form). Add an explicit check in
sframe_xlate_do_escape_expr (to test against the current CFA register)
to ensure the functionality continues to work.
Use differentiated warning text in sframe_xlate_do_val_offset to avoid
confusion to the user as the same function is used for handling
.cfi_val_offset and .cfi_escape DW_CFA_val_offset,...
Also, add a common test with DWARF reg 12 which is non SP / FP on x86_64
and aarch64 (and s390x too).
gas/
* gas/dw2gencfi.c (struct cfi_escape_data): Move from ...
* gas/dw2gencfi.h (struct cfi_escape_data): ... to.
* gas/gen-sframe.c (sframe_xlate_do_val_offset): Include string
for .cfi_escape conditionally.
(sframe_xlate_do_escape_expr): New definition.
(sframe_xlate_do_escape_val_offset): Likewise.
(sframe_xlate_do_cfi_escape): Likewise.
(sframe_do_cfi_insn): Handle CFI_escape explicitly.
gas/testsuite/
* gas/cfi-sframe/cfi-sframe.exp: Add new tests.
* gas/cfi-sframe/cfi-sframe-common-9.d: New test.
* gas/cfi-sframe/cfi-sframe-common-9.s: New test.
* gas/cfi-sframe/cfi-sframe-x86_64-empty-1.d: New test.
* gas/cfi-sframe/cfi-sframe-x86_64-empty-1.s: New test.
* gas/cfi-sframe/cfi-sframe-x86_64-empty-2.d: New test.
* gas/cfi-sframe/cfi-sframe-x86_64-empty-2.s: New test.
* gas/cfi-sframe/cfi-sframe-x86_64-empty-3.d: New test.
* gas/cfi-sframe/cfi-sframe-x86_64-empty-3.s: New test.
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If data is encountered that is not a power of two, dump all of the data with
a .<N>byte directive. The current largest support risc-v instruction length
is 22, so the data over 22 bytes will be displayed by,
.insn, 22, ... + .<N-22>byte.
Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
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The oss-fuzz gas fuzzer is quite broken in that it doesn't
reinitialise all gas and bfd static variables between runs. Since gas
naughtily modifies bfd_und_section and bfd_abs_section those bfd
statics can hold pointers into freed memory between runs.
This patch fixes oss-fuzz issue 398060144.
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Add gpr and fpr names for the o64 ABI to objdump.
With the recent addition of both EABIs, this completes support for the
standard ABI options (ABI-breaking options such as -modd-spreg or
-mabi=32 -mfp64 notwithstanding). The names have been verified against
GCC's usage of the registers. Notably, the only(?) documentation that
defines the o64 ABI at
https://gcc.gnu.org/projects/mipso64-abi.html
appears to contain a mistake w.r.t. floating-point arguments. In
particular:
> If the first and second arguments floating-point arguments to a
> function are 32-bit values, they are passed in $f12 and $f14.
As from 4.0.0 this does not happen in GCC's implementation of the ABI;
a pair of single-float arguments are still passed in $f12 and $f13, the
same as when one or both of the arguments are double-precision floats.
The registers $f12, $f13 and $f14 have been named $fa0, $fa1 and $ft10
to match the implementation.
Signed-off-by: Maximilian Ciric <max.ciric@gmail.com>
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Make md_undefined_symbol() conditional upon dealing with ELF, much like
other architectures (e.g. Arm32 and Arm64) have it. This avoids errors
in gas and even assertions in libbfd when "accidentally" e.g. a COFF-
targeting source file uses "_GLOBAL_OFFSET_TABLE_" for whatever reason.
While there also convert the final return statement to properly use
NULL.
NB: In principle 64-bit Mach-O knows GOT, too. Yet only an i?86-macho
assembler can be built right now, as per configure.tgt. Pretty clearly
adjustments to gotrel[] would also be necessary before these targets
could actually work reasonably cleanly.
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The ELF linker rejects use of this reloc type without a base register
for PIC code. Suppress its use by gas in such cases.
To keep things building for non-ELF, include the entire containing if()
in an #ifdef: All consumers of ->fx_tcbit* live in such conditionals as
well, hence there's no reason to keep the producer active.
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With us doing the transformation to an immediate operand for MOV and
various ALU insns, there's little reason to then not support the same
conversion for the other two insns which have respective immediate
operand forms. Unfortunately for IMUL (due to the 0F opcode prefix)
there's no suitable relocation, so the pre-APX forms cannot be marked
for relaxation in the assembler.
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pr30117 showed one of the assertions added by 4d1bb7955a8b was too
strict. oss-fuzz also found the second assertion to be too strict,
with this testcase distilled from 7k of garbage source:
A=%eax%%!
Y=A
Z=A
or $6,Z
PR 32721
* config/tc-i386.c (parse_register): Move "know" into
condition. Simplify.
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gas/
* config/tc-avr.c (md_assemble): Fix indentation.
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Commit 3fb6f5457e5b typoed an array subscript.
* config/tc-score7.c (s7_gen_reloc): Correct array subscript.
* testsuite/gas/score/pr32700.d,
* testsuite/gas/score/pr32700.s: New test.
* testsuite/gas/score/relax.exp: Run it.
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Extend gpr and fpr register names with names suitable for both EABIs.
Heavily inspired by the EABI documenation written by Eric Christopher,
which can be read at
https://sourceware.org/legacy-ml/binutils/2003-06/msg00436.html
2025-02-15 Anghelo Carvajal <angheloalf95@gmail.com>
* mips-dis.c (mips_fpr_names_eabi32): New variable.
(mips_fpr_names_eabi64): New variable.
(mips_abi_choices): Add "eabi32" and "eabi64" options.
Signed-off-by: Anghelo Carvajal <angheloalf95@gmail.com>
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The MIPS ABI register names are the same between n64 and n32, so remove
duplication and use n64 GPR disassembly output for the n32 test as well.
The tests were developed long before we gained output reuse support.
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Adjust a comment about "img" vendor configurations to comply with the
GNU coding standards.
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Fix broken commit 070961b377b3 ("MIPS: Set r6 as default arch if vendor
is img") that sets up GAS in an inconsistent way where "img" vendor has
been used with a 64-bit configuration, such as `mips64-img-linux-gnu'.
In that case GAS is set up to use a 64-bit ABI by default combined with
the MIPS32r6 CPU, which is 32-bit.
Consequently GAS always fails to assemble even trivial input, producing
a message such as:
Assembler messages:
Error: -march=mips32r6 is not compatible with the selected ABI
.../gas/testsuite/gas/all/nop.s:2: Error: `gp=32' used with a 64-bit ABI
unless the defaults have been suitably overridden either for the ABI or
the CPU.
Set the default CPU to MIPS64r6 for 64-bit "img" vendor configurations
then and adjust the GAS testsuite accordingly, removing 1048 FAIL and 3
ERROR regression test results for the `mips64-img-linux-gnu' and
`mips64el-img-linux-gnu' targets each.
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Add support for giving negated targets in the list of targets passed to
`mips_arch_create' for the purpose of setting the default architecture.
This is so that a subset of targets can be excluded from matching within
a broader set of targets.
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The opcode space, major opcode, and - where applicable - opcode
extension checks fully qualify the insns we're after; operand matching
has been done far earlier, so wrong operand counts cannot occur here.
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All F16C and all FMA insns are VEX-encoded; there's no need to check
for their Cpu* attributes.
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Updating should be based solely on the current instruction. For example,
recording of VEX-encoded insns as v3 should be independent of there
being earlier AMX insns.
Further for BASELINE only a very limited set of the
GNU_PROPERTY_X86_FEATURE_2_* bits should actually be taken into account:
Most of the bits represent advanced (later) features (XSAVE, XSAVEOPT,
and XSAVEC for example being part of v3).
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In commit a0094f1a70e1 ("gas: make .nops output visible in listing") I
was wrongly assuming fr_fix would be zero for rs_fill_nop, when that's
only a side effect of listing_newline() inserting dummy frags, but only
when file/line did actually change from the previous invocation. This is
in particular not going to be true when the .nops directive isn't the
first statement on a line.
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So far tricks had to be played to use .insn to encode extended-EVEX
insns; the X4 bit couldn't be controlled at all. Extend the syntax just
enough to cover all features, taking care to reject invalid feature
combinations (albeit aiming at being as lax there as possible, to offer
users as much flexibility as we can - we don't, after all, know what
future will bring).
In a pre-existing testcase replace all but one .byte; the one that needs
to remain wants to have EVEX.U clear in a way that's neither
controllable via AVX10/256 embedded rounding (would otherwise also set
EVEX.ND), nor via the index register (EVEX.X4), as there's no memory
operand. For one of the converted instances ModR/M.mod needs correcting:
An 8-bit displacement requires that to be 1, not 2. Also adjust source
comments to better represent what the bad insns mimic.
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OP_VE is the opcode space for crypto vector instructions.
Ref:
https://github.com/riscv/riscv-isa-manual/blob/main/src/vector-crypto.adoc#crypto-vector-cryptographic-instructions
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Previously we limited SSAMOSWAP.W only available on RV32, but it should
be available on RV64 as well.
See
https://github.com/riscv/riscv-cfi/blob/main/src/cfi_backward.adoc
https://github.com/riscv/riscv-isa-manual/blob/702a3e6e843235a2a13b918ae6938b04f8974ffc/src/unpriv-cfi.adoc#L789
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bfd_alloc can return NULL on out-of-memory so code needs to check the
return value and print an error. That check was missing in write.c.
notes_alloc won't return NULL, instead the underlying obstack_alloc
prints an OOM message and the process exits. This is more convenient,
and when the bfd_alloc memory is attached to the gas output bfd it is
released only slightly before the notes obstack.
* config/obj-macho.c (obj_mach_o_set_indirect_symbols): Use
notes_calloc rather than bfd_zalloc.
* write.c (set_symtab): Use notes_alloc.
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This patch addresses memory leaks in gas that show up when running the
testsuite on x86_64-w64-mingw32. The seh_ctx_cur, and weak sym naming
leaks can occur many times during assembly. The symbol hook and
section leaks are not so important since this memory needs to persist
until closing the output bfd.
* config/obj-coff-seh.c (do_seh_endproc): Free seh_ctx_cur and
its fields.
* config/obj-coff-seh.h (struct seh_context): Remove unused
"next" field.
* config/obj-coff.c (coff_obj_symbol_new_hook): Use notes_alloc
for aux entries.
(coff_obj_symbol_clone_hook): Likewise.
(obj_coff_def): Don't strdup name unless we need to do so
for tc_canonicalize_symbol_name. Free after making symbol.
(weak_name2altname, weak_altname2name): Return a char*.
(weak_uniquify): Use notes_concat.
(pecoff_obj_set_weak_hook, pecoff_obj_clear_weak_hook): Free name
returned by weak_name2altname.
(coff_frob_symbol): Similarly for weak_altname2name.
(obj_coff_section): Use notes_memdup0.
* symbols.h: Add include guard.
(notes_memdup0): New inline function.
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RISC-V already support bfloat16 instruciton like Zfbfmin, Zvfbfmin and
Zvfbfwma, so I think it's reasonable to add .bfloat16 directive to
support bfloat16 data type.
And the code logic mostly support by common code already.
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Clean up after commit 112cf77b1855 ("MIPS: use is_whitespace()") and
untangle the code flow in the handling of forced size suffixes, noting
that owing to the loop right above the only data `c' can hold at this
point is '\0', '.', or a white-space character. No functional change.
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Fix a regression from commit 3fb49709438e ("MIPS16/GAS: Fix forced size
suffixes with argumentless instructions") and reject MIPS16 instructions
that end with a dot and no forced size suffix following, e.g.:
$ cat test.s
.set mips16
foo:
break.
entry.
addiu. $2, 0x7fff
addiu. $3, $2, 0
.align 8, 0
$ as -32 -o test.o test.s
$ objdump -d test.o
test.o: file format elf32-tradbigmips
Disassembly of section .text:
00000000 <foo>:
0: e805 break
2: e809 entry
4: f7ef 4a1f addiu v0,32767
8: 4260 addiu v1,v0,0
...
$
Add a test accordingly, also verifying invalid forced size suffixes.
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oss-fuzz fuzz_as is seriously broken with respect to gas static
variables, so much so that most fuzz_as reports should simply be
ignored. This patch is a fix for
https://oss-fuzz.com/testcase-detail/6268463220654080
* config/tc-i386.c (i386_md_end): Clear GOT_symbol.
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The CPUID EDX bit[28] indicates its enablement, and it includes REP
XMODEXP and REP MONTMUL2. XMODX stands for modular exponentiation, it indicates
the support of modular exponentiation feature, both REP XMODEXP and
REP MONTMUL2 use it.
gas/ChangeLog:
* NEWS: Support Zhaoxin PadLock XMODX instructions.
* config/tc-i386.c (add_branch_prefix_frag_p): Don't add prefix to
PadLockXMODX instructions.
(output_insn): Handle PadLockXMODX instructions.
* doc/c-i386.texi: Document PadLockXMODX.
* testsuite/gas/i386/i386.exp: Add PadLockXMODX test.
* testsuite/gas/i386/padlockxmodx.d: Ditto.
* testsuite/gas/i386/padlockxmodx.s: Ditto.
opcodes/ChangeLog:
* i386-dis.c: Add PadLockXMODX.
* i386-gen.c: Ditto
* i386-opc.h (CpuPadLockXMODX): New.
* i386-opc.tbl: Add Zhaoxin PadLock XMODX instructions.
* i386-tbl.h: Regenerated.
* i386-mnem.h: Ditto.
* i386-init.h: Ditto.
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We want is_whitespace() to be used uniformly, no matter what this then
expands to.
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Convert uses of ISSPACE() and testing for specific characters into
calls to is_whitespace and is_end_of_stmt. While doing that, also
remove some redundant tests, like ';' together with is_end_of_line[]
and is_whitespace and !is_end_of_line.
Note the invalid casts being fixed as part of moving to is_... macros;
there were (unsigned int) where there should have been (unsigned char)
applied on char as index to is_end_of_line[].
Beware that the input language changes slightly: some constructs with
whitespace characters other than space and TAB are now invalid.
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Unwinding of the stack pointer (SP) is performed using the assumed
default rule ".cfi_val_offset <SP-reg>, 0", so that SP unwinds as:
SP = CFA
Warn if the CFI directive .cfi_val_offset is encountered for the
SP register with a different offset.
gas/
* gen-sframe.c (sframe_xlate_do_val_offset): Skip SFrame FDE
if non-default SP value offset.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
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Use the appropriate struct cfi_insn_data union members to access
fields when generating SFrame information from CFI directives.
gas/
* gen-sframe.c (sframe_xlate_do_def_cfa, sframe_xlate_do_offset,
sframe_xlate_do_val_offset): Access ri fields, as .cfi_def_cfa,
.cfi_offset, and .cfi_val_offset define a register and offset
value.
* (sframe_xlate_do_def_cfa_register): Access r field, as
.cfi_def_cfa_register defines a register.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
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Wherever blanks are permissible in input, tabs ought to be permissible,
too. This is particularly relevant when -f is passed to gas (alongside
appropriate input). At the same time use is_end_of_stmt() instead of an
open-coded check in adjacent code.
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Replace an open-coded check and convert ISSPACE() uses.
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Convert an open-coded check.
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Convert an open-coded check.
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Wherever blanks are permissible in input, tabs ought to be permissible,
too. This is particularly relevant when -f is passed to gas (alongside
appropriate input).
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Convert an open-coded check.
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Wherever blanks are permissible in input, tabs ought to be permissible,
too. This is particularly relevant when -f is passed to gas (alongside
appropriate input). Also convert an open-coded check.
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Wherever blanks are permissible in input, tabs ought to be permissible,
too. This is particularly relevant when -f is passed to gas (alongside
appropriate input).
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Wherever blanks are permissible in input, tabs ought to be permissible,
too. This is particularly relevant when -f is passed to gas (alongside
appropriate input). Also convert open-coded checks as well as ISSPACE()
uses. At the same time use is_end_of_stmt() instead of a kind-of-open-
coded check in adjacent code.
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Wherever blanks are permissible in input, tabs ought to be permissible,
too. This is particularly relevant when -f is passed to gas (alongside
appropriate input). Also convert an ISSPACE() use. At the same time use
is_end_of_stmt() instead of open-coded checks in adjacent code.
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Convert ISSPACE() uses. At the same time use is_end_of_stmt() instead
of open-coded checks in adjacent code. The function also needs using in
next_line_shows_parallel().
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Wherever blanks are permissible in input, tabs ought to be permissible,
too. This is particularly relevant when -f is passed to gas (alongside
appropriate input). At the same time use is_end_of_stmt() instead of
kind-of-open-coded checks in adjacent code.
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