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2025-05-09aarch64: Add new test advsimd-widening-narrowing.dAlice Carlotti2-0/+1210
All instructions were previously untested.
2025-05-09aarch64: Add new test advsimd-three-same.dAlice Carlotti2-0/+2453
All instructions except orr/mov were previously untested.
2025-05-09aarch64: Add missing widening fmops testAlice Carlotti3-10/+8
Also remove the valid instructions from the test for invalid instructions - this meant that the instruction was previously being tested for assembly but not disassembly.
2025-05-09aarch64: Add tests for fabd, urecpe and ursqrtAlice Carlotti2-2/+22
Other instructions in the encoding group are tested in advsimd-fp16.d, so add these instructions to the existing test file.
2025-05-09aarch64: Add tests for fcvt, fcvtzs and fcvtzuAlice Carlotti2-2/+52
Other instructions in the encoding group are tested in float-fp16.d, so add these instructions to the existing test file.
2025-05-09aarch64: Add tests for csdb and eret to system.dAlice Carlotti2-0/+4
2025-05-09aarch64: Add test for ands and bicsAlice Carlotti2-0/+107
The other instructions in the encoding group are tested in shifted.d, so add these to the existing test file.
2025-05-09aarch64: Adjust float-fp16.d test patternsAlice Carlotti1-164/+164
Adjust the test to match instruction addresses of any length.
2025-05-09aarch64: Adjust advsimd-fp16.d test patternsAlice Carlotti1-569/+569
Adjust the test to match instruction addresses of any length, and escape literal '.' characters for a stricter match.
2025-05-09aarch64: Adjust shifted.d test patternsAlice Carlotti1-727/+727
Adjust the test to match any instruction addresses, so that the test can be extended more easily.
2025-05-09aarch64: Eliminate AARCH64_OPND_SVE_ADDR_RAlice Carlotti1-15/+24
Adjust parsing for AARCH64_OPND_SVE_ADDR_RR{_LSL*} operands to accept implicit XZR offsets. Add new AARCH64_OPND_SVE_ADDR_RM{_LSL*} operands to support instructions where an XZR offset is allowed but must be specified explicitly. This allows the removal of the duplicate opcode table entries using AARCH64_OPND_SVE_ADDR_R.
2025-05-09aarch64: Disallow invalid SVE addressing modesAlice Carlotti6-9/+106
The fix for PR22988 in 2018 added a new operand AARCH64_OPND_SVE_ADDR_R to support implicit XZR offsets, but this fix had several flaws that meant it accepted several invalid addressing modes: 1. The base register type wasn't properly checked when the optional register offset was omitted. This meant that ldff1b {z1.s}, p1/z,[z1.d] was parsed as if it were ldff1b z1.d, p1/z, [x1.d, xzr]. 2. The explicit offset parsing didn't include a shift type, so the new operand would incorrectly parse ldff1h{z0.s}, p0/z, [x0, x0] as if it were ldff1h{z0.s}, p0/z, [x0, x0, lsl #1]. 3. Regardless of the above correctness issues, support for implicit offsets should have been added by amending the operands in the existing opcode table entries, instead of adding new duplicate table entires. Issue 1 can be fixed by using an "if" instead of an "else if" in parse_operands, while issue 2 can be fixed by failing when the first condition is false. This patch applies just these two fixes, leaving issue 3 to be addressed in a subsequent more invasive patch. The instructions removed from the test sme-5.d are architecturally invalid. The new tests cover all of the affected ldff1 variants; the issue also affected SME ZA ld1*/st1* instructions using the same operand type.
2025-05-09RISC-V: Support Zce 1.0Jerry Zhang Jian5-1/+20
Zce is the extension defined in code-size-reduction Ref: https://github.com/riscvarchive/riscv-code-size-reduction Co-authored-by: Kito Cheng <kito.cheng@sifive.com>
2025-05-09RISC-V: Add augmented hypervisor extension 'sha' support.Jiawei4-1/+6
The augmented hypervisor extension 'sha'[1] is a new profile-defined extension that captures the full set of features that are mandated to be supported along with the H extension. https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc#rva23s64-profile bfd/ChangeLog: * elfxx-riscv.c: New extension and implies. gas/ChangeLog: * NEWS: New extension. * testsuite/gas/riscv/imply.d: New test for sha. * testsuite/gas/riscv/imply.s: Ditto. * testsuite/gas/riscv/march-help.l: New extension.
2025-05-09RISC-V: Add Privileged Architecture 1.13 CSRs.Jiawei15-4/+2518
This patch support RISC-V Privileged Architecture 1.13 CSRs 'medelegh' and 'hedelegh'. More details between 1.12 and 1.13 see [1]. [1] https://github.com/riscv/riscv-isa-manual/blob/main/src/priv-preface.adoc Version log: Remove gas/po changes. bfd/ChangeLog: * cpu-riscv.c: New option. * cpu-riscv.h (enum riscv_spec_class): Ditto. binutils/ChangeLog: * doc/binutils.texi: New option. gas/ChangeLog: * NEWS: Add priv-1.13 support. * config/tc-riscv.c: New option. * configure: Ditto. * configure.ac: Ditto. * testsuite/gas/riscv/csr-version-1p10.d: New CSR. * testsuite/gas/riscv/csr-version-1p10.l: New warning. * testsuite/gas/riscv/csr-version-1p11.d: New CSR. * testsuite/gas/riscv/csr-version-1p11.l: New warning. * testsuite/gas/riscv/csr-version-1p12.d: New CSR. * testsuite/gas/riscv/csr-version-1p12.l: New warning. * testsuite/gas/riscv/csr.s: New CSR. * testsuite/gas/riscv/attribute-15.d: New test. * testsuite/gas/riscv/attribute-16.d: New test. * testsuite/gas/riscv/csr-version-1p13.d: New test. * testsuite/gas/riscv/csr-version-1p13.l: New test. include/ChangeLog: * opcode/riscv-opc.h (CSR_MEDELEGH): New CSR. (CSR_HEDELEGH): Ditto. (DECLARE_CSR): Ditto.
2025-05-09RISC-V: Added vendor extensions, xmipscbop, xmipscmov, xmipsexectl and xmipslspChao-ying Fu6-0/+200
Spec: https://mips.com/wp-content/uploads/2025/03/P8700-F_Programmers_Reference_Manual_Rev1.82_3-19-2025.pdf Added MIPS vendor extensions, xmipscbop, xmipscmov, xmipsexectl and xmipslsp with verison 1.0. Passed binutils testsuites of targets elf32/elf64/linux32/linux64. Signed-off-by: Jovan Dmitrović <jovan.dmitrovic@htecgroup.com> Signed-off-by: Chao-ying Fu <cfu@wavecomp.com>
2025-05-06gas: input_scrub buffersAlan Modra1-8/+19
This tidies freeing of input_scrub buffers on failure paths, making input_scrub_end iterate over any input_scrub_push'd files or string buffers to clean up memory. * input-scrub.c (input_scrub_free): New function. (input_scrub_pop): Call it rather than input_scrub_end. (input_scrub_end): Iterate over next_saved_file freeing buffers. (input_scrub_next_buffer): Move sb_kill to input_scrub_free.
2025-05-02aarch64: drop stray newlinesJan Beulich1-3/+3
as_bad() already emits a newline; having extra ones leads to somewhat distorted diagnostics.
2025-05-02arm: drop stray newlinesJan Beulich1-11/+11
Both as_bad() and as_warn() already emit a newline; having extra ones leads to somewhat distorted diagnostics.
2025-05-02COFF: correct function auxiliary symbol data clearingJan Beulich1-2/+2
It's unclear why the array part of the union was used there, when we're dealing with a function. Originally, when 32-bit hosts and targets were prevailing, the memset() in question ended up clearing the entire x_fcn, while for 64-bit hosts/targets only x_lnnoptr would have been cleared. Then a2c7ca15a560 ("Use stdint types in coff internal_auxent") made things consistent, but imo in the wrong direction (and likely unintentionally). Go back to what apparently was meant originally, using the correct part of the union now.
2025-05-02COFF: function auxiliary symbolsJan Beulich12-17/+216
For one at least x86 gcc emits .def/.endef for functions, but no 2nd pair to designate their ends (sizes). While we can't recover the sizes, we can at least properly establish the chain of function symbols, which of course requires to emit auxiliary symbols for every function symbol even when there's no C_EFCN: We simply shouldn't be making their insertion conditional upon there not being a function processing of which is "in progress". In fact it was wrong to assign dual purpose to {,next_}set_end: Functions don't have "ends" set, but links to the next one. The same symbol table entry can serve both as an end marker and be a part of the chain of (defined) functions; this can't be expressed by a single static variable. Use what (again) becomes last_functionP for this purpose, along with tracking what symbol C_EFCN should apply to. This then allows to undo exposing of the respective (supposedly static) tracking variable, which PPC's XCOFF handling had introduced. Also rename it back to what it was before its exposure. For now the new testcases are XFAIL for Arm64 since there, unlike for Arm32, mapping symbols are emitted for COFF, too.
2025-05-02gas: add new COFF-specific subdir in testsuiteJan Beulich4-17/+34
... and move the cofftag testcase there (from all/). Just like we have one for ELF.
2025-05-02Arm/COFF: accept .def outside of CCS modeJan Beulich3-2/+6
There's no reason to reject this common COFF directive when it doesn't have any other meaning.
2025-04-28PowerPC: Support for Prefixed Add Immediate Shifted Instruction (RFC02686)Surya Kumari Jangala2-0/+53
opcodes/ * ppc-opc.c (insert_si32, extract_si32, insert_nsi32, extract_nsi32): New functions. (SI32, NSI32, P_D_SI32_MASK, P_DRAPCREL_SI32_MASK): New macros. (IMM32): Update for new macros. (powerpc_opcodes): Add plis, paddis, psubis. gas/ * testsuite/gas/ppc/future.s: New test. * testsuite/gas/ppc/future.d: Likewise.
2025-04-24gas: sframe: fix handling of .cfi_def_cfa_registerClaudiu Zissulescu4-1/+29
Fix PR gas/32879 sframe: Assembler internal error when translating cfi_def_cfa_register As per the documentation, .cfi_def_cfa_register modifies a rule for computing CFA; the register is updated, but the offset remains the same. While translating .cfi_def_cfa_register into SFrame context, we use the information from last translated FRE to set the CFA offset. However, there may be cases when the last translated FRE is empty. Use last FRE only if available. Signed-off-by: Claudiu Zissulescu <claudiu.zissulescu-ianculescu@oracle.com> Signed-off-by: Indu Bhagat <indu.bhagat@oracle.com>
2025-04-23LoongArch: Add test for divide by zero in instructionsLulu Cai3-0/+7
Added tests for division/modulo by zero for instruction expressions.
2025-04-22gas: sframe: Fix typo in comment on SFrame identifierJens Remus4-4/+4
gas/config/ * tc-aarch64.c (aarch64_sframe_get_abi_arch): Fix typo in comment on SFrame identifier. * tc-aarch64.h (aarch64_sframe_get_abi_arch, sframe_get_abi_arch): Likewise. * tc-i386.c (x86_sframe_get_abi_arch): Likewise. * tc-i386.h (x86_sframe_get_abi_arch, sframe_get_abi_arch): Likewise. Reported-by: Indu Bhagat <indu.bhagat@oracle.com> Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2025-04-21avoid bogus format-overflow errorAlan Modra1-7/+8
Seen on x86_64-linux Ubuntu 24.04.2 using gcc-13.3.0 with CFLAGS="-m32 -g -O2 -fsanitize=address,undefined" In function ‘sprintf’, inlined from ‘s_mri_for’ at gas/config/tc-m68k.c:6941:5: /usr/include/bits/stdio2.h:30:10: error: null destination pointer [-Werror=format-overflow=] 30 | return __builtin___sprintf_chk (__s, __USE_FORTIFY_LEVEL - 1, | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 31 | __glibc_objsize (__s), __fmt, | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 32 | __va_arg_pack ()); | ~~~~~~~~~~~~~~~~~ Rewrite the code without sprintf, as in other parts of s_mri_for. See also commit 760fb390fd4c and following commits. Note that adding -D_FORTIFY_SOURCE=0 to CFLAGS (which is a good idea when building with sanitizers) merely transforms the sprintf_chk error here into one regarding plain sprintf.
2025-04-18loongarch gas resolving constant expressionsAlan Modra1-10/+22
The test added in commit 4fe96ddaf614 results in an asan complaint: loongarch-parse.y:225:16: runtime error: left shift of negative value -1 To avoid the complaint, perform left shifts as unsigned (which gives the same result on 2's complement machines). Do the same for addition, subtraction and multiplication. Furthermore, warn on divide/modulus by zero.
2025-04-13LoongArch: Support LA32R aliases rdcnt{vl,vh,id}.wWANG Xuerui4-0/+16
These LA32R instructions are in fact special cases of the LA32S/LA64 rdtime{l,h}.w (with only one output operand instead of two, the other one being forced to $zero), but are named differently in the LA32R ISA manual nevertheless. As the LA32R names are more memorable to a degree (especially for those having difficulties remembering which operand corresponds to the node ID), support them by making them aliases of the corresponding LA32S/LA64 instruction respectively, and make them render as such in disassembly. Signed-off-by: WANG Xuerui <git@xen0n.name>
2025-04-09aarch64 tests: escape dot in regex pattern to really match a dotMatthieu Longo3-3/+3
2025-04-09s390: Add support for z17 as CPU nameJens Remus3-4/+6
So far IBM z17 was identified as arch15. Add the real name, as it has been announced. [1] [1]: IBM z17 announcement letter, AD25-0015, https://www.ibm.com/docs/en/announcements/z17-makes-more-possible gas/ * config/tc-s390.c (s390_parse_cpu): Add z17 as alternate CPU name for arch15. * doc/c-s390.texi: Likewise. * doc/as.texi: Likewise. opcodes/ * s390-mkopc.c (main): Add z17 as alternate CPU name for arch15. Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2025-04-08LoongArch: Warn about right shifts of negative numbersLulu Cai5-0/+89
The GNU Assembler User Guide says that the right shift operator ">>" in an expression is the same as the C operator. On LoongArch the assembler directives and instructions do not treat negative numbers ">>" the same way. The directives treats negative numbers ">>" as logical right shifts while the instructions treats them as arithmetic right shifts. The right shift of negative numbers in the instructions may be changed from an arithmetic right shift to a logical right shift in the future, and a warning is issued for this.
2025-04-07nm: also retrieve size for COFF function symbolsJan Beulich1-2/+2
Like ELF for all symbols, COFF can record size for at least function ones. Use that - if available - in preference to the distance-to-next- symbol heuristic. To be able to use the new test there, make TI C54x follow TI C4x in providing .sdef to cover for .def already having different meaning.
2025-03-29x86: Add {noimm8s} pseudo prefixH.J. Lu6-0/+142
Instruction templates with only sign-extended 8-bit immediate operand also have a second template with full-operand-size immediate operand under a different opcode. Add {noimm8s} pseudo prefix to exclude templates with only sign-extended 8-bit immediate operand. gas/ PR gas/32811 * config/tc-i386.c (pseudo_prefixes): Add no_imm8s. (operand_size_match): Return false for templates with only sign- extended 8-bit immediate operand if {noimm8s} is used. (parse_insn): Handle Prefix_NoImm8s. * doc/c-i386.texi: Document {noimm8s}. * testsuite/gas/i386/pseudos.s: Add tests for {noimm8s}. * testsuite/gas/i386/x86-64-pseudos.s: Likewise. * testsuite/gas/i386/pseudos.d: Updated. * testsuite/gas/i386/x86-64-pseudos.d: Likewise. opcodes/ PR gas/32811 * opcodes/i386-opc.h (Prefix_NoImm8s): New. * i386-opc.tbl: Add {noimm8s} pseudo prefix. * i386-mnem.h: Regenerated. * i386-tbl.h: Likewise. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
2025-03-27x86: Remove AVX10.2 256 bit rounding supportHaochen Jiang33-2733/+11
Since we will support 512 bit on both P-core and E-core for AVX10, 256 bit rounding is not that useful because we currently have rounding feature directly on E-core now and no need to use 256-bit rounding as somehow a workaround. This patch will remove all the support and backport to Binutils 2.44. gas/ChangeLog: * NEWS: Mention support removal. * config/tc-i386.c (build_evex_prefix): Remove U bit encode. (check_VecOperands): Remove ymm check for rounding. (s_insn): Revise .insn comment. * testsuite/gas/i386/avx10_2-256-cvt-intel.d: Remove ymm rounding related test. * testsuite/gas/i386/avx10_2-256-cvt.d: Ditto. * testsuite/gas/i386/avx10_2-256-cvt.s: Ditto. * testsuite/gas/i386/avx10_2-256-miscs-intel.d: Ditto. * testsuite/gas/i386/avx10_2-256-miscs.d: Ditto. * testsuite/gas/i386/avx10_2-256-miscs.s: Ditto. * testsuite/gas/i386/avx10_2-256-satcvt-intel.d: Ditto. * testsuite/gas/i386/avx10_2-256-satcvt.d: Ditto. * testsuite/gas/i386/avx10_2-256-satcvt.s: Ditto. * testsuite/gas/i386/evex.d: Ditto. * testsuite/gas/i386/evex.s: Ditto. * testsuite/gas/i386/i386.exp: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-cvt-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-cvt.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-cvt.s: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-miscs-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-miscs.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-miscs.s: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-satcvt-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-satcvt.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-satcvt.s: Ditto. * testsuite/gas/i386/x86-64-evex.d: Ditto. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/avx10_2-rounding-intel.d: Removed. * testsuite/gas/i386/avx10_2-rounding-inval.l: Removed. * testsuite/gas/i386/avx10_2-rounding-inval.s: Removed. * testsuite/gas/i386/avx10_2-rounding.d: Removed. * testsuite/gas/i386/avx10_2-rounding.s: Removed. * testsuite/gas/i386/x86-64-avx10_2-rounding-intel.d: Removed. * testsuite/gas/i386/x86-64-avx10_2-rounding.d: Removed. * testsuite/gas/i386/x86-64-avx10_2-rounding.s: Removed. opcodes/ChangeLog: * i386-dis.c (struct instr_info): Remove U bit. (get_valid_dis386): Roll back to APX condition. * i386-opc.tbl: Remove ymm rounding support. * i386-tbl.h: Regenerated.
2025-03-26RISC-V: add Smrnmi 1.0 instruction supportJerry Zhang Jian2-0/+11
Add instruction `mnret' support Ref: https://github.com/riscv/riscv-isa-manual/blob/bb8b9127f81965eeff2d150c211d1c89376591c4/src/rnmi.adoc https://github.com/riscv/riscv-opcodes/blob/946eb673874b3a0f2474d1424dc28bc7ee53c306/extensions/rv_smrnmi bfd/ChangeLog: * elfxx-riscv.c: Add new Smrnmi instruction class handling gas/ChangeLog: * testsuite/gas/riscv/smrnmi.s: New test for mnret * testsuite/gas/riscv/rmrnmi.d: Likewise include/ChangeLog: * opcode/ricsv-opc.h: Add MATCH_MNRET, MASK_MNRET * opcode/riscv.h: Add new instruction class opcodes/ChangeLog: * riscv-opc.c: Add `mnret' instruction Signed-off-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com>
2025-03-24aarch64: Add missing FEAT_MEC dc encodings and gate sysregsEzra Sitorus5-0/+31
FEAT_MEC support was introduced in [1]. However, the dc instruction was missing these encodings: - DC CIPAE - DC CIGDPAE Furthermore, the Arm ARM states that FEAT_MEC is an optional extension, introduced for v9.2-a. Therefore, these sysregs: - MECIDR_EL2 - MECID_P0_EL2 - MECID_A0_EL2 - MECID_P1_EL2 - MECID_A1_EL2 - VMECID_P_EL2 - VMECID_A_EL2 - MECID_RL_A_EL3 which were introduced in that commit now require -march=armv9.2-a at the very least to be enabled, as well as the dc encodings. opcodes/ChangeLog: * aarch64-opc.c (aarch64_sys_regs_dc): Add "cipae" and "cigdpae". * aarch64-sys-regs.def: Add V8_7A as a requirement for the above system registers. gas/testsuite/gas/ChangeLog * aarch64/mec-invalid.s: Add .arch directive. * aarch64/mec.d: Add .arch directive and check for cipae, cigdpae. * aarch64/mec.s: Add MEC data cache operations test. * aarch64/mec-arch-bad.d: New test to check for bad arch version. * aarch64/mec-arch-bad.l: Above. [1]: https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=31f2faf5cf112931cfb8c0564a2b78477c907fe3 Regression tested on aarch64-none-elf
2025-03-21aarch64: simplify RCPC3 unpredictable logicJan Beulich5-66/+32
The original observation was that STILP is warned about when everything is fine. Documentation, not just for STILP, says explicitly that behavior is identical to respective pre-existing insns (for STILP in particular that's STP). With that it's unclear why distinct logic was added: Other code can be re-used, simply distinguishing by the number of operands. This was diagnostics also end up more consistent. Along with adding some STILP uses to the (positive) testcase, also add a pair of STLR to similarly demonstrate that the register overlap goes without warning when there's no write-back.
2025-03-18RISC-V: Support pointer masking extension 1.0Jerry Zhang Jian4-1/+15
- Adding Ssnpm, Smnpm, Smmpm, Sspm, and Supm - No new CSR added - Pointer masking only applies to RV64 - Ref: https://github.com/riscv/riscv-j-extension/releases/download/pointer-masking-ratified/pointer-masking-ratified.pdf Signed-off-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com>
2025-03-18gas/NEW: Updated news related to mapping symbol and extensions for risc-vNelson Chu1-0/+11
2025-03-18RISC-V: Add extension XTheadVdot for T-Head VECTOR vendor extension [1]Jin Ma4-0/+67
T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds the additional extension "XTheadVdot" based on the "V" extension, and it provides four 8-bit multiply and add with 32-bit instructions for the "v" extension. The 'th' prefix and the "XTheadVector" extension are documented in a PR for the RISC-V toolchain conventions ([2]). Co-Authored-By: Lifang Xia <lifang_xia@linux.alibaba.com> [1] https://github.com/XUANTIE-RV/thead-extension-spec/tree/master/xtheadvdot [2] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add support for "XTheadVdot" extension. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * doc/c-riscv.texi: Likewise. * testsuite/gas/riscv/march-help.l: Likewise. * testsuite/gas/riscv/x-thead-vdot.d: New test. * testsuite/gas/riscv/x-thead-vdot.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_TH_VMAQA_VV): New. * opcode/riscv.h (enum riscv_insn_class): Add insn class for XTheadVdot. opcodes/ChangeLog: * riscv-opc.c: Likewise.
2025-03-18RISC-V: Avoid parsing arch string repeatedly for dis-assemblerNelson Chu1-18/+5
Since we now always generate $x+isa for now, these would increase the dis-assemble time by parsing the same architecture string repeatedly. We already have `arch_str' field into `subset_list' to record the current architecture stirng, but it's only useful for assembler, since dis-assembler and linker don't need it before. Now for dis-assembler, we just need to update the `arch_str' after parsing the architecture stirng, and then avoid parsing repeatedly if the strings are the same.
2025-03-14gas: permit wider-than-byte operands for .cfi_escapeJan Beulich5-7/+53
Some DW_CFA_* and DW_OP_* take wider than byte, but non-LEB128 operands. Having to hand-encode such when needing to resort to .cfi_escape isn't very helpful.
2025-03-14gas: permit LEB128 operands for .cfi_escapeJan Beulich6-7/+87
Many DW_CFA_* and DW_OP_* take LEB128 operands. Having to hand-encode such when needing to resort to .cfi_escape isn't very helpful.
2025-03-14gas: make NO_LISTING work againJan Beulich3-54/+20
Presumably since no target enables this and there's also no configure control, builds with NO_LISTING defined didn't really work anymore. Convert fallback functions to macros and add #ifndef in a few places. (Behavior is different for affected command line options vs directives: The former are rejected as unrecognized, while the latter are silently ignored. I think that's fair enough.)
2025-03-14gas: include .cfi_* generated data in listingJan Beulich9-7/+162
These are data generating directives not overly different from e.g. .byte and .long. Whatever (directly) results from should also be represented in the listing, if one was requested. It's just that the output data is generated much later than the parsing of the directive arguments.
2025-03-14gas: deal with the need for relocations from .cfi_{escape,fde_data}Jan Beulich8-10/+49
Ignoring return values often isn't a good idea. The Sparc assembler in particular would report an internal error if an expression with relocation specifier is used with .cfi_escape, when the same works fine with .byte. Propagate the relocation indicator up from do_parse_cons_expression(), and eventually into emit_expr_with_reloc(). dot_cfi_fde_data(), only retaining the expression's X_add_number, would require further work. Simply report the lack of support there. While there, also check that what we were dealt is actually a constant.
2025-03-10gas: Use SFrame header and FDE field sizes when generating .sframeJens Remus1-16/+13
The use of SFRAME_RELOC_SIZE in generation of SFrame stack trace information from CFI directives erroneously suggested that this could be used to configure a different relocation size. But in practice it is tied to the SFrame field sizes it is used for and therefore cannot be changed. Replace the uses of SFRAME_RELOC_SIZE by the size of the respective SFrame header and FDE fields when emitting SFrame information. While at it enhance some comments. gas/ * gen-sframe.c (SFRAME_RELOC_SIZE): Delete. (sizeof_member): Define. (output_sframe_funcdesc): Use size of SFrame FDE fields instead of SFRAME_RELOC_SIZE. (output_sframe_internal): Use size of SFrame header fields instead of SFRAME_RELOC_SIZE. Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2025-03-07AVR: gas/32704 - Improve code generation for __gcc_isr.Georg-Johann Lay1-54/+122
The prologue generated by __gcc_isr can be improved in situations where: * ZERO_REG is needed, and * SREG is not clobbered by the ISR, and * avr-gcc provides a GPR >= R16 with the Done chunk, and * Code generation is for ordinary AVRs (not AVRrc). For example, the prologue for volatile char var; __attribute__((signal)) void __vector_1 (void) { var = 1; var = 0; } may be 00000000 <__vector_1>: 0: 8f 93 push r24 2: 1f 92 push r1 4: 80 e0 ldi r24, 0 6: 18 2e mov r1, r24 instead of the code as currently generated by GAS: 00000000 <__vector_1>: 0: 1f 92 push r1 2: 1f b6 in r1, SREG 4: 1f 92 push r1 6: 11 24 clr r1 8: 8f 93 push r24 which consumes more stack, time and code than needed. gas/ PR gas/32704 PR gas/21683 * config/tc-avr.c (avr_isr): bool-ize. (avr_emit_insn): Emit "mov" code as MOV R1,<reg>. (avr_isr_stack_t): New typedef. (avr_emit_push, avr_emit_pop): New static functions. (avr_patch_gccisr_frag): Overhaul prologue and epilogue generation.
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