diff options
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 10 | ||||
| -rw-r--r-- | opcodes/mips-dis.c | 14 | ||||
| -rw-r--r-- | opcodes/mips-opc.c | 8 |
3 files changed, 30 insertions, 2 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 666238d..dcfa522 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,13 @@ +2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com> + + * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and + mips64r6 descriptors. + (parse_mips_ase_option): Handle -Mginv option. + (print_mips_disassembler_options): Document -Mginv. + * mips-opc.c (decode_mips_operand) <+\>: New operand format. + (GINV): New macro. + (mips_opcodes): Define ginvi and ginvt. + 2018-06-13 Scott Egerton <scott.egerton@imgtec.com> Faraz Shahbazker <Faraz.Shahbazker@mips.com> diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c index 95a1937..aeb8d7e 100644 --- a/opcodes/mips-dis.c +++ b/opcodes/mips-dis.c @@ -563,7 +563,7 @@ const struct mips_arch_choice mips_arch_choices[] = { "mips32r6", 1, bfd_mach_mipsisa32r6, CPU_MIPS32R6, ISA_MIPS32R6, (ASE_EVA | ASE_MSA | ASE_VIRT | ASE_XPA | ASE_MCU | ASE_MT | ASE_DSP - | ASE_DSPR2 | ASE_DSPR3 | ASE_CRC), + | ASE_DSPR2 | ASE_DSPR3 | ASE_CRC | ASE_GINV), mips_cp0_names_mips3264r2, mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, @@ -603,7 +603,7 @@ const struct mips_arch_choice mips_arch_choices[] = ISA_MIPS64R6, (ASE_EVA | ASE_MSA | ASE_MSA64 | ASE_XPA | ASE_VIRT | ASE_VIRT64 | ASE_MCU | ASE_MT | ASE_DSP | ASE_DSPR2 | ASE_DSPR3 | ASE_CRC - | ASE_CRC64), + | ASE_CRC64 | ASE_GINV), mips_cp0_names_mips3264r2, mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, @@ -929,6 +929,12 @@ parse_mips_ase_option (const char *option) return TRUE; } + if (CONST_STRNEQ (option, "ginv")) + { + mips_ase |= ASE_GINV; + return TRUE; + } + return FALSE; } @@ -2569,6 +2575,10 @@ with the -M switch (multiple options should be separated by commas):\n")); ASE instructions.\n")); fprintf (stream, _("\n\ + ginv Recognize the Global INValidate (GINV) ASe\n\ + instructions.\n")); + + fprintf (stream, _("\n\ gpr-names=ABI Print GPR names according to specified ABI.\n\ Default: based on binary being disassembled.\n")); diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index d172801..1cbcbc6 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -139,6 +139,7 @@ decode_mips_operand (const char *p) case '\'': BRANCH (26, 0, 2); case '"': BRANCH (21, 0, 2); case ';': SPECIAL (10, 16, SAME_RS_RT); + case '\\': BIT (2, 8, 0); /* (0 .. 3) */ } break; @@ -408,6 +409,9 @@ decode_mips_operand (const char *p) #define CRC ASE_CRC #define CRC64 ASE_CRC64 +/* Global INValidate (GINV) support. */ +#define GINV ASE_GINV + /* The order of overloaded instructions matters. Label arguments and register arguments look the same. Instructions that can have either for arguments must apear in the correct order in this table for the @@ -3361,6 +3365,10 @@ const struct mips_opcode mips_builtin_opcodes[] = {"crc32cw", "t,s,-d", 0x7c00018f, 0xfc00ffff, MOD_1|RD_2, 0, 0, CRC, 0 }, {"crc32cd", "t,s,-d", 0x7c0001cf, 0xfc00ffff, MOD_1|RD_2, 0, 0, CRC64, 0 }, +/* MIPS Global INValidate (GINV) ASE. */ +{"ginvi", "s", 0x7c00003d, 0xfc1fffff, RD_1, 0, 0, GINV, 0 }, +{"ginvt", "s,+\\", 0x7c0000bd, 0xfc1ffcff, RD_1, 0, 0, GINV, 0 }, + /* No hazard protection on coprocessor instructions--they shouldn't change the state of the processor and if they do it's up to the user to put in nops as necessary. These are at the end so that the |