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-rw-r--r--gdb/arch/aarch64-insn.c36
-rw-r--r--gdb/arch/aarch64-insn.h146
-rw-r--r--gdb/arch/aarch64-mte-linux.h6
-rw-r--r--gdb/arch/aarch64.h94
-rw-r--r--gdb/arch/arc.c26
-rw-r--r--gdb/arch/arc.h19
-rw-r--r--gdb/arch/arm-get-next-pcs.c162
-rw-r--r--gdb/arch/arm-get-next-pcs.h6
-rw-r--r--gdb/arch/arm-linux.c11
-rw-r--r--gdb/arch/arm-linux.h9
-rw-r--r--gdb/arch/arm.c48
-rw-r--r--gdb/arch/arm.h172
-rw-r--r--gdb/arch/loongarch.c12
-rw-r--r--gdb/arch/loongarch.h32
-rw-r--r--gdb/arch/ppc-linux-common.c38
-rw-r--r--gdb/arch/ppc-linux-common.h28
-rw-r--r--gdb/arch/riscv.c8
-rw-r--r--gdb/arch/riscv.h25
-rw-r--r--gdb/arch/xtensa.h8
19 files changed, 432 insertions, 454 deletions
diff --git a/gdb/arch/aarch64-insn.c b/gdb/arch/aarch64-insn.c
index 54874df..016f9d6 100644
--- a/gdb/arch/aarch64-insn.c
+++ b/gdb/arch/aarch64-insn.c
@@ -47,8 +47,8 @@ decode_masked_match (uint32_t insn, uint32_t mask, uint32_t pattern)
Return 1 if the opcodes matches and is decoded, otherwise 0. */
int
-aarch64_decode_adr (CORE_ADDR addr, uint32_t insn, int *is_adrp,
- unsigned *rd, int32_t *offset)
+aarch64_decode_adr (CORE_ADDR addr, uint32_t insn, int *is_adrp, unsigned *rd,
+ int32_t *offset)
{
/* adr 0ii1 0000 iiii iiii iiii iiii iiir rrrr */
/* adrp 1ii1 0000 iiii iiii iiii iiii iiir rrrr */
@@ -71,7 +71,7 @@ aarch64_decode_adr (CORE_ADDR addr, uint32_t insn, int *is_adrp,
aarch64_debug_printf ("decode: 0x%s 0x%x %s x%u, #?",
core_addr_to_string_nz (addr), insn,
- *is_adrp ? "adrp" : "adr", *rd);
+ *is_adrp ? "adrp" : "adr", *rd);
return 1;
}
return 0;
@@ -88,8 +88,7 @@ aarch64_decode_adr (CORE_ADDR addr, uint32_t insn, int *is_adrp,
Return 1 if the opcodes matches and is decoded, otherwise 0. */
int
-aarch64_decode_b (CORE_ADDR addr, uint32_t insn, int *is_bl,
- int32_t *offset)
+aarch64_decode_b (CORE_ADDR addr, uint32_t insn, int *is_bl, int32_t *offset)
{
/* b 0001 01ii iiii iiii iiii iiii iiii iiii */
/* bl 1001 01ii iiii iiii iiii iiii iiii iiii */
@@ -190,8 +189,8 @@ aarch64_decode_cb (CORE_ADDR addr, uint32_t insn, int *is64, int *is_cbnz,
Return 1 if the opcodes matches and is decoded, otherwise 0. */
int
-aarch64_decode_tb (CORE_ADDR addr, uint32_t insn, int *is_tbnz,
- unsigned *bit, unsigned *rt, int32_t *imm)
+aarch64_decode_tb (CORE_ADDR addr, uint32_t insn, int *is_tbnz, unsigned *bit,
+ unsigned *rt, int32_t *imm)
{
/* tbz b011 0110 bbbb biii iiii iiii iiir rrrr */
/* tbnz B011 0111 bbbb biii iiii iiii iiir rrrr */
@@ -250,8 +249,7 @@ aarch64_decode_ldr_literal (CORE_ADDR addr, uint32_t insn, int *is_w,
if (aarch64_debug)
debug_printf ("decode: %s 0x%x %s %s%u, #?\n",
core_addr_to_string_nz (addr), insn,
- *is_w ? "ldrsw" : "ldr",
- *is64 ? "x" : "w", *rt);
+ *is_w ? "ldrsw" : "ldr", *is64 ? "x" : "w", *rt);
return 1;
}
@@ -335,9 +333,9 @@ aarch64_emit_load_store (uint32_t *buf, uint32_t size,
op = ENCODE (1, 1, 24);
return aarch64_emit_insn (buf, opcode | ENCODE (size, 2, 30) | op
- | ENCODE (operand.index >> 3, 12, 10)
- | ENCODE (rn.num, 5, 5)
- | ENCODE (rt.num, 5, 0));
+ | ENCODE (operand.index >> 3, 12, 10)
+ | ENCODE (rn.num, 5, 5)
+ | ENCODE (rt.num, 5, 0));
}
case MEMORY_OPERAND_POSTINDEX:
{
@@ -346,9 +344,10 @@ aarch64_emit_load_store (uint32_t *buf, uint32_t size,
op = ENCODE (0, 1, 24);
return aarch64_emit_insn (buf, opcode | ENCODE (size, 2, 30) | op
- | post_index | ENCODE (operand.index, 9, 12)
- | ENCODE (rn.num, 5, 5)
- | ENCODE (rt.num, 5, 0));
+ | post_index
+ | ENCODE (operand.index, 9, 12)
+ | ENCODE (rn.num, 5, 5)
+ | ENCODE (rt.num, 5, 0));
}
case MEMORY_OPERAND_PREINDEX:
{
@@ -357,9 +356,10 @@ aarch64_emit_load_store (uint32_t *buf, uint32_t size,
op = ENCODE (0, 1, 24);
return aarch64_emit_insn (buf, opcode | ENCODE (size, 2, 30) | op
- | pre_index | ENCODE (operand.index, 9, 12)
- | ENCODE (rn.num, 5, 5)
- | ENCODE (rt.num, 5, 0));
+ | pre_index
+ | ENCODE (operand.index, 9, 12)
+ | ENCODE (rn.num, 5, 5)
+ | ENCODE (rt.num, 5, 0));
}
default:
return 0;
diff --git a/gdb/arch/aarch64-insn.h b/gdb/arch/aarch64-insn.h
index 7560da9..e80bcfd 100644
--- a/gdb/arch/aarch64-insn.h
+++ b/gdb/arch/aarch64-insn.h
@@ -32,15 +32,15 @@ extern bool aarch64_debug;
#define submask(x) ((1L << ((x) + 1)) - 1)
/* Extract the bitfield from OBJ starting at bit ST and ending at bit FN. */
-#define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
+#define bits(obj, st, fn) (((obj) >> (st)) & submask ((fn) - (st)))
/* Extract bit ST from OBJ. */
-#define bit(obj,st) (((obj) >> (st)) & 1)
+#define bit(obj, st) (((obj) >> (st)) & 1)
/* Extract the signed bitfield from OBJ starting at bit ST and ending at
bit FN. The result is sign-extended. */
-#define sbits(obj,st,fn) \
- ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
+#define sbits(obj, st, fn) \
+ ((long) (bits (obj, st, fn) | ((long) bit (obj, fn) * ~submask (fn - st))))
/* Prologue analyzer helper macros. */
@@ -59,80 +59,80 @@ enum aarch64_opcodes
/* CBNZ s011 0101 iiii iiii iiii iiii iiir rrrr */
/* TBZ b011 0110 bbbb biii iiii iiii iiir rrrr */
/* TBNZ b011 0111 bbbb biii iiii iiii iiir rrrr */
- B = 0x14000000,
- BL = 0x80000000 | B,
- BCOND = 0x40000000 | B,
- CBZ = 0x20000000 | B,
- CBNZ = 0x21000000 | B,
- TBZ = 0x36000000 | B,
- TBNZ = 0x37000000 | B,
+ B = 0x14000000,
+ BL = 0x80000000 | B,
+ BCOND = 0x40000000 | B,
+ CBZ = 0x20000000 | B,
+ CBNZ = 0x21000000 | B,
+ TBZ = 0x36000000 | B,
+ TBNZ = 0x37000000 | B,
/* BR 1101 0110 0001 1111 0000 00rr rrr0 0000 */
/* BLR 1101 0110 0011 1111 0000 00rr rrr0 0000 */
- BR = 0xd61f0000,
- BLR = 0xd63f0000,
+ BR = 0xd61f0000,
+ BLR = 0xd63f0000,
/* RET 1101 0110 0101 1111 0000 00rr rrr0 0000 */
- RET = 0xd65f0000,
+ RET = 0xd65f0000,
/* STP s010 100o o0ii iiii irrr rrrr rrrr rrrr */
/* LDP s010 100o o1ii iiii irrr rrrr rrrr rrrr */
/* STP (SIMD&VFP) ss10 110o o0ii iiii irrr rrrr rrrr rrrr */
/* LDP (SIMD&VFP) ss10 110o o1ii iiii irrr rrrr rrrr rrrr */
- STP = 0x28000000,
- LDP = 0x28400000,
- STP_SIMD_VFP = 0x04000000 | STP,
- LDP_SIMD_VFP = 0x04000000 | LDP,
+ STP = 0x28000000,
+ LDP = 0x28400000,
+ STP_SIMD_VFP = 0x04000000 | STP,
+ LDP_SIMD_VFP = 0x04000000 | LDP,
/* STR ss11 100o 00xi iiii iiii xxrr rrrr rrrr */
/* LDR ss11 100o 01xi iiii iiii xxrr rrrr rrrr */
/* LDRSW 1011 100o 10xi iiii iiii xxrr rrrr rrrr */
- STR = 0x38000000,
- LDR = 0x00400000 | STR,
- LDRSW = 0x80800000 | STR,
+ STR = 0x38000000,
+ LDR = 0x00400000 | STR,
+ LDRSW = 0x80800000 | STR,
/* LDAXR ss00 1000 0101 1111 1111 11rr rrrr rrrr */
- LDAXR = 0x085ffc00,
+ LDAXR = 0x085ffc00,
/* STXR ss00 1000 000r rrrr 0111 11rr rrrr rrrr */
- STXR = 0x08007c00,
+ STXR = 0x08007c00,
/* STLR ss00 1000 1001 1111 1111 11rr rrrr rrrr */
- STLR = 0x089ffc00,
+ STLR = 0x089ffc00,
/* MOV s101 0010 1xxi iiii iiii iiii iiir rrrr */
/* MOVK s111 0010 1xxi iiii iiii iiii iiir rrrr */
- MOV = 0x52800000,
- MOVK = 0x20000000 | MOV,
+ MOV = 0x52800000,
+ MOVK = 0x20000000 | MOV,
/* ADD s00o ooo1 xxxx xxxx xxxx xxxx xxxx xxxx */
/* SUB s10o ooo1 xxxx xxxx xxxx xxxx xxxx xxxx */
/* SUBS s11o ooo1 xxxx xxxx xxxx xxxx xxxx xxxx */
- ADD = 0x01000000,
- SUB = 0x40000000 | ADD,
- SUBS = 0x20000000 | SUB,
+ ADD = 0x01000000,
+ SUB = 0x40000000 | ADD,
+ SUBS = 0x20000000 | SUB,
/* AND s000 1010 xx0x xxxx xxxx xxxx xxxx xxxx */
/* ORR s010 1010 xx0x xxxx xxxx xxxx xxxx xxxx */
/* ORN s010 1010 xx1x xxxx xxxx xxxx xxxx xxxx */
/* EOR s100 1010 xx0x xxxx xxxx xxxx xxxx xxxx */
- AND = 0x0a000000,
- ORR = 0x20000000 | AND,
- ORN = 0x00200000 | ORR,
- EOR = 0x40000000 | AND,
+ AND = 0x0a000000,
+ ORR = 0x20000000 | AND,
+ ORN = 0x00200000 | ORR,
+ EOR = 0x40000000 | AND,
/* LSLV s001 1010 110r rrrr 0010 00rr rrrr rrrr */
/* LSRV s001 1010 110r rrrr 0010 01rr rrrr rrrr */
/* ASRV s001 1010 110r rrrr 0010 10rr rrrr rrrr */
- LSLV = 0x1ac02000,
- LSRV = 0x00000400 | LSLV,
- ASRV = 0x00000800 | LSLV,
+ LSLV = 0x1ac02000,
+ LSRV = 0x00000400 | LSLV,
+ ASRV = 0x00000800 | LSLV,
/* SBFM s001 0011 0nii iiii iiii iirr rrrr rrrr */
- SBFM = 0x13000000,
+ SBFM = 0x13000000,
/* UBFM s101 0011 0nii iiii iiii iirr rrrr rrrr */
- UBFM = 0x40000000 | SBFM,
+ UBFM = 0x40000000 | SBFM,
/* CSINC s001 1010 100r rrrr cccc 01rr rrrr rrrr */
- CSINC = 0x9a800400,
+ CSINC = 0x9a800400,
/* MUL s001 1011 000r rrrr 0111 11rr rrrr rrrr */
- MUL = 0x1b007c00,
+ MUL = 0x1b007c00,
/* MSR (register) 1101 0101 0001 oooo oooo oooo ooor rrrr */
/* MRS 1101 0101 0011 oooo oooo oooo ooor rrrr */
- MSR = 0xd5100000,
- MRS = 0x00200000 | MSR,
+ MSR = 0xd5100000,
+ MRS = 0x00200000 | MSR,
/* HINT 1101 0101 0000 0011 0010 oooo ooo1 1111 */
- HINT = 0xd503201f,
- SEVL = (5 << 5) | HINT,
- WFE = (2 << 5) | HINT,
- NOP = (0 << 5) | HINT,
+ HINT = 0xd503201f,
+ SEVL = (5 << 5) | HINT,
+ WFE = (2 << 5) | HINT,
+ NOP = (0 << 5) | HINT,
};
/* List of useful masks. */
@@ -191,8 +191,8 @@ int aarch64_decode_b (CORE_ADDR addr, uint32_t insn, int *is_bl,
int aarch64_decode_bcond (CORE_ADDR addr, uint32_t insn, unsigned *cond,
int32_t *offset);
-int aarch64_decode_cb (CORE_ADDR addr, uint32_t insn, int *is64,
- int *is_cbnz, unsigned *rn, int32_t *offset);
+int aarch64_decode_cb (CORE_ADDR addr, uint32_t insn, int *is64, int *is_cbnz,
+ unsigned *rn, int32_t *offset);
int aarch64_decode_tb (CORE_ADDR addr, uint32_t insn, int *is_tbnz,
unsigned *bit, unsigned *rt, int32_t *imm);
@@ -221,18 +221,16 @@ struct aarch64_insn_visitor
struct aarch64_insn_data *data);
/* Visit instruction CBZ/CBNZ Rn, OFFSET. */
- void (*cb) (const int32_t offset, const int is_cbnz,
- const unsigned rn, int is64,
- struct aarch64_insn_data *data);
+ void (*cb) (const int32_t offset, const int is_cbnz, const unsigned rn,
+ int is64, struct aarch64_insn_data *data);
/* Visit instruction TBZ/TBNZ Rt, #BIT, OFFSET. */
- void (*tb) (const int32_t offset, int is_tbnz,
- const unsigned rt, unsigned bit,
- struct aarch64_insn_data *data);
+ void (*tb) (const int32_t offset, int is_tbnz, const unsigned rt,
+ unsigned bit, struct aarch64_insn_data *data);
/* Visit instruction ADR/ADRP Rd, OFFSET. */
- void (*adr) (const int32_t offset, const unsigned rd,
- const int is_adrp, struct aarch64_insn_data *data);
+ void (*adr) (const int32_t offset, const unsigned rd, const int is_adrp,
+ struct aarch64_insn_data *data);
/* Visit instruction LDR/LDRSW Rt, OFFSET. */
void (*ldr_literal) (const int32_t offset, const int is_sw,
@@ -247,7 +245,7 @@ void aarch64_relocate_instruction (uint32_t insn,
const struct aarch64_insn_visitor *visitor,
struct aarch64_insn_data *data);
-#define can_encode_int32(val, bits) \
+#define can_encode_int32(val, bits) \
(((val) >> (bits)) == 0 || ((val) >> (bits)) == -1)
/* Write a B or BL instruction into *BUF.
@@ -272,10 +270,9 @@ void aarch64_relocate_instruction (uint32_t insn,
byte-addressed but should be 4 bytes aligned. It has a limited range of
+/- 1MB (19 bits << 2). */
-#define emit_bcond(buf, cond, offset) \
- aarch64_emit_insn (buf, \
- BCOND | ENCODE ((offset) >> 2, 19, 5) \
- | ENCODE ((cond), 4, 0))
+#define emit_bcond(buf, cond, offset) \
+ aarch64_emit_insn (buf, BCOND | ENCODE ((offset) >> 2, 19, 5) \
+ | ENCODE ((cond), 4, 0))
/* Write a CBZ or CBNZ instruction into *BUF.
@@ -288,12 +285,11 @@ void aarch64_relocate_instruction (uint32_t insn,
byte-addressed but should be 4 bytes aligned. It has a limited range of
+/- 1MB (19 bits << 2). */
-#define emit_cb(buf, is_cbnz, rt, offset) \
- aarch64_emit_insn (buf, \
- ((is_cbnz) ? CBNZ : CBZ) \
- | ENCODE (rt.is64, 1, 31) /* sf */ \
- | ENCODE (offset >> 2, 19, 5) /* imm19 */ \
- | ENCODE (rt.num, 5, 0))
+#define emit_cb(buf, is_cbnz, rt, offset) \
+ aarch64_emit_insn (buf, ((is_cbnz) ? CBNZ : CBZ) \
+ | ENCODE (rt.is64, 1, 31) /* sf */ \
+ | ENCODE (offset >> 2, 19, 5) /* imm19 */ \
+ | ENCODE (rt.num, 5, 0))
/* Write a LDR instruction into *BUF.
@@ -320,10 +316,9 @@ void aarch64_relocate_instruction (uint32_t insn,
OFFSET is the immediate to add to the base address. It is limited to
0 .. 16380 range (12 bits << 2). */
-#define emit_ldrsw(buf, rt, rn, operand) \
+#define emit_ldrsw(buf, rt, rn, operand) \
aarch64_emit_load_store (buf, 3, LDRSW, rt, rn, operand)
-
/* Write a TBZ or TBNZ instruction into *BUF.
TBZ rt, #bit, #offset
@@ -336,13 +331,12 @@ void aarch64_relocate_instruction (uint32_t insn,
byte-addressed but should be 4 bytes aligned. It has a limited range of
+/- 32KB (14 bits << 2). */
-#define emit_tb(buf, is_tbnz, bit, rt, offset) \
- aarch64_emit_insn (buf, \
- ((is_tbnz) ? TBNZ: TBZ) \
- | ENCODE (bit >> 5, 1, 31) /* b5 */ \
- | ENCODE (bit, 5, 19) /* b40 */ \
- | ENCODE (offset >> 2, 14, 5) /* imm14 */ \
- | ENCODE (rt.num, 5, 0))
+#define emit_tb(buf, is_tbnz, bit, rt, offset) \
+ aarch64_emit_insn (buf, ((is_tbnz) ? TBNZ : TBZ) \
+ | ENCODE (bit >> 5, 1, 31) /* b5 */ \
+ | ENCODE (bit, 5, 19) /* b40 */ \
+ | ENCODE (offset >> 2, 14, 5) /* imm14 */ \
+ | ENCODE (rt.num, 5, 0))
/* Write a NOP instruction into *BUF. */
diff --git a/gdb/arch/aarch64-mte-linux.h b/gdb/arch/aarch64-mte-linux.h
index e862b0b..38a2dbc 100644
--- a/gdb/arch/aarch64-mte-linux.h
+++ b/gdb/arch/aarch64-mte-linux.h
@@ -24,7 +24,7 @@
/* Feature check for Memory Tagging Extension. */
#ifndef HWCAP2_MTE
-#define HWCAP2_MTE (1 << 18)
+#define HWCAP2_MTE (1 << 18)
#endif
/* The MTE regset consists of a single 64-bit register. */
@@ -38,8 +38,8 @@
/* Memory tagging definitions. */
#ifndef SEGV_MTEAERR
-# define SEGV_MTEAERR 8
-# define SEGV_MTESERR 9
+#define SEGV_MTEAERR 8
+#define SEGV_MTESERR 9
#endif
/* Memory tag types for AArch64. */
diff --git a/gdb/arch/aarch64.h b/gdb/arch/aarch64.h
index de4461e..8dc767b 100644
--- a/gdb/arch/aarch64.h
+++ b/gdb/arch/aarch64.h
@@ -38,38 +38,37 @@ struct aarch64_features
uint8_t tls = 0;
};
-inline bool operator==(const aarch64_features &lhs, const aarch64_features &rhs)
+inline bool
+operator== (const aarch64_features &lhs, const aarch64_features &rhs)
{
- return lhs.vq == rhs.vq
- && lhs.pauth == rhs.pauth
- && lhs.mte == rhs.mte
- && lhs.tls == rhs.tls;
+ return lhs.vq == rhs.vq && lhs.pauth == rhs.pauth && lhs.mte == rhs.mte
+ && lhs.tls == rhs.tls;
}
namespace std
{
- template<>
- struct hash<aarch64_features>
+template<>
+struct hash<aarch64_features>
+{
+ std::size_t operator() (const aarch64_features &features) const noexcept
{
- std::size_t operator()(const aarch64_features &features) const noexcept
- {
- std::size_t h;
-
- h = features.vq;
- h = h << 1 | features.pauth;
- h = h << 1 | features.mte;
- /* Shift by two bits for now. We may need to increase this in the future
+ std::size_t h;
+
+ h = features.vq;
+ h = h << 1 | features.pauth;
+ h = h << 1 | features.mte;
+ /* Shift by two bits for now. We may need to increase this in the future
if more TLS registers get added. */
- h = h << 2 | features.tls;
- return h;
- }
- };
-}
+ h = h << 2 | features.tls;
+ return h;
+ }
+};
+} // namespace std
/* Create the aarch64 target description. */
target_desc *
- aarch64_create_target_description (const aarch64_features &features);
+aarch64_create_target_description (const aarch64_features &features);
/* Given a pointer value POINTER and a MASK of non-address bits, remove the
non-address bits from the pointer and sign-extend the result if required.
@@ -87,23 +86,23 @@ aarch64_mask_from_pac_registers (const CORE_ADDR cmask, const CORE_ADDR dmask);
registers become pseudo registers. */
enum aarch64_regnum
{
- AARCH64_X0_REGNUM, /* First integer register. */
- AARCH64_FP_REGNUM = AARCH64_X0_REGNUM + 29, /* Frame register, if used. */
- AARCH64_LR_REGNUM = AARCH64_X0_REGNUM + 30, /* Return address. */
- AARCH64_SP_REGNUM, /* Stack pointer. */
- AARCH64_PC_REGNUM, /* Program counter. */
- AARCH64_CPSR_REGNUM, /* Current Program Status Register. */
- AARCH64_V0_REGNUM, /* First fp/vec register. */
- AARCH64_V31_REGNUM = AARCH64_V0_REGNUM + 31, /* Last fp/vec register. */
- AARCH64_SVE_Z0_REGNUM = AARCH64_V0_REGNUM, /* First SVE Z register. */
- AARCH64_SVE_Z31_REGNUM = AARCH64_V31_REGNUM, /* Last SVE Z register. */
- AARCH64_FPSR_REGNUM, /* Floating Point Status Register. */
- AARCH64_FPCR_REGNUM, /* Floating Point Control Register. */
- AARCH64_SVE_P0_REGNUM, /* First SVE predicate register. */
- AARCH64_SVE_P15_REGNUM = AARCH64_SVE_P0_REGNUM + 15, /* Last SVE predicate
+ AARCH64_X0_REGNUM, /* First integer register. */
+ AARCH64_FP_REGNUM = AARCH64_X0_REGNUM + 29, /* Frame register, if used. */
+ AARCH64_LR_REGNUM = AARCH64_X0_REGNUM + 30, /* Return address. */
+ AARCH64_SP_REGNUM, /* Stack pointer. */
+ AARCH64_PC_REGNUM, /* Program counter. */
+ AARCH64_CPSR_REGNUM, /* Current Program Status Register. */
+ AARCH64_V0_REGNUM, /* First fp/vec register. */
+ AARCH64_V31_REGNUM = AARCH64_V0_REGNUM + 31, /* Last fp/vec register. */
+ AARCH64_SVE_Z0_REGNUM = AARCH64_V0_REGNUM, /* First SVE Z register. */
+ AARCH64_SVE_Z31_REGNUM = AARCH64_V31_REGNUM, /* Last SVE Z register. */
+ AARCH64_FPSR_REGNUM, /* Floating Point Status Register. */
+ AARCH64_FPCR_REGNUM, /* Floating Point Control Register. */
+ AARCH64_SVE_P0_REGNUM, /* First SVE predicate register. */
+ AARCH64_SVE_P15_REGNUM = AARCH64_SVE_P0_REGNUM + 15, /* Last SVE predicate
register. */
- AARCH64_SVE_FFR_REGNUM, /* SVE First Fault Register. */
- AARCH64_SVE_VG_REGNUM, /* SVE Vector Granule. */
+ AARCH64_SVE_FFR_REGNUM, /* SVE First Fault Register. */
+ AARCH64_SVE_VG_REGNUM, /* SVE Vector Granule. */
/* Other useful registers. */
AARCH64_LAST_X_ARG_REGNUM = AARCH64_X0_REGNUM + 7,
@@ -113,14 +112,14 @@ enum aarch64_regnum
/* Sizes of various AArch64 registers. */
#define AARCH64_TLS_REGISTER_SIZE 8
-#define V_REGISTER_SIZE 16
+#define V_REGISTER_SIZE 16
/* PAC-related constants. */
/* Bit 55 is used to select between a kernel-space and user-space address. */
-#define VA_RANGE_SELECT_BIT_MASK 0x80000000000000ULL
+#define VA_RANGE_SELECT_BIT_MASK 0x80000000000000ULL
/* Mask with 1's in bits 55~63, used to remove the top byte of pointers
(Top Byte Ignore). */
-#define AARCH64_TOP_BITS_MASK 0xff80000000000000ULL
+#define AARCH64_TOP_BITS_MASK 0xff80000000000000ULL
/* Pseudo register base numbers. */
#define AARCH64_Q0_REGNUM 0
@@ -150,19 +149,18 @@ enum aarch64_regnum
VG : Vector Granule.
The number of 64bit chunks in an SVE Z register. */
-#define sve_vg_from_vl(vl) ((vl) / 8)
-#define sve_vl_from_vg(vg) ((vg) * 8)
+#define sve_vg_from_vl(vl) ((vl) / 8)
+#define sve_vl_from_vg(vg) ((vg) *8)
#ifndef sve_vq_from_vl
-#define sve_vq_from_vl(vl) ((vl) / 0x10)
+#define sve_vq_from_vl(vl) ((vl) / 0x10)
#endif
#ifndef sve_vl_from_vq
-#define sve_vl_from_vq(vq) ((vq) * 0x10)
+#define sve_vl_from_vq(vq) ((vq) *0x10)
#endif
-#define sve_vq_from_vg(vg) (sve_vq_from_vl (sve_vl_from_vg (vg)))
-#define sve_vg_from_vq(vq) (sve_vg_from_vl (sve_vl_from_vq (vq)))
-
+#define sve_vq_from_vg(vg) (sve_vq_from_vl (sve_vl_from_vg (vg)))
+#define sve_vg_from_vq(vq) (sve_vg_from_vl (sve_vl_from_vq (vq)))
/* Maximum supported VQ value. Increase if required. */
-#define AARCH64_MAX_SVE_VQ 16
+#define AARCH64_MAX_SVE_VQ 16
#endif /* ARCH_AARCH64_H */
diff --git a/gdb/arch/arc.c b/gdb/arch/arc.c
index 56e46d0..cc2c991 100644
--- a/gdb/arch/arc.c
+++ b/gdb/arch/arc.c
@@ -15,7 +15,6 @@
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
-
#include "gdbsupport/common-defs.h"
#include "arc.h"
#include <stdlib.h>
@@ -46,14 +45,14 @@ arc_create_target_description (const struct arc_arch_features &features)
/* Architecture names here must match the ones in
ARCH_INFO_STRUCT in bfd/cpu-arc.c. */
if (features.isa == ARC_ISA_ARCV1 && features.reg_size == 4)
- arch_name = "arc:ARC700";
+ arch_name = "arc:ARC700";
else if (features.isa == ARC_ISA_ARCV2 && features.reg_size == 4)
- arch_name = "arc:ARCv2";
+ arch_name = "arc:ARCv2";
else
{
- std::string msg = string_printf
- ("Cannot determine architecture: ISA=%d; bitness=%d",
- features.isa, 8 * features.reg_size);
+ std::string msg
+ = string_printf ("Cannot determine architecture: ISA=%d; bitness=%d",
+ features.isa, 8 * features.reg_size);
gdb_assert_not_reached ("%s", msg.c_str ());
}
@@ -73,8 +72,9 @@ arc_create_target_description (const struct arc_arch_features &features)
regnum = create_feature_arc_v2_aux (tdesc.get (), regnum);
break;
default:
- std::string msg = string_printf
- ("Cannot choose target description XML: %d", features.isa);
+ std::string msg
+ = string_printf ("Cannot choose target description XML: %d",
+ features.isa);
gdb_assert_not_reached ("%s", msg.c_str ());
}
@@ -86,8 +86,7 @@ arc_create_target_description (const struct arc_arch_features &features)
/* Wrapper used by std::unordered_map to generate hash for features set. */
struct arc_arch_features_hasher
{
- std::size_t
- operator() (const arc_arch_features &features) const noexcept
+ std::size_t operator() (const arc_arch_features &features) const noexcept
{
return features.hash ();
}
@@ -95,9 +94,9 @@ struct arc_arch_features_hasher
/* Cache of previously created target descriptions, indexed by the hash
of the features set used to create them. */
-static std::unordered_map<arc_arch_features,
- const target_desc_up,
- arc_arch_features_hasher> arc_tdesc_cache;
+static std::unordered_map<arc_arch_features, const target_desc_up,
+ arc_arch_features_hasher>
+ arc_tdesc_cache;
/* See arch/arc.h. */
@@ -113,7 +112,6 @@ arc_lookup_target_description (const struct arc_arch_features &features)
target_desc_up tdesc = arc_create_target_description (features);
-
/* Add to the cache, and return a pointer borrowed from the
target_desc_up. This is safe as the cache (and the pointers
contained within it) are not deleted until GDB exits. */
diff --git a/gdb/arch/arc.h b/gdb/arch/arc.h
index 38dbd0f..dd75a6a 100644
--- a/gdb/arch/arc.h
+++ b/gdb/arch/arc.h
@@ -23,15 +23,17 @@
/* Supported ARC ISAs. */
enum arc_isa
{
- ARC_ISA_ARCV1 = 1, /* a.k.a. ARCompact (ARC600, ARC700) */
- ARC_ISA_ARCV2 /* such as ARC EM and ARC HS */
+ ARC_ISA_ARCV1 = 1, /* a.k.a. ARCompact (ARC600, ARC700) */
+ ARC_ISA_ARCV2 /* such as ARC EM and ARC HS */
};
struct arc_arch_features
{
arc_arch_features (int reg_size, arc_isa isa)
- : reg_size (reg_size), isa (isa)
- {}
+ : reg_size (reg_size),
+ isa (isa)
+ {
+ }
/* Register size in bytes. Possible values are 4, and 8. A 0 indicates
an uninitialised value. */
@@ -70,18 +72,17 @@ struct arc_arch_features
The only external client of this must be the gdbserver which manipulates
the returned data. */
-target_desc_up arc_create_target_description
- (const struct arc_arch_features &features);
+target_desc_up
+arc_create_target_description (const struct arc_arch_features &features);
#else
/* Lookup the cache for a target description matching the FEATURES.
If nothing is found, then create one and return it. */
-const target_desc *arc_lookup_target_description
- (const struct arc_arch_features &features);
+const target_desc *
+arc_lookup_target_description (const struct arc_arch_features &features);
#endif /* GDBSERVER */
-
#endif /* ARCH_ARC_H */
diff --git a/gdb/arch/arm-get-next-pcs.c b/gdb/arch/arm-get-next-pcs.c
index dcbb5a5..b548570 100644
--- a/gdb/arch/arm-get-next-pcs.c
+++ b/gdb/arch/arm-get-next-pcs.c
@@ -28,10 +28,8 @@
void
arm_get_next_pcs_ctor (struct arm_get_next_pcs *self,
- struct arm_get_next_pcs_ops *ops,
- int byte_order,
- int byte_order_for_code,
- int has_thumb2_breakpoint,
+ struct arm_get_next_pcs_ops *ops, int byte_order,
+ int byte_order_for_code, int has_thumb2_breakpoint,
struct regcache *regcache)
{
self->ops = ops;
@@ -50,7 +48,7 @@ static std::vector<CORE_ADDR>
thumb_deal_with_atomic_sequence_raw (struct arm_get_next_pcs *self)
{
int byte_order_for_code = self->byte_order_for_code;
- CORE_ADDR breaks[2] = {CORE_ADDR_MAX, CORE_ADDR_MAX};
+ CORE_ADDR breaks[2] = { CORE_ADDR_MAX, CORE_ADDR_MAX };
CORE_ADDR pc = regcache_read_pc (self->regcache);
CORE_ADDR loc = pc;
unsigned short insn1, insn2;
@@ -84,7 +82,7 @@ thumb_deal_with_atomic_sequence_raw (struct arm_get_next_pcs *self)
instructions. */
for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
{
- insn1 = self->ops->read_mem_uint (loc, 2,byte_order_for_code);
+ insn1 = self->ops->read_mem_uint (loc, 2, byte_order_for_code);
loc += 2;
if (thumb_insn_size (insn1) != 4)
@@ -118,8 +116,7 @@ thumb_deal_with_atomic_sequence_raw (struct arm_get_next_pcs *self)
/* Assume that there is at most one conditional branch in the
atomic sequence. If a conditional branch is found, put a
breakpoint in its destination address. */
- if ((insn1 & 0xf800) == 0xf000
- && (insn2 & 0xd000) == 0x8000
+ if ((insn1 & 0xf800) == 0xf000 && (insn2 & 0xd000) == 0x8000
&& (insn1 & 0x0380) != 0x0380)
{
int sign, j1, j2, imm1, imm2;
@@ -166,8 +163,7 @@ thumb_deal_with_atomic_sequence_raw (struct arm_get_next_pcs *self)
/* Check for duplicated breakpoints. Check also for a breakpoint
placed (branch instruction's destination) anywhere in sequence. */
if (last_breakpoint
- && (breaks[1] == breaks[0]
- || (breaks[1] >= pc && breaks[1] < loc)))
+ && (breaks[1] == breaks[0] || (breaks[1] >= pc && breaks[1] < loc)))
last_breakpoint = 0;
std::vector<CORE_ADDR> next_pcs;
@@ -188,7 +184,7 @@ static std::vector<CORE_ADDR>
arm_deal_with_atomic_sequence_raw (struct arm_get_next_pcs *self)
{
int byte_order_for_code = self->byte_order_for_code;
- CORE_ADDR breaks[2] = {CORE_ADDR_MAX, CORE_ADDR_MAX};
+ CORE_ADDR breaks[2] = { CORE_ADDR_MAX, CORE_ADDR_MAX };
CORE_ADDR pc = regcache_read_pc (self->regcache);
CORE_ADDR loc = pc;
unsigned int insn;
@@ -248,8 +244,7 @@ arm_deal_with_atomic_sequence_raw (struct arm_get_next_pcs *self)
/* Check for duplicated breakpoints. Check also for a breakpoint
placed (branch instruction's destination) anywhere in sequence. */
if (last_breakpoint
- && (breaks[1] == breaks[0]
- || (breaks[1] >= pc && breaks[1] < loc)))
+ && (breaks[1] == breaks[0] || (breaks[1] >= pc && breaks[1] < loc)))
last_breakpoint = 0;
std::vector<CORE_ADDR> next_pcs;
@@ -269,9 +264,9 @@ thumb_get_next_pcs_raw (struct arm_get_next_pcs *self)
int byte_order = self->byte_order;
int byte_order_for_code = self->byte_order_for_code;
CORE_ADDR pc = regcache_read_pc (self->regcache);
- unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */
+ unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */
unsigned short inst1;
- CORE_ADDR nextpc = pc + 2; /* Default is next instruction. */
+ CORE_ADDR nextpc = pc + 2; /* Default is next instruction. */
ULONGEST status, itstate;
struct regcache *regcache = self->regcache;
std::vector<CORE_ADDR> next_pcs;
@@ -310,9 +305,9 @@ thumb_get_next_pcs_raw (struct arm_get_next_pcs *self)
itstate = inst1 & 0x00ff;
pc += thumb_insn_size (inst1);
- while (itstate != 0 && ! condition_true (itstate >> 4, status))
+ while (itstate != 0 && !condition_true (itstate >> 4, status))
{
- inst1 = self->ops->read_mem_uint (pc, 2,byte_order_for_code);
+ inst1 = self->ops->read_mem_uint (pc, 2, byte_order_for_code);
pc += thumb_insn_size (inst1);
itstate = thumb_advance_itstate (itstate);
}
@@ -323,15 +318,16 @@ thumb_get_next_pcs_raw (struct arm_get_next_pcs *self)
else if (itstate != 0)
{
/* We are in a conditional block. Check the condition. */
- if (! condition_true (itstate >> 4, status))
+ if (!condition_true (itstate >> 4, status))
{
/* Advance to the next executed instruction. */
pc += thumb_insn_size (inst1);
itstate = thumb_advance_itstate (itstate);
- while (itstate != 0 && ! condition_true (itstate >> 4, status))
+ while (itstate != 0 && !condition_true (itstate >> 4, status))
{
- inst1 = self->ops->read_mem_uint (pc, 2, byte_order_for_code);
+ inst1
+ = self->ops->read_mem_uint (pc, 2, byte_order_for_code);
pc += thumb_insn_size (inst1);
itstate = thumb_advance_itstate (itstate);
@@ -374,7 +370,8 @@ thumb_get_next_pcs_raw (struct arm_get_next_pcs *self)
the instruction after the IT block. */
do
{
- inst1 = self->ops->read_mem_uint (pc, 2, byte_order_for_code);
+ inst1
+ = self->ops->read_mem_uint (pc, 2, byte_order_for_code);
pc += thumb_insn_size (inst1);
itstate = thumb_advance_itstate (itstate);
}
@@ -391,7 +388,7 @@ thumb_get_next_pcs_raw (struct arm_get_next_pcs *self)
/* We are in a conditional block. Check the condition. */
int cond = itstate >> 4;
- if (! condition_true (cond, status))
+ if (!condition_true (cond, status))
{
/* Advance to the next instruction. All the 32-bit
instructions share a common prefix. */
@@ -403,7 +400,7 @@ thumb_get_next_pcs_raw (struct arm_get_next_pcs *self)
/* Otherwise, handle the instruction normally. */
}
- if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */
+ if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */
{
CORE_ADDR sp;
@@ -414,17 +411,17 @@ thumb_get_next_pcs_raw (struct arm_get_next_pcs *self)
sp = regcache_raw_get_unsigned (regcache, ARM_SP_REGNUM);
nextpc = self->ops->read_mem_uint (sp + offset, 4, byte_order);
}
- else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */
+ else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */
{
unsigned long cond = bits (inst1, 8, 11);
- if (cond == 0x0f) /* 0x0f = SWI */
+ if (cond == 0x0f) /* 0x0f = SWI */
{
nextpc = self->ops->syscall_next_pc (self);
}
else if (cond != 0x0f && condition_true (cond, status))
nextpc = pc_val + (sbits (inst1, 0, 7) << 1);
}
- else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */
+ else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */
{
nextpc = pc_val + (sbits (inst1, 0, 10) << 1);
}
@@ -522,7 +519,7 @@ thumb_get_next_pcs_raw (struct arm_get_next_pcs *self)
if (load_pc)
{
CORE_ADDR addr = regcache_raw_get_unsigned (regcache, rn);
- nextpc = self->ops->read_mem_uint (addr + offset, 4, byte_order);
+ nextpc = self->ops->read_mem_uint (addr + offset, 4, byte_order);
}
}
else if ((inst1 & 0xffef) == 0xea4f && (inst2 & 0xfff0) == 0x0f00)
@@ -569,8 +566,7 @@ thumb_get_next_pcs_raw (struct arm_get_next_pcs *self)
load_pc = 0;
if (load_pc)
- nextpc
- = self->ops->read_mem_uint (base, 4, byte_order);
+ nextpc = self->ops->read_mem_uint (base, 4, byte_order);
}
else if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf000)
{
@@ -579,12 +575,13 @@ thumb_get_next_pcs_raw (struct arm_get_next_pcs *self)
tbl_reg = bits (inst1, 0, 3);
if (tbl_reg == 0x0f)
- table = pc + 4; /* Regcache copy of PC isn't right yet. */
+ table = pc + 4; /* Regcache copy of PC isn't right yet. */
else
table = regcache_raw_get_unsigned (regcache, tbl_reg);
offset = regcache_raw_get_unsigned (regcache, bits (inst2, 0, 3));
- length = 2 * self->ops->read_mem_uint (table + offset, 1, byte_order);
+ length
+ = 2 * self->ops->read_mem_uint (table + offset, 1, byte_order);
nextpc = pc_val + length;
}
else if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf010)
@@ -594,23 +591,25 @@ thumb_get_next_pcs_raw (struct arm_get_next_pcs *self)
tbl_reg = bits (inst1, 0, 3);
if (tbl_reg == 0x0f)
- table = pc + 4; /* Regcache copy of PC isn't right yet. */
+ table = pc + 4; /* Regcache copy of PC isn't right yet. */
else
table = regcache_raw_get_unsigned (regcache, tbl_reg);
- offset = 2 * regcache_raw_get_unsigned (regcache, bits (inst2, 0, 3));
- length = 2 * self->ops->read_mem_uint (table + offset, 2, byte_order);
+ offset
+ = 2 * regcache_raw_get_unsigned (regcache, bits (inst2, 0, 3));
+ length
+ = 2 * self->ops->read_mem_uint (table + offset, 2, byte_order);
nextpc = pc_val + length;
}
}
- else if ((inst1 & 0xff00) == 0x4700) /* bx REG, blx REG */
+ else if ((inst1 & 0xff00) == 0x4700) /* bx REG, blx REG */
{
if (bits (inst1, 3, 6) == 0x0f)
nextpc = UNMAKE_THUMB_ADDR (pc_val);
else
nextpc = regcache_raw_get_unsigned (regcache, bits (inst1, 3, 6));
}
- else if ((inst1 & 0xff87) == 0x4687) /* mov pc, REG */
+ else if ((inst1 & 0xff87) == 0x4687) /* mov pc, REG */
{
if (bits (inst1, 3, 6) == 0x0f)
nextpc = pc_val;
@@ -661,7 +660,7 @@ arm_get_next_pcs_raw (struct arm_get_next_pcs *self)
this_instr = self->ops->read_mem_uint (pc, 4, byte_order_for_code);
status = regcache_raw_get_unsigned (regcache, ARM_PS_REGNUM);
- nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */
+ nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */
if (bits (this_instr, 28, 31) == INST_NV)
switch (bits (this_instr, 24, 27))
@@ -680,7 +679,7 @@ arm_get_next_pcs_raw (struct arm_get_next_pcs *self)
case 0xe:
/* Coprocessor register transfer. */
if (bits (this_instr, 12, 15) == 15)
- error (_("Invalid update to pc in instruction"));
+ error (_ ("Invalid update to pc in instruction"));
break;
}
else if (condition_true (bits (this_instr, 28, 31), status))
@@ -688,7 +687,7 @@ arm_get_next_pcs_raw (struct arm_get_next_pcs *self)
switch (bits (this_instr, 24, 27))
{
case 0x0:
- case 0x1: /* data processing */
+ case 0x1: /* data processing */
case 0x2:
case 0x3:
{
@@ -700,8 +699,8 @@ arm_get_next_pcs_raw (struct arm_get_next_pcs *self)
break;
if (bits (this_instr, 22, 25) == 0
- && bits (this_instr, 4, 7) == 9) /* multiply */
- error (_("Invalid update to pc in instruction"));
+ && bits (this_instr, 4, 7) == 9) /* multiply */
+ error (_ ("Invalid update to pc in instruction"));
/* BX <reg>, BLX <reg> */
if (bits (this_instr, 4, 27) == 0x12fff1
@@ -709,8 +708,8 @@ arm_get_next_pcs_raw (struct arm_get_next_pcs *self)
{
rn = bits (this_instr, 0, 3);
nextpc = ((rn == ARM_PC_REGNUM)
- ? (pc_val + 8)
- : regcache_raw_get_unsigned (regcache, rn));
+ ? (pc_val + 8)
+ : regcache_raw_get_unsigned (regcache, rn));
next_pcs.push_back (nextpc);
return next_pcs;
@@ -720,84 +719,84 @@ arm_get_next_pcs_raw (struct arm_get_next_pcs *self)
c = (status & FLAG_C) ? 1 : 0;
rn = bits (this_instr, 16, 19);
operand1 = ((rn == ARM_PC_REGNUM)
- ? (pc_val + 8)
- : regcache_raw_get_unsigned (regcache, rn));
+ ? (pc_val + 8)
+ : regcache_raw_get_unsigned (regcache, rn));
if (bit (this_instr, 25))
{
unsigned long immval = bits (this_instr, 0, 7);
unsigned long rotate = 2 * bits (this_instr, 8, 11);
operand2 = ((immval >> rotate) | (immval << (32 - rotate)))
- & 0xffffffff;
+ & 0xffffffff;
}
- else /* operand 2 is a shifted register. */
- operand2 = shifted_reg_val (regcache, this_instr, c,
- pc_val, status);
+ else /* operand 2 is a shifted register. */
+ operand2
+ = shifted_reg_val (regcache, this_instr, c, pc_val, status);
switch (bits (this_instr, 21, 24))
{
- case 0x0: /*and */
+ case 0x0: /*and */
result = operand1 & operand2;
break;
- case 0x1: /*eor */
+ case 0x1: /*eor */
result = operand1 ^ operand2;
break;
- case 0x2: /*sub */
+ case 0x2: /*sub */
result = operand1 - operand2;
break;
- case 0x3: /*rsb */
+ case 0x3: /*rsb */
result = operand2 - operand1;
break;
- case 0x4: /*add */
+ case 0x4: /*add */
result = operand1 + operand2;
break;
- case 0x5: /*adc */
+ case 0x5: /*adc */
result = operand1 + operand2 + c;
break;
- case 0x6: /*sbc */
+ case 0x6: /*sbc */
result = operand1 - operand2 + c;
break;
- case 0x7: /*rsc */
+ case 0x7: /*rsc */
result = operand2 - operand1 + c;
break;
case 0x8:
case 0x9:
case 0xa:
- case 0xb: /* tst, teq, cmp, cmn */
+ case 0xb: /* tst, teq, cmp, cmn */
result = (unsigned long) nextpc;
break;
- case 0xc: /*orr */
+ case 0xc: /*orr */
result = operand1 | operand2;
break;
- case 0xd: /*mov */
+ case 0xd: /*mov */
/* Always step into a function. */
result = operand2;
break;
- case 0xe: /*bic */
+ case 0xe: /*bic */
result = operand1 & ~operand2;
break;
- case 0xf: /*mvn */
+ case 0xf: /*mvn */
result = ~operand2;
break;
}
- nextpc = self->ops->addr_bits_remove (self, result);
+ nextpc = self->ops->addr_bits_remove (self, result);
break;
}
case 0x4:
- case 0x5: /* data transfer */
+ case 0x5: /* data transfer */
case 0x6:
case 0x7:
if (bits (this_instr, 25, 27) == 0x3 && bit (this_instr, 4) == 1)
@@ -817,23 +816,23 @@ arm_get_next_pcs_raw (struct arm_get_next_pcs *self)
unsigned long base;
if (bit (this_instr, 22))
- error (_("Invalid update to pc in instruction"));
+ error (_ ("Invalid update to pc in instruction"));
/* byte write to PC */
rn = bits (this_instr, 16, 19);
base = ((rn == ARM_PC_REGNUM)
- ? (pc_val + 8)
- : regcache_raw_get_unsigned (regcache, rn));
+ ? (pc_val + 8)
+ : regcache_raw_get_unsigned (regcache, rn));
if (bit (this_instr, 24))
{
/* pre-indexed */
int c = (status & FLAG_C) ? 1 : 0;
- unsigned long offset =
- (bit (this_instr, 25)
- ? shifted_reg_val (regcache, this_instr, c,
- pc_val, status)
- : bits (this_instr, 0, 11));
+ unsigned long offset
+ = (bit (this_instr, 25)
+ ? shifted_reg_val (regcache, this_instr, c,
+ pc_val, status)
+ : bits (this_instr, 0, 11));
if (bit (this_instr, 23))
base += offset;
@@ -848,7 +847,7 @@ arm_get_next_pcs_raw (struct arm_get_next_pcs *self)
break;
case 0x8:
- case 0x9: /* block transfer */
+ case 0x9: /* block transfer */
if (bit (this_instr, 20))
{
/* LDM */
@@ -866,21 +865,22 @@ arm_get_next_pcs_raw (struct arm_get_next_pcs *self)
/* up */
unsigned long reglist = bits (this_instr, 0, 14);
offset = count_one_bits_l (reglist) * 4;
- if (bit (this_instr, 24)) /* pre */
+ if (bit (this_instr, 24)) /* pre */
offset += 4;
}
else if (bit (this_instr, 24))
offset = -4;
rn_val_offset = rn_val + offset;
- nextpc = (CORE_ADDR) self->ops->read_mem_uint (rn_val_offset,
- 4, byte_order);
+ nextpc
+ = (CORE_ADDR) self->ops->read_mem_uint (rn_val_offset, 4,
+ byte_order);
}
}
break;
- case 0xb: /* branch & link */
- case 0xa: /* branch */
+ case 0xb: /* branch & link */
+ case 0xa: /* branch */
{
nextpc = BranchDest (pc, this_instr);
break;
@@ -888,16 +888,16 @@ arm_get_next_pcs_raw (struct arm_get_next_pcs *self)
case 0xc:
case 0xd:
- case 0xe: /* coproc ops */
+ case 0xe: /* coproc ops */
break;
- case 0xf: /* SWI */
+ case 0xf: /* SWI */
{
nextpc = self->ops->syscall_next_pc (self);
}
break;
default:
- error (_("Bad bit-field extraction"));
+ error (_ ("Bad bit-field extraction"));
return next_pcs;
}
}
diff --git a/gdb/arch/arm-get-next-pcs.h b/gdb/arch/arm-get-next-pcs.h
index e6bb8d8..583046e 100644
--- a/gdb/arch/arm-get-next-pcs.h
+++ b/gdb/arch/arm-get-next-pcs.h
@@ -55,10 +55,8 @@ struct arm_get_next_pcs
/* Initialize arm_get_next_pcs. */
void arm_get_next_pcs_ctor (struct arm_get_next_pcs *self,
- struct arm_get_next_pcs_ops *ops,
- int byte_order,
- int byte_order_for_code,
- int has_thumb2_breakpoint,
+ struct arm_get_next_pcs_ops *ops, int byte_order,
+ int byte_order_for_code, int has_thumb2_breakpoint,
struct regcache *regcache);
/* Find the next possible PCs after the current instruction executes. */
diff --git a/gdb/arch/arm-linux.c b/gdb/arch/arm-linux.c
index bafbc52..5fbf2a3 100644
--- a/gdb/arch/arm-linux.c
+++ b/gdb/arch/arm-linux.c
@@ -26,10 +26,8 @@
/* Calculate the offset from stack pointer of the pc register on the stack
in the case of a sigreturn or sigreturn_rt syscall. */
int
-arm_linux_sigreturn_next_pc_offset (unsigned long sp,
- unsigned long sp_data,
- unsigned long svc_number,
- int is_sigreturn)
+arm_linux_sigreturn_next_pc_offset (unsigned long sp, unsigned long sp_data,
+ unsigned long svc_number, int is_sigreturn)
{
/* Offset of R0 register. */
int r0_offset = 0;
@@ -62,8 +60,7 @@ arm_linux_sigreturn_next_pc_offset (unsigned long sp,
for arm-linux. */
CORE_ADDR
-arm_linux_get_next_pcs_fixup (struct arm_get_next_pcs *self,
- CORE_ADDR nextpc)
+arm_linux_get_next_pcs_fixup (struct arm_get_next_pcs *self, CORE_ADDR nextpc)
{
/* The Linux kernel offers some user-mode helpers in a high page. We can
not read this page (as of 2.6.23), and even if we could then we
@@ -119,7 +116,7 @@ arm_linux_get_next_pcs_fixup (struct arm_get_next_pcs *self,
}
else
{
- if (bits (insn, 24, 27) == 0xb /* BL <label> */
+ if (bits (insn, 24, 27) == 0xb /* BL <label> */
|| bits (insn, 4, 27) == 0x12fff3 /* BLX Rm */)
bl_blx_p = 1;
}
diff --git a/gdb/arch/arm-linux.h b/gdb/arch/arm-linux.h
index 8432990..b38702f 100644
--- a/gdb/arch/arm-linux.h
+++ b/gdb/arch/arm-linux.h
@@ -68,11 +68,10 @@
#define ARM_NEW_SIGFRAME_MAGIC 0x5ac3c35a
-int
-arm_linux_sigreturn_next_pc_offset (unsigned long sp,
- unsigned long sp_data,
- unsigned long svc_number,
- int is_sigreturn);
+int arm_linux_sigreturn_next_pc_offset (unsigned long sp,
+ unsigned long sp_data,
+ unsigned long svc_number,
+ int is_sigreturn);
struct arm_get_next_pcs;
diff --git a/gdb/arch/arm.c b/gdb/arch/arm.c
index 4720c20..dfff5fd 100644
--- a/gdb/arch/arm.c
+++ b/gdb/arch/arm.c
@@ -88,7 +88,6 @@ condition_true (unsigned long cond, unsigned long status_reg)
return 1;
}
-
/* See arm.h. */
int
@@ -123,7 +122,7 @@ arm_instruction_changes_pc (uint32_t this_instr)
case 0xe:
/* Coprocessor register transfer. */
if (bits (this_instr, 12, 15) == 15)
- error (_("Invalid update to pc in instruction"));
+ error (_ ("Invalid update to pc in instruction"));
return 0;
default:
return 0;
@@ -194,7 +193,7 @@ arm_instruction_changes_pc (uint32_t this_instr)
return 0;
default:
- internal_error (_("bad value in switch"));
+ internal_error (_ ("bad value in switch"));
}
}
@@ -203,28 +202,27 @@ arm_instruction_changes_pc (uint32_t this_instr)
int
thumb_instruction_changes_pc (unsigned short inst)
{
- if ((inst & 0xff00) == 0xbd00) /* pop {rlist, pc} */
+ if ((inst & 0xff00) == 0xbd00) /* pop {rlist, pc} */
return 1;
- if ((inst & 0xf000) == 0xd000) /* conditional branch */
+ if ((inst & 0xf000) == 0xd000) /* conditional branch */
return 1;
- if ((inst & 0xf800) == 0xe000) /* unconditional branch */
+ if ((inst & 0xf800) == 0xe000) /* unconditional branch */
return 1;
- if ((inst & 0xff00) == 0x4700) /* bx REG, blx REG */
+ if ((inst & 0xff00) == 0x4700) /* bx REG, blx REG */
return 1;
- if ((inst & 0xff87) == 0x4687) /* mov pc, REG */
+ if ((inst & 0xff87) == 0x4687) /* mov pc, REG */
return 1;
- if ((inst & 0xf500) == 0xb100) /* CBNZ or CBZ. */
+ if ((inst & 0xf500) == 0xb100) /* CBNZ or CBZ. */
return 1;
return 0;
}
-
/* See arm.h. */
int
@@ -322,8 +320,8 @@ thumb2_instruction_changes_pc (unsigned short inst1, unsigned short inst2)
/* See arm.h. */
unsigned long
-shifted_reg_val (struct regcache *regcache, unsigned long inst,
- int carry, unsigned long pc_val, unsigned long status_reg)
+shifted_reg_val (struct regcache *regcache, unsigned long inst, int carry,
+ unsigned long pc_val, unsigned long status_reg)
{
unsigned long res, shift;
int rm = bits (inst, 0, 3);
@@ -332,35 +330,33 @@ shifted_reg_val (struct regcache *regcache, unsigned long inst,
if (bit (inst, 4))
{
int rs = bits (inst, 8, 11);
- shift = (rs == 15
- ? pc_val + 8
- : regcache_raw_get_unsigned (regcache, rs)) & 0xFF;
+ shift
+ = (rs == 15 ? pc_val + 8 : regcache_raw_get_unsigned (regcache, rs))
+ & 0xFF;
}
else
shift = bits (inst, 7, 11);
- res = (rm == ARM_PC_REGNUM
- ? (pc_val + (bit (inst, 4) ? 12 : 8))
- : regcache_raw_get_unsigned (regcache, rm));
+ res = (rm == ARM_PC_REGNUM ? (pc_val + (bit (inst, 4) ? 12 : 8))
+ : regcache_raw_get_unsigned (regcache, rm));
switch (shifttype)
{
- case 0: /* LSL */
+ case 0: /* LSL */
res = shift >= 32 ? 0 : res << shift;
break;
- case 1: /* LSR */
+ case 1: /* LSR */
res = shift >= 32 ? 0 : res >> shift;
break;
- case 2: /* ASR */
+ case 2: /* ASR */
if (shift >= 32)
shift = 31;
- res = ((res & 0x80000000L)
- ? ~((~res) >> shift) : res >> shift);
+ res = ((res & 0x80000000L) ? ~((~res) >> shift) : res >> shift);
break;
- case 3: /* ROR/RRX */
+ case 3: /* ROR/RRX */
shift &= 31;
if (shift == 0)
res = (res >> 1) | (carry ? 0x80000000L : 0);
@@ -408,7 +404,7 @@ arm_create_target_description (arm_fp_type fp_type, bool tls)
break;
default:
- error (_("Invalid Arm FP type: %d"), fp_type);
+ error (_ ("Invalid Arm FP type: %d"), fp_type);
}
if (tls)
@@ -457,7 +453,7 @@ arm_create_mprofile_target_description (arm_m_profile_type m_type)
break;
default:
- error (_("Invalid Arm M type: %d"), m_type);
+ error (_ ("Invalid Arm M type: %d"), m_type);
}
return tdesc;
diff --git a/gdb/arch/arm.h b/gdb/arch/arm.h
index c64a156..7f68251 100644
--- a/gdb/arch/arm.h
+++ b/gdb/arch/arm.h
@@ -22,56 +22,59 @@
#include "gdbsupport/tdesc.h"
/* Prologue helper macros for ARMv8.1-m PACBTI. */
-#define IS_PAC(instruction) (instruction == 0xf3af801d)
-#define IS_PACBTI(instruction) (instruction == 0xf3af800d)
-#define IS_BTI(instruction) (instruction == 0xf3af800f)
-#define IS_PACG(instruction) ((instruction & 0xfff0f0f0) == 0xfb60f000)
-#define IS_AUT(instruction) (instruction == 0xf3af802d)
-#define IS_AUTG(instruction) ((instruction & 0xfff00ff0) == 0xfb500f00)
+#define IS_PAC(instruction) (instruction == 0xf3af801d)
+#define IS_PACBTI(instruction) (instruction == 0xf3af800d)
+#define IS_BTI(instruction) (instruction == 0xf3af800f)
+#define IS_PACG(instruction) ((instruction & 0xfff0f0f0) == 0xfb60f000)
+#define IS_AUT(instruction) (instruction == 0xf3af802d)
+#define IS_AUTG(instruction) ((instruction & 0xfff00ff0) == 0xfb500f00)
/* DWARF register numbers according to the AADWARF32 document. */
-enum arm_dwarf_regnum {
+enum arm_dwarf_regnum
+{
ARM_DWARF_RA_AUTH_CODE = 143
};
/* Register numbers of various important registers. */
-enum gdb_regnum {
- ARM_A1_REGNUM = 0, /* first integer-like argument */
- ARM_A4_REGNUM = 3, /* last integer-like argument */
+enum gdb_regnum
+{
+ ARM_A1_REGNUM = 0, /* first integer-like argument */
+ ARM_A4_REGNUM = 3, /* last integer-like argument */
ARM_AP_REGNUM = 11,
ARM_IP_REGNUM = 12,
- ARM_SP_REGNUM = 13, /* Contains address of top of stack */
- ARM_LR_REGNUM = 14, /* address to return to from a function call */
- ARM_PC_REGNUM = 15, /* Contains program counter */
+ ARM_SP_REGNUM = 13, /* Contains address of top of stack */
+ ARM_LR_REGNUM = 14, /* address to return to from a function call */
+ ARM_PC_REGNUM = 15, /* Contains program counter */
/* F0..F7 are the fp registers for the (obsolete) FPA architecture. */
- ARM_F0_REGNUM = 16, /* first floating point register */
- ARM_F3_REGNUM = 19, /* last floating point argument register */
- ARM_F7_REGNUM = 23, /* last floating point register */
- ARM_FPS_REGNUM = 24, /* floating point status register */
- ARM_PS_REGNUM = 25, /* Contains processor status */
- ARM_WR0_REGNUM, /* WMMX data registers. */
+ ARM_F0_REGNUM = 16, /* first floating point register */
+ ARM_F3_REGNUM = 19, /* last floating point argument register */
+ ARM_F7_REGNUM = 23, /* last floating point register */
+ ARM_FPS_REGNUM = 24, /* floating point status register */
+ ARM_PS_REGNUM = 25, /* Contains processor status */
+ ARM_WR0_REGNUM, /* WMMX data registers. */
ARM_WR15_REGNUM = ARM_WR0_REGNUM + 15,
- ARM_WC0_REGNUM, /* WMMX control registers. */
+ ARM_WC0_REGNUM, /* WMMX control registers. */
ARM_WCSSF_REGNUM = ARM_WC0_REGNUM + 2,
ARM_WCASF_REGNUM = ARM_WC0_REGNUM + 3,
ARM_WC7_REGNUM = ARM_WC0_REGNUM + 7,
- ARM_WCGR0_REGNUM, /* WMMX general purpose registers. */
+ ARM_WCGR0_REGNUM, /* WMMX general purpose registers. */
ARM_WCGR3_REGNUM = ARM_WCGR0_REGNUM + 3,
ARM_WCGR7_REGNUM = ARM_WCGR0_REGNUM + 7,
- ARM_D0_REGNUM, /* VFP double-precision registers. */
+ ARM_D0_REGNUM, /* VFP double-precision registers. */
ARM_D31_REGNUM = ARM_D0_REGNUM + 31,
ARM_FPSCR_REGNUM,
/* Other useful registers. */
- ARM_FP_REGNUM = 11, /* Frame register in ARM code, if used. */
- THUMB_FP_REGNUM = 7, /* Frame register in Thumb code, if used. */
+ ARM_FP_REGNUM = 11, /* Frame register in ARM code, if used. */
+ THUMB_FP_REGNUM = 7, /* Frame register in Thumb code, if used. */
ARM_LAST_ARG_REGNUM = ARM_A4_REGNUM,
ARM_LAST_FP_ARG_REGNUM = ARM_F3_REGNUM
};
/* Register count constants. */
-enum arm_register_counts {
+enum arm_register_counts
+{
/* Number of Q registers for MVE. */
ARM_MVE_NUM_Q_REGS = 8,
/* Number of argument registers. */
@@ -85,28 +88,30 @@ enum arm_register_counts {
/* Enum describing the different kinds of breakpoints. */
enum arm_breakpoint_kinds
{
- ARM_BP_KIND_THUMB = 2,
- ARM_BP_KIND_THUMB2 = 3,
- ARM_BP_KIND_ARM = 4,
+ ARM_BP_KIND_THUMB = 2,
+ ARM_BP_KIND_THUMB2 = 3,
+ ARM_BP_KIND_ARM = 4,
};
/* Supported Arm FP hardware types. */
-enum arm_fp_type {
- ARM_FP_TYPE_NONE = 0,
- ARM_FP_TYPE_VFPV2,
- ARM_FP_TYPE_VFPV3,
- ARM_FP_TYPE_IWMMXT,
- ARM_FP_TYPE_INVALID
+enum arm_fp_type
+{
+ ARM_FP_TYPE_NONE = 0,
+ ARM_FP_TYPE_VFPV2,
+ ARM_FP_TYPE_VFPV3,
+ ARM_FP_TYPE_IWMMXT,
+ ARM_FP_TYPE_INVALID
};
/* Supported M-profile Arm types. */
-enum arm_m_profile_type {
- ARM_M_TYPE_M_PROFILE,
- ARM_M_TYPE_VFP_D16,
- ARM_M_TYPE_WITH_FPA,
- ARM_M_TYPE_MVE,
- ARM_M_TYPE_SYSTEM,
- ARM_M_TYPE_INVALID
+enum arm_m_profile_type
+{
+ ARM_M_TYPE_M_PROFILE,
+ ARM_M_TYPE_VFP_D16,
+ ARM_M_TYPE_WITH_FPA,
+ ARM_M_TYPE_MVE,
+ ARM_M_TYPE_SYSTEM,
+ ARM_M_TYPE_INVALID
};
/* System control registers accessible through an addresses. */
@@ -124,39 +129,39 @@ enum system_register_address : CORE_ADDR
};
/* Instruction condition field values. */
-#define INST_EQ 0x0
-#define INST_NE 0x1
-#define INST_CS 0x2
-#define INST_CC 0x3
-#define INST_MI 0x4
-#define INST_PL 0x5
-#define INST_VS 0x6
-#define INST_VC 0x7
-#define INST_HI 0x8
-#define INST_LS 0x9
-#define INST_GE 0xa
-#define INST_LT 0xb
-#define INST_GT 0xc
-#define INST_LE 0xd
-#define INST_AL 0xe
-#define INST_NV 0xf
-
-#define FLAG_N 0x80000000
-#define FLAG_Z 0x40000000
-#define FLAG_C 0x20000000
-#define FLAG_V 0x10000000
-
-#define CPSR_T 0x20
-
-#define XPSR_T 0x01000000
+#define INST_EQ 0x0
+#define INST_NE 0x1
+#define INST_CS 0x2
+#define INST_CC 0x3
+#define INST_MI 0x4
+#define INST_PL 0x5
+#define INST_VS 0x6
+#define INST_VC 0x7
+#define INST_HI 0x8
+#define INST_LS 0x9
+#define INST_GE 0xa
+#define INST_LT 0xb
+#define INST_GT 0xc
+#define INST_LE 0xd
+#define INST_AL 0xe
+#define INST_NV 0xf
+
+#define FLAG_N 0x80000000
+#define FLAG_Z 0x40000000
+#define FLAG_C 0x20000000
+#define FLAG_V 0x10000000
+
+#define CPSR_T 0x20
+
+#define XPSR_T 0x01000000
/* Size of registers. */
-#define ARM_INT_REGISTER_SIZE 4
+#define ARM_INT_REGISTER_SIZE 4
/* IEEE extended doubles are 80 bits. DWORD aligned they use 96 bits. */
-#define ARM_FP_REGISTER_SIZE 12
-#define ARM_VFP_REGISTER_SIZE 8
-#define IWMMXT_VEC_REGISTER_SIZE 8
+#define ARM_FP_REGISTER_SIZE 12
+#define ARM_VFP_REGISTER_SIZE 8
+#define IWMMXT_VEC_REGISTER_SIZE 8
/* Size of register sets. */
@@ -169,22 +174,22 @@ enum system_register_address : CORE_ADDR
/* d0-d31,fpscr. */
#define ARM_VFP3_REGS_SIZE (32 * ARM_VFP_REGISTER_SIZE + ARM_INT_REGISTER_SIZE)
/* wR0-wR15,fpscr. */
-#define IWMMXT_REGS_SIZE (16 * IWMMXT_VEC_REGISTER_SIZE \
- + 6 * ARM_INT_REGISTER_SIZE)
+#define IWMMXT_REGS_SIZE \
+ (16 * IWMMXT_VEC_REGISTER_SIZE + 6 * ARM_INT_REGISTER_SIZE)
/* Addresses for calling Thumb functions have the bit 0 set.
Here are some macros to test, set, or clear bit 0 of addresses. */
-#define IS_THUMB_ADDR(addr) ((addr) & 1)
-#define MAKE_THUMB_ADDR(addr) ((addr) | 1)
+#define IS_THUMB_ADDR(addr) ((addr) &1)
+#define MAKE_THUMB_ADDR(addr) ((addr) | 1)
#define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
/* Support routines for instruction parsing. */
#define submask(x) ((1L << ((x) + 1)) - 1)
-#define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
-#define bit(obj,st) (((obj) >> (st)) & 1)
-#define sbits(obj,st,fn) \
- ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
-#define BranchDest(addr,instr) \
+#define bits(obj, st, fn) (((obj) >> (st)) & submask ((fn) - (st)))
+#define bit(obj, st) (((obj) >> (st)) & 1)
+#define sbits(obj, st, fn) \
+ ((long) (bits (obj, st, fn) | ((long) bit (obj, fn) * ~submask (fn - st))))
+#define BranchDest(addr, instr) \
((CORE_ADDR) (((unsigned long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
/* Forward declaration. */
@@ -213,10 +218,8 @@ int thumb_advance_itstate (unsigned int itstate);
/* Decode shifted register value. */
-unsigned long shifted_reg_val (struct regcache *regcache,
- unsigned long inst,
- int carry,
- unsigned long pc_val,
+unsigned long shifted_reg_val (struct regcache *regcache, unsigned long inst,
+ int carry, unsigned long pc_val,
unsigned long status_reg);
/* Create an Arm target description with the given FP hardware type. */
@@ -225,6 +228,7 @@ target_desc *arm_create_target_description (arm_fp_type fp_type, bool tls);
/* Create an Arm M-profile target description with the given hardware type. */
-target_desc *arm_create_mprofile_target_description (arm_m_profile_type m_type);
+target_desc *
+arm_create_mprofile_target_description (arm_m_profile_type m_type);
#endif /* ARCH_ARM_H */
diff --git a/gdb/arch/loongarch.c b/gdb/arch/loongarch.c
index 168fcbc..5b2bada 100644
--- a/gdb/arch/loongarch.c
+++ b/gdb/arch/loongarch.c
@@ -33,7 +33,8 @@
#endif
STATIC_IN_GDB target_desc_up
-loongarch_create_target_description (const struct loongarch_gdbarch_features features)
+loongarch_create_target_description (
+ const struct loongarch_gdbarch_features features)
{
/* Now we should create a new target description. */
target_desc_up tdesc = allocate_target_description ();
@@ -80,12 +81,13 @@ struct loongarch_gdbarch_features_hasher
/* Cache of previously seen target descriptions, indexed by the feature set
that created them. */
-static std::unordered_map<loongarch_gdbarch_features,
- const target_desc_up,
- loongarch_gdbarch_features_hasher> loongarch_tdesc_cache;
+static std::unordered_map<loongarch_gdbarch_features, const target_desc_up,
+ loongarch_gdbarch_features_hasher>
+ loongarch_tdesc_cache;
const target_desc *
-loongarch_lookup_target_description (const struct loongarch_gdbarch_features features)
+loongarch_lookup_target_description (
+ const struct loongarch_gdbarch_features features)
{
/* Lookup in the cache. If we find it then return the pointer out of
the target_desc_up (which is a unique_ptr). This is safe as the
diff --git a/gdb/arch/loongarch.h b/gdb/arch/loongarch.h
index d0a63dc..c9ada1b 100644
--- a/gdb/arch/loongarch.h
+++ b/gdb/arch/loongarch.h
@@ -25,20 +25,22 @@
/* Register numbers of various important registers. */
enum loongarch_regnum
{
- LOONGARCH_RA_REGNUM = 1, /* Return Address. */
- LOONGARCH_SP_REGNUM = 3, /* Stack Pointer. */
- LOONGARCH_A0_REGNUM = 4, /* First Argument/Return Value. */
- LOONGARCH_A7_REGNUM = 11, /* Seventh Argument/Syscall Number. */
- LOONGARCH_FP_REGNUM = 22, /* Frame Pointer. */
- LOONGARCH_ORIG_A0_REGNUM = 32, /* Syscall's original arg0. */
- LOONGARCH_PC_REGNUM = 33, /* Program Counter. */
- LOONGARCH_BADV_REGNUM = 34, /* Bad Vaddr for Addressing Exception. */
- LOONGARCH_LINUX_NUM_GREGSET = 45, /* 32 GPR, ORIG_A0, PC, BADV, RESERVED 10. */
- LOONGARCH_ARG_REGNUM = 8, /* r4-r11: general-purpose argument registers.
+ LOONGARCH_RA_REGNUM = 1, /* Return Address. */
+ LOONGARCH_SP_REGNUM = 3, /* Stack Pointer. */
+ LOONGARCH_A0_REGNUM = 4, /* First Argument/Return Value. */
+ LOONGARCH_A7_REGNUM = 11, /* Seventh Argument/Syscall Number. */
+ LOONGARCH_FP_REGNUM = 22, /* Frame Pointer. */
+ LOONGARCH_ORIG_A0_REGNUM = 32, /* Syscall's original arg0. */
+ LOONGARCH_PC_REGNUM = 33, /* Program Counter. */
+ LOONGARCH_BADV_REGNUM = 34, /* Bad Vaddr for Addressing Exception. */
+ LOONGARCH_LINUX_NUM_GREGSET
+ = 45, /* 32 GPR, ORIG_A0, PC, BADV, RESERVED 10. */
+ LOONGARCH_ARG_REGNUM = 8, /* r4-r11: general-purpose argument registers.
f0-f7: floating-point argument registers. */
LOONGARCH_FIRST_FP_REGNUM = LOONGARCH_LINUX_NUM_GREGSET,
LOONGARCH_LINUX_NUM_FPREGSET = 32,
- LOONGARCH_FIRST_FCC_REGNUM = LOONGARCH_FIRST_FP_REGNUM + LOONGARCH_LINUX_NUM_FPREGSET,
+ LOONGARCH_FIRST_FCC_REGNUM
+ = LOONGARCH_FIRST_FP_REGNUM + LOONGARCH_LINUX_NUM_FPREGSET,
LOONGARCH_LINUX_NUM_FCC = 8,
LOONGARCH_FCSR_REGNUM = LOONGARCH_FIRST_FCC_REGNUM + LOONGARCH_LINUX_NUM_FCC,
};
@@ -98,8 +100,8 @@ struct loongarch_gdbarch_features
This is only used directly from the gdbserver where the created target
description is modified after it is return. */
-target_desc_up loongarch_create_target_description
- (const struct loongarch_gdbarch_features features);
+target_desc_up loongarch_create_target_description (
+ const struct loongarch_gdbarch_features features);
#else
@@ -110,8 +112,8 @@ target_desc_up loongarch_create_target_description
GDBARCH_LIST_LOOKUP_BY_INFO performs a pointer comparison on target
descriptions to find candidate gdbarch objects. */
-const target_desc *loongarch_lookup_target_description
- (const struct loongarch_gdbarch_features features);
+const target_desc *loongarch_lookup_target_description (
+ const struct loongarch_gdbarch_features features);
#endif /* GDBSERVER */
diff --git a/gdb/arch/ppc-linux-common.c b/gdb/arch/ppc-linux-common.c
index 93f1c2e..dd7e0bb 100644
--- a/gdb/arch/ppc-linux-common.c
+++ b/gdb/arch/ppc-linux-common.c
@@ -27,7 +27,7 @@
when debugging core files, which might not provide this constant. */
#ifndef PPC_FEATURE_HAS_DFP
-#define PPC_FEATURE_HAS_DFP 0x00000400
+#define PPC_FEATURE_HAS_DFP 0x00000400
#endif
bool
@@ -51,34 +51,34 @@ ppc_linux_match_description (struct ppc_linux_features features)
if (features.wordsize == 8)
{
if (features.vsx)
- tdesc = (features.htm? tdesc_powerpc_isa207_htm_vsx64l
- : features.isa207? tdesc_powerpc_isa207_vsx64l
- : features.ppr_dscr? tdesc_powerpc_isa205_ppr_dscr_vsx64l
- : features.isa205? tdesc_powerpc_isa205_vsx64l
- : tdesc_powerpc_vsx64l);
+ tdesc = (features.htm ? tdesc_powerpc_isa207_htm_vsx64l
+ : features.isa207 ? tdesc_powerpc_isa207_vsx64l
+ : features.ppr_dscr ? tdesc_powerpc_isa205_ppr_dscr_vsx64l
+ : features.isa205 ? tdesc_powerpc_isa205_vsx64l
+ : tdesc_powerpc_vsx64l);
else if (features.altivec)
- tdesc = (features.isa205? tdesc_powerpc_isa205_altivec64l
- : tdesc_powerpc_altivec64l);
+ tdesc = (features.isa205 ? tdesc_powerpc_isa205_altivec64l
+ : tdesc_powerpc_altivec64l);
else
- tdesc = (features.isa205? tdesc_powerpc_isa205_64l
- : tdesc_powerpc_64l);
+ tdesc
+ = (features.isa205 ? tdesc_powerpc_isa205_64l : tdesc_powerpc_64l);
}
else
{
gdb_assert (features.wordsize == 4);
if (features.vsx)
- tdesc = (features.htm? tdesc_powerpc_isa207_htm_vsx32l
- : features.isa207? tdesc_powerpc_isa207_vsx32l
- : features.ppr_dscr? tdesc_powerpc_isa205_ppr_dscr_vsx32l
- : features.isa205? tdesc_powerpc_isa205_vsx32l
- : tdesc_powerpc_vsx32l);
+ tdesc = (features.htm ? tdesc_powerpc_isa207_htm_vsx32l
+ : features.isa207 ? tdesc_powerpc_isa207_vsx32l
+ : features.ppr_dscr ? tdesc_powerpc_isa205_ppr_dscr_vsx32l
+ : features.isa205 ? tdesc_powerpc_isa205_vsx32l
+ : tdesc_powerpc_vsx32l);
else if (features.altivec)
- tdesc = (features.isa205? tdesc_powerpc_isa205_altivec32l
- : tdesc_powerpc_altivec32l);
+ tdesc = (features.isa205 ? tdesc_powerpc_isa205_altivec32l
+ : tdesc_powerpc_altivec32l);
else
- tdesc = (features.isa205? tdesc_powerpc_isa205_32l
- : tdesc_powerpc_32l);
+ tdesc
+ = (features.isa205 ? tdesc_powerpc_isa205_32l : tdesc_powerpc_32l);
}
gdb_assert (tdesc != NULL);
diff --git a/gdb/arch/ppc-linux-common.h b/gdb/arch/ppc-linux-common.h
index 8b9ba70..c2e37a0 100644
--- a/gdb/arch/ppc-linux-common.h
+++ b/gdb/arch/ppc-linux-common.h
@@ -33,14 +33,14 @@ struct target_desc;
#define PPC_LINUX_SIZEOF_PPRREGSET 8
#define PPC_LINUX_SIZEOF_DSCRREGSET 8
#define PPC_LINUX_SIZEOF_TARREGSET 8
-#define PPC_LINUX_SIZEOF_EBBREGSET (3*8)
-#define PPC_LINUX_SIZEOF_PMUREGSET (5*8)
-#define PPC_LINUX_SIZEOF_TM_SPRREGSET (3*8)
-#define PPC32_LINUX_SIZEOF_CGPRREGSET (48*4)
-#define PPC64_LINUX_SIZEOF_CGPRREGSET (48*8)
-#define PPC_LINUX_SIZEOF_CFPRREGSET (32*8+8)
-#define PPC_LINUX_SIZEOF_CVMXREGSET (34*16)
-#define PPC_LINUX_SIZEOF_CVSXREGSET (32*8)
+#define PPC_LINUX_SIZEOF_EBBREGSET (3 * 8)
+#define PPC_LINUX_SIZEOF_PMUREGSET (5 * 8)
+#define PPC_LINUX_SIZEOF_TM_SPRREGSET (3 * 8)
+#define PPC32_LINUX_SIZEOF_CGPRREGSET (48 * 4)
+#define PPC64_LINUX_SIZEOF_CGPRREGSET (48 * 8)
+#define PPC_LINUX_SIZEOF_CFPRREGSET (32 * 8 + 8)
+#define PPC_LINUX_SIZEOF_CVMXREGSET (34 * 16)
+#define PPC_LINUX_SIZEOF_CVSXREGSET (32 * 8)
#define PPC_LINUX_SIZEOF_CPPRREGSET 8
#define PPC_LINUX_SIZEOF_CDSCRREGSET 8
#define PPC_LINUX_SIZEOF_CTARREGSET 8
@@ -62,17 +62,11 @@ struct ppc_linux_features
/* Base value for ppc_linux_features variables. */
const struct ppc_linux_features ppc_linux_no_features = {
- 0,
- false,
- false,
- false,
- false,
- false,
- false,
+ 0, false, false, false, false, false, false,
};
/* Return a target description that matches FEATURES. */
-const struct target_desc * ppc_linux_match_description
-(struct ppc_linux_features features);
+const struct target_desc *
+ppc_linux_match_description (struct ppc_linux_features features);
#endif /* ARCH_PPC_LINUX_COMMON_H */
diff --git a/gdb/arch/riscv.c b/gdb/arch/riscv.c
index 6f6fcb0..dae4eea 100644
--- a/gdb/arch/riscv.c
+++ b/gdb/arch/riscv.c
@@ -88,7 +88,7 @@ riscv_create_target_description (const struct riscv_gdbarch_features features)
targets. We don't support creating vector features on native targets
(yet). */
if (features.vlen != 0)
- error (_("unable to create vector feature"));
+ error (_ ("unable to create vector feature"));
return tdesc;
}
@@ -107,9 +107,9 @@ struct riscv_gdbarch_features_hasher
/* Cache of previously seen target descriptions, indexed by the feature set
that created them. */
-static std::unordered_map<riscv_gdbarch_features,
- const target_desc_up,
- riscv_gdbarch_features_hasher> riscv_tdesc_cache;
+static std::unordered_map<riscv_gdbarch_features, const target_desc_up,
+ riscv_gdbarch_features_hasher>
+ riscv_tdesc_cache;
/* See arch/riscv.h. */
diff --git a/gdb/arch/riscv.h b/gdb/arch/riscv.h
index 54610ed..0e14cd9 100644
--- a/gdb/arch/riscv.h
+++ b/gdb/arch/riscv.h
@@ -67,9 +67,8 @@ struct riscv_gdbarch_features
/* Equality operator. */
bool operator== (const struct riscv_gdbarch_features &rhs) const
{
- return (xlen == rhs.xlen && flen == rhs.flen
- && embedded == rhs.embedded && vlen == rhs.vlen
- && has_fflags_reg == rhs.has_fflags_reg
+ return (xlen == rhs.xlen && flen == rhs.flen && embedded == rhs.embedded
+ && vlen == rhs.vlen && has_fflags_reg == rhs.has_fflags_reg
&& has_frm_reg == rhs.has_frm_reg
&& has_fcsr_reg == rhs.has_fcsr_reg);
}
@@ -83,13 +82,10 @@ struct riscv_gdbarch_features
/* Used by std::unordered_map to hash feature sets. */
std::size_t hash () const noexcept
{
- std::size_t val = ((embedded ? 1 : 0) << 10
- | (has_fflags_reg ? 1 : 0) << 11
- | (has_frm_reg ? 1 : 0) << 12
- | (has_fcsr_reg ? 1 : 0) << 13
- | (xlen & 0x1f) << 5
- | (flen & 0x1f) << 0
- | (vlen & 0xfff) << 14);
+ std::size_t val
+ = ((embedded ? 1 : 0) << 10 | (has_fflags_reg ? 1 : 0) << 11
+ | (has_frm_reg ? 1 : 0) << 12 | (has_fcsr_reg ? 1 : 0) << 13
+ | (xlen & 0x1f) << 5 | (flen & 0x1f) << 0 | (vlen & 0xfff) << 14);
return val;
}
};
@@ -100,8 +96,8 @@ struct riscv_gdbarch_features
This is only used directly from the gdbserver where the created target
description is modified after it is return. */
-target_desc_up riscv_create_target_description
- (const struct riscv_gdbarch_features features);
+target_desc_up
+riscv_create_target_description (const struct riscv_gdbarch_features features);
#else
@@ -112,10 +108,9 @@ target_desc_up riscv_create_target_description
GDBARCH_LIST_LOOKUP_BY_INFO performs a pointer comparison on target
descriptions to find candidate gdbarch objects. */
-const target_desc *riscv_lookup_target_description
- (const struct riscv_gdbarch_features features);
+const target_desc *
+riscv_lookup_target_description (const struct riscv_gdbarch_features features);
#endif /* GDBSERVER */
-
#endif /* ARCH_RISCV_H */
diff --git a/gdb/arch/xtensa.h b/gdb/arch/xtensa.h
index 865ddfc..9bc3d4c 100644
--- a/gdb/arch/xtensa.h
+++ b/gdb/arch/xtensa.h
@@ -36,13 +36,13 @@ typedef struct
xtensa_elf_greg_t windowstart;
xtensa_elf_greg_t windowbase;
xtensa_elf_greg_t threadptr;
- xtensa_elf_greg_t reserved[7+48];
+ xtensa_elf_greg_t reserved[7 + 48];
xtensa_elf_greg_t ar[64];
} xtensa_elf_gregset_t;
-#define XTENSA_ELF_NGREG (sizeof (xtensa_elf_gregset_t) \
- / sizeof (xtensa_elf_greg_t))
+#define XTENSA_ELF_NGREG \
+ (sizeof (xtensa_elf_gregset_t) / sizeof (xtensa_elf_greg_t))
-#define C0_NREGS 16 /* Number of A-registers to track in call0 ABI. */
+#define C0_NREGS 16 /* Number of A-registers to track in call0 ABI. */
#endif /* ARCH_XTENSA_H */
generated by cgit v1.1 at 2025-08-05 16:30:01 +0000