diff options
-rw-r--r-- | gas/config/tc-aarch64.c | 81 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/sme-2-illegal.l | 10 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/sme-3-illegal.l | 10 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/sme-5-illegal.l | 38 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/sme-6-illegal.l | 38 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/sme-7-illegal.l | 20 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/sme-9-illegal.l | 18 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/sme-9-illegal.s | 2 | ||||
-rw-r--r-- | include/opcode/aarch64.h | 1 | ||||
-rw-r--r-- | opcodes/aarch64-opc-2.c | 8 | ||||
-rw-r--r-- | opcodes/aarch64-opc.c | 45 | ||||
-rw-r--r-- | opcodes/aarch64-tbl.h | 39 |
12 files changed, 145 insertions, 165 deletions
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 0db2ba0..ba7f543 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -4440,50 +4440,14 @@ parse_sme_za_hv_tiles_operand (char **str, struct aarch64_indexed_za *opnd, aarch64_opnd_qualifier_t *qualifier) { - int64_t imm_limit; - const reg_entry *reg; - - reg = parse_reg_with_qual (str, REG_TYPE_ZATHV, qualifier); + const reg_entry *reg = parse_reg_with_qual (str, REG_TYPE_ZATHV, qualifier); if (!reg) return false; opnd->v = aarch64_check_reg_type (reg, REG_TYPE_ZATV); opnd->regno = reg->number; - switch (*qualifier) - { - case AARCH64_OPND_QLF_S_B: - imm_limit = 15; - break; - case AARCH64_OPND_QLF_S_H: - imm_limit = 7; - break; - case AARCH64_OPND_QLF_S_S: - imm_limit = 3; - break; - case AARCH64_OPND_QLF_S_D: - imm_limit = 1; - break; - case AARCH64_OPND_QLF_S_Q: - imm_limit = 0; - break; - default: - set_syntax_error (_("invalid ZA tile element size, allowed b, h, s, d and q")); - return false; - } - - if (!parse_sme_za_index (str, opnd)) - return false; - - /* Check if optional index offset is in the range for instruction - variant. */ - if (opnd->index.imm < 0 || opnd->index.imm > imm_limit) - { - set_syntax_error (_("index offset out of range")); - return false; - } - - return true; + return parse_sme_za_index (str, opnd); } /* Like parse_sme_za_hv_tiles_operand, but expect braces around the @@ -4644,17 +4608,8 @@ parse_sme_za_array (char **str, struct aarch64_indexed_za *opnd) } opnd->regno = -1; - if (! parse_sme_za_index (&q, opnd)) - return false; - - if (opnd->index.imm < 0 || opnd->index.imm > 15) - { - set_syntax_error (_("offset out of range")); - return false; - } - *str = q; - return true; + return parse_sme_za_index (str, opnd); } /* Parse streaming mode operand for SMSTART and SMSTOP. @@ -4697,43 +4652,15 @@ static bool parse_sme_pred_reg_with_index (char **str, struct aarch64_indexed_za *opnd, aarch64_opnd_qualifier_t *qualifier) { - int regno; - int64_t imm_limit; const reg_entry *reg = parse_reg_with_qual (str, REG_TYPE_PN, qualifier); - if (reg == NULL) return false; - regno = reg->number; - switch (*qualifier) - { - case AARCH64_OPND_QLF_S_B: - imm_limit = 15; - break; - case AARCH64_OPND_QLF_S_H: - imm_limit = 7; - break; - case AARCH64_OPND_QLF_S_S: - imm_limit = 3; - break; - case AARCH64_OPND_QLF_S_D: - imm_limit = 1; - break; - default: - set_syntax_error (_("wrong predicate register element size, allowed b, h, s and d")); - return false; - } - opnd->regno = regno; + opnd->regno = reg->number; if (! parse_sme_za_index (str, opnd)) return false; - if (opnd->index.imm < 0 || opnd->index.imm > imm_limit) - { - set_syntax_error (_("element index out of range for given variant")); - return false; - } - return true; } diff --git a/gas/testsuite/gas/aarch64/sme-2-illegal.l b/gas/testsuite/gas/aarch64/sme-2-illegal.l index 994c6f1..eaf1b97 100644 --- a/gas/testsuite/gas/aarch64/sme-2-illegal.l +++ b/gas/testsuite/gas/aarch64/sme-2-illegal.l @@ -4,11 +4,11 @@ [^:]*:[0-9]+: Error: ZA tile number out of range at operand 3 -- `mova z0\.s,p0/m,za4h\.s\[w12,#0\]' [^:]*:[0-9]+: Error: ZA tile number out of range at operand 3 -- `mova z0\.d,p0/m,za8h\.d\[w12,#0\]' [^:]*:[0-9]+: Error: operand 3 must be an SME horizontal or vertical vector access register -- `mova z0\.q,p0/m,za16h.q\[w12\]' -[^:]*:[0-9]+: Error: index offset out of range at operand 3 -- `mova z31\.b,p7/m,za0v\.b\[w15,#16\]' -[^:]*:[0-9]+: Error: index offset out of range at operand 3 -- `mova z31\.h,p7/m,za1v\.h\[w15,#8\]' -[^:]*:[0-9]+: Error: index offset out of range at operand 3 -- `mova z31\.s,p7/m,za3v\.s\[w15,#4\]' -[^:]*:[0-9]+: Error: index offset out of range at operand 3 -- `mova z31\.d,p7/m,za7v\.d\[w15,#2\]' -[^:]*:[0-9]+: Error: index offset out of range at operand 3 -- `mova z31\.q,p7/m,za15v\.q\[w15,#1\]' +[^:]*:[0-9]+: Error: immediate offset out of range 0 to 15 at operand 3 -- `mova z31\.b,p7/m,za0v\.b\[w15,#16\]' +[^:]*:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 3 -- `mova z31\.h,p7/m,za1v\.h\[w15,#8\]' +[^:]*:[0-9]+: Error: immediate offset out of range 0 to 3 at operand 3 -- `mova z31\.s,p7/m,za3v\.s\[w15,#4\]' +[^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 3 -- `mova z31\.d,p7/m,za7v\.d\[w15,#2\]' +[^:]*:[0-9]+: Error: immediate offset must be 0 at operand 3 -- `mova z31\.q,p7/m,za15v\.q\[w15,#1\]' [^:]*:[0-9]+: Error: expected ',' at operand 3 -- `mova z31\.q,p7/m,za15v\.q\[w15\]' [^:]*:[0-9]+: Error: expected '\[' at operand 3 -- `mova z0\.b,p0/m,za0v.b' [^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `mova z31\.b,p7/m,za0v\.b\[15,w15\]' diff --git a/gas/testsuite/gas/aarch64/sme-3-illegal.l b/gas/testsuite/gas/aarch64/sme-3-illegal.l index 6b2791d..cb8fe4e 100644 --- a/gas/testsuite/gas/aarch64/sme-3-illegal.l +++ b/gas/testsuite/gas/aarch64/sme-3-illegal.l @@ -4,8 +4,8 @@ [^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za4v\.s\[w12,#0\],p0/m,z0.s' [^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za8v\.d\[w12,#0\],p0/m,z0.d' [^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `mova za16v\.q\[w12\],p0/m,z0.q' -[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `mova za0v\.b\[w15,#16\],p7/m,z31.b' -[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `mova za1v\.h\[w15,#8\],p7/m,z31.h' -[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `mova za3v\.s\[w15,#4\],p7/m,z31.s' -[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `mova za7v\.d\[w15,#2\],p7/m,z31.d' -[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `mova za15v\.q\[w15,#1\],p7/m,z31.q' +[^:]*:[0-9]+: Error: immediate offset out of range 0 to 15 at operand 1 -- `mova za0v\.b\[w15,#16\],p7/m,z31.b' +[^:]*:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `mova za1v\.h\[w15,#8\],p7/m,z31.h' +[^:]*:[0-9]+: Error: immediate offset out of range 0 to 3 at operand 1 -- `mova za3v\.s\[w15,#4\],p7/m,z31.s' +[^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 1 -- `mova za7v\.d\[w15,#2\],p7/m,z31.d' +[^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `mova za15v\.q\[w15,#1\],p7/m,z31.q' diff --git a/gas/testsuite/gas/aarch64/sme-5-illegal.l b/gas/testsuite/gas/aarch64/sme-5-illegal.l index ec1e989..d706a16 100644 --- a/gas/testsuite/gas/aarch64/sme-5-illegal.l +++ b/gas/testsuite/gas/aarch64/sme-5-illegal.l @@ -8,41 +8,41 @@ [^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `ld1b {za1h.b\[w12,0\]},p0/z,\[x0\]' [^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `ld1b {za1v.b\[w12,0\]},p0/z,\[sp\]' [^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `ld1b {za1h.b\[w12,0\]},p0/z,\[sp,x0\]' -[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1b {za0v.b\[w15,16\]},p7/z,\[x17\]' -[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1b {za0h.b\[w15,16\]},p7/z,\[sp\]' -[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1b {za0v.b\[w15,16\]},p7/z,\[sp,x17\]' +[^:]*:[0-9]+: Error: immediate offset out of range 0 to 15 at operand 1 -- `ld1b {za0v.b\[w15,16\]},p7/z,\[x17\]' +[^:]*:[0-9]+: Error: immediate offset out of range 0 to 15 at operand 1 -- `ld1b {za0h.b\[w15,16\]},p7/z,\[sp\]' +[^:]*:[0-9]+: Error: immediate offset out of range 0 to 15 at operand 1 -- `ld1b {za0v.b\[w15,16\]},p7/z,\[sp,x17\]' [^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `ld1h {za2v.h\[w12,0\]},p0/z,\[x0\]' [^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `ld1h {za2h.h\[w12,0\]},p0/z,\[sp\]' [^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `ld1h {za2v.h\[w12,0\]},p0/z,\[x0,x0,lsl#1\]' [^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `ld1h {za2h.h\[w12,0\]},p0/z,\[sp,x0,lsl#1\]' -[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1h {za1v.h\[w15,8\]},p7/z,\[x17\]' -[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1h {za1h.h\[w15,8\]},p7/z,\[sp\]' -[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1h {za1v.h\[w15,8\]},p7/z,\[x0,x17,lsl#1\]' -[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1h {za1h.h\[w15,8\]},p7/z,\[sp,x17,lsl#1\]' +[^:]*:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `ld1h {za1v.h\[w15,8\]},p7/z,\[x17\]' +[^:]*:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `ld1h {za1h.h\[w15,8\]},p7/z,\[sp\]' +[^:]*:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `ld1h {za1v.h\[w15,8\]},p7/z,\[x0,x17,lsl#1\]' +[^:]*:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `ld1h {za1h.h\[w15,8\]},p7/z,\[sp,x17,lsl#1\]' [^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `ld1w {za4h.s\[w12,0\]},p0/z,\[x0\]' [^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `ld1w {za4v.s\[w12,0\]},p0/z,\[sp\]' [^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `ld1w {za4h.s\[w12,0\]},p0/z,\[x0,x0,lsl#2\]' [^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `ld1w {za4v.s\[w12,0\]},p0/z,\[sp,x0,lsl#2\]' -[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1w {za3h.s\[w15,4\]},p7/z,\[x17\]' -[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1w {za3v.s\[w15,4\]},p7/z,\[sp\]' -[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1w {za3h.s\[w15,4\]},p7/z,\[x0,x17,lsl#2\]' -[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1w {za3v.s\[w15,4\]},p7/z,\[sp,x17,lsl#2\]' +[^:]*:[0-9]+: Error: immediate offset out of range 0 to 3 at operand 1 -- `ld1w {za3h.s\[w15,4\]},p7/z,\[x17\]' +[^:]*:[0-9]+: Error: immediate offset out of range 0 to 3 at operand 1 -- `ld1w {za3v.s\[w15,4\]},p7/z,\[sp\]' +[^:]*:[0-9]+: Error: immediate offset out of range 0 to 3 at operand 1 -- `ld1w {za3h.s\[w15,4\]},p7/z,\[x0,x17,lsl#2\]' +[^:]*:[0-9]+: Error: immediate offset out of range 0 to 3 at operand 1 -- `ld1w {za3v.s\[w15,4\]},p7/z,\[sp,x17,lsl#2\]' [^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `ld1d {za8v.d\[w12,0\]},p0/z,\[x0\]' [^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `ld1d {za8h.d\[w12,0\]},p0/z,\[sp\]' [^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `ld1d {za8v.d\[w12,0\]},p0/z,\[x0,x0,lsl#3\]' [^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `ld1d {za8h.d\[w12,0\]},p0/z,\[sp,x0,lsl#3\]' -[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1d {za7v.d\[w15,2\]},p7/z,\[x17\]' -[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1d {za7h.d\[w15,2\]},p7/z,\[sp\]' -[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1d {za7v.d\[w15,2\]},p7/z,\[x0,x17,lsl#3\]' -[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1d {za7h.d\[w15,2\]},p7/z,\[sp,x17,lsl#3\]' +[^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 1 -- `ld1d {za7v.d\[w15,2\]},p7/z,\[x17\]' +[^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 1 -- `ld1d {za7h.d\[w15,2\]},p7/z,\[sp\]' +[^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 1 -- `ld1d {za7v.d\[w15,2\]},p7/z,\[x0,x17,lsl#3\]' +[^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 1 -- `ld1d {za7h.d\[w15,2\]},p7/z,\[sp,x17,lsl#3\]' [^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `ld1q {za16v.q\[w12\]},p0/z,\[x0\]' [^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `ld1q {za16h.q\[w12\]},p0/z,\[sp\]' [^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `ld1q {za16v.q\[w12\]},p0/z,\[x0,x0,lsl#4\]' [^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `ld1q {za16h.q\[w12\]},p0/z,\[sp,x0,lsl#4\]' -[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1q {za15v.q\[w15,1\]},p7/z,\[x17\]' -[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1q {za15h.q\[w15,1\]},p7/z,\[sp\]' -[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1q {za15v.q\[w15,1\]},p7/z,\[x0,x17,lsl#4\]' -[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `ld1q {za15h.q\[w15,1\]},p7/z,\[sp,x17,lsl#4\]' +[^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `ld1q {za15v.q\[w15,1\]},p7/z,\[x17\]' +[^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `ld1q {za15h.q\[w15,1\]},p7/z,\[sp\]' +[^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `ld1q {za15v.q\[w15,1\]},p7/z,\[x0,x17,lsl#4\]' +[^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `ld1q {za15h.q\[w15,1\]},p7/z,\[sp,x17,lsl#4\]' [^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1b {za0h.b\[w12,0\]},p0/z,\[x0,x1,lsl#1\]' [^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1h {za0h.h\[w12,0\]},p0/z,\[x0,x1,lsl#2\]' [^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1w {za3v.s\[w12,3\]},p7/z,\[x0,x1,lsl#3\]' diff --git a/gas/testsuite/gas/aarch64/sme-6-illegal.l b/gas/testsuite/gas/aarch64/sme-6-illegal.l index 4fe3613..d2a3f3c 100644 --- a/gas/testsuite/gas/aarch64/sme-6-illegal.l +++ b/gas/testsuite/gas/aarch64/sme-6-illegal.l @@ -8,38 +8,38 @@ [^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `st1b {za1h.b\[w12,0\]},p0,\[x0\]' [^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `st1b {za1v.b\[w12,0\]},p0,\[sp\]' [^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `st1b {za1h.b\[w12,0\]},p0,\[sp,x0\]' -[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1b {za0v.b\[w15,16\]},p7,\[x17\]' -[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1b {za0h.b\[w15,16\]},p7,\[sp\]' -[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1b {za0v.b\[w15,16\]},p7,\[sp,x17\]' +[^:]*:[0-9]+: Error: immediate offset out of range 0 to 15 at operand 1 -- `st1b {za0v.b\[w15,16\]},p7,\[x17\]' +[^:]*:[0-9]+: Error: immediate offset out of range 0 to 15 at operand 1 -- `st1b {za0h.b\[w15,16\]},p7,\[sp\]' +[^:]*:[0-9]+: Error: immediate offset out of range 0 to 15 at operand 1 -- `st1b {za0v.b\[w15,16\]},p7,\[sp,x17\]' [^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `st1h {za2v.h\[w12,0\]},p0,\[x0\]' [^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `st1h {za2h.h\[w12,0\]},p0,\[sp\]' [^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `st1h {za2v.h\[w12,0\]},p0,\[x0,x0,lsl#1\]' [^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `st1h {za2h.h\[w12,0\]},p0,\[sp,x0,lsl#1\]' -[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1h {za1v.h\[w15,8\]},p7,\[x17\]' -[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1h {za1h.h\[w15,8\]},p7,\[sp\]' -[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1h {za1v.h\[w15,8\]},p7,\[x0,x17,lsl#1\]' -[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1h {za1h.h\[w15,8\]},p7,\[sp,x17,lsl#1\]' +[^:]*:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `st1h {za1v.h\[w15,8\]},p7,\[x17\]' +[^:]*:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `st1h {za1h.h\[w15,8\]},p7,\[sp\]' +[^:]*:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `st1h {za1v.h\[w15,8\]},p7,\[x0,x17,lsl#1\]' +[^:]*:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `st1h {za1h.h\[w15,8\]},p7,\[sp,x17,lsl#1\]' [^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `st1w {za4h.s\[w12,0\]},p0,\[x0\]' [^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `st1w {za4v.s\[w12,0\]},p0,\[sp\]' [^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `st1w {za4h.s\[w12,0\]},p0,\[x0,x0,lsl#2\]' [^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `st1w {za4v.s\[w12,0\]},p0,\[sp,x0,lsl#2\]' -[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1w {za3h.s\[w15,4\]},p7,\[x17\]' -[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1w {za3v.s\[w15,4\]},p7,\[sp\]' -[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1w {za3h.s\[w15,4\]},p7,\[x0,x17,lsl#2\]' -[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1w {za3v.s\[w15,4\]},p7,\[sp,x17,lsl#2\]' +[^:]*:[0-9]+: Error: immediate offset out of range 0 to 3 at operand 1 -- `st1w {za3h.s\[w15,4\]},p7,\[x17\]' +[^:]*:[0-9]+: Error: immediate offset out of range 0 to 3 at operand 1 -- `st1w {za3v.s\[w15,4\]},p7,\[sp\]' +[^:]*:[0-9]+: Error: immediate offset out of range 0 to 3 at operand 1 -- `st1w {za3h.s\[w15,4\]},p7,\[x0,x17,lsl#2\]' +[^:]*:[0-9]+: Error: immediate offset out of range 0 to 3 at operand 1 -- `st1w {za3v.s\[w15,4\]},p7,\[sp,x17,lsl#2\]' [^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `st1d {za8v.d\[w12,0\]},p0,\[x0\]' [^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `st1d {za8h.d\[w12,0\]},p0,\[sp\]' [^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `st1d {za8v.d\[w12,0\]},p0,\[x0,x0,lsl#3\]' [^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `st1d {za8h.d\[w12,0\]},p0,\[sp,x0,lsl#3\]' -[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1d {za7v.d\[w15,2\]},p7,\[x17\]' -[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1d {za7h.d\[w15,2\]},p7,\[sp\]' -[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1d {za7v.d\[w15,2\]},p7,\[x0,x17,lsl#3\]' -[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1d {za7h.d\[w15,2\]},p7,\[sp,x17,lsl#3\]' +[^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 1 -- `st1d {za7v.d\[w15,2\]},p7,\[x17\]' +[^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 1 -- `st1d {za7h.d\[w15,2\]},p7,\[sp\]' +[^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 1 -- `st1d {za7v.d\[w15,2\]},p7,\[x0,x17,lsl#3\]' +[^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 1 -- `st1d {za7h.d\[w15,2\]},p7,\[sp,x17,lsl#3\]' [^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `st1q {za16v.q\[w12\]},p0,\[x0\]' [^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `st1q {za16h.q\[w12\]},p0,\[sp\]' [^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `st1q {za16v.q\[w12\]},p0,\[x0,x0,lsl#4\]' [^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `st1q {za16h.q\[w12\]},p0,\[sp,x0,lsl#4\]' -[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1q {za15v.q\[w15,1\]},p7,\[x17\]' -[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1q {za15h.q\[w15,1\]},p7,\[sp\]' -[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1q {za15v.q\[w15,1\]},p7,\[x0,x17,lsl#4\]' -[^:]*:[0-9]+: Error: index offset out of range at operand 1 -- `st1q {za15h.q\[w15,1\]},p7,\[sp,x17,lsl#4\]' +[^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `st1q {za15v.q\[w15,1\]},p7,\[x17\]' +[^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `st1q {za15h.q\[w15,1\]},p7,\[sp\]' +[^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `st1q {za15v.q\[w15,1\]},p7,\[x0,x17,lsl#4\]' +[^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `st1q {za15h.q\[w15,1\]},p7,\[sp,x17,lsl#4\]' diff --git a/gas/testsuite/gas/aarch64/sme-7-illegal.l b/gas/testsuite/gas/aarch64/sme-7-illegal.l index 913bd0e..242c5ec 100644 --- a/gas/testsuite/gas/aarch64/sme-7-illegal.l +++ b/gas/testsuite/gas/aarch64/sme-7-illegal.l @@ -3,8 +3,8 @@ [^:]*:[0-9]+: Error: invalid addressing mode at operand 2 -- `ldr za\[w12,1\],\[sp,x0\]' [^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `ldr za\[w12,0\],\[sp,#1,mul vl\]' [^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `ldr za\[w13,9\],\[x17,#19,mul vl\]' -[^:]*:[0-9]+: Error: offset out of range at operand 1 -- `ldr za\[w13,21\],\[x17,#21,mul vl\]' -[^:]*:[0-9]+: Error: offset out of range at operand 1 -- `ldr za\[w15,32\],\[x17,#15,mul vl\]' +[^:]*:[0-9]+: Error: immediate offset out of range 0 to 15 at operand 1 -- `ldr za\[w13,21\],\[x17,#21,mul vl\]' +[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `ldr za\[w15,32\],\[x17,#15,mul vl\]' [^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 1 -- `ldr za\[w16,15\],\[sp,#15,mul vl\]' [^:]*:[0-9]+: Error: only 'MUL VL' is permitted at operand 2 -- `ldr za\[w12,0\],\[x0,#0,mul#1\]' [^:]*:[0-9]+: Error: only 'MUL VL' is permitted at operand 2 -- `ldr za\[w13,0\],\[sp,#0,mul#2\]' @@ -14,8 +14,8 @@ [^:]*:[0-9]+: Error: invalid addressing mode at operand 2 -- `str za\[w12,1\],\[sp,x0\]' [^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `str za\[w12,0\],\[sp,#1,mul vl\]' [^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `str za\[w13,9\],\[x17,#19,mul vl\]' -[^:]*:[0-9]+: Error: offset out of range at operand 1 -- `str za\[w13,21\],\[x17,#21,mul vl\]' -[^:]*:[0-9]+: Error: offset out of range at operand 1 -- `str za\[w15,32\],\[x17,#15,mul vl\]' +[^:]*:[0-9]+: Error: immediate offset out of range 0 to 15 at operand 1 -- `str za\[w13,21\],\[x17,#21,mul vl\]' +[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `str za\[w15,32\],\[x17,#15,mul vl\]' [^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 1 -- `str za\[w16,15\],\[sp,#15,mul vl\]' [^:]*:[0-9]+: Error: only 'MUL VL' is permitted at operand 2 -- `str za\[w12,0\],\[x0,#0,mul#1\]' [^:]*:[0-9]+: Error: only 'MUL VL' is permitted at operand 2 -- `str za\[w13,0\],\[sp,#0,mul#2\]' @@ -23,11 +23,11 @@ [^:]*:[0-9]+: Error: only 'MUL VL' is permitted at operand 2 -- `str za\[w15,15\],\[sp,#15,mul#4\]' [^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `ldr za\[w13,13\],\[x17,#23,mul vl\]' [^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `str za\[w13,13\],\[x17,#23,mul vl\]' -[^:]*:[0-9]+: Error: offset out of range at operand 1 -- `ldr za\[w13,23\],\[x17,#13,mul vl\]' -[^:]*:[0-9]+: Error: offset out of range at operand 1 -- `str za\[w13,23\],\[x17,#13,mul vl\]' -[^:]*:[0-9]+: Error: offset out of range at operand 1 -- `ldr za\[w13,16\],\[x17,#16,mul vl\]' -[^:]*:[0-9]+: Error: offset out of range at operand 1 -- `str za\[w13,16\],\[x17,#16,mul vl\]' -[^:]*:[0-9]+: Error: offset out of range at operand 1 -- `ldr za\[w13,-1\],\[x17,#1,mul vl\]' -[^:]*:[0-9]+: Error: offset out of range at operand 1 -- `str za\[w13,-1\],\[x17,#1,mul vl\]' +[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `ldr za\[w13,23\],\[x17,#13,mul vl\]' +[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `str za\[w13,23\],\[x17,#13,mul vl\]' +[^:]*:[0-9]+: Error: immediate offset out of range 0 to 15 at operand 1 -- `ldr za\[w13,16\],\[x17,#16,mul vl\]' +[^:]*:[0-9]+: Error: immediate offset out of range 0 to 15 at operand 1 -- `str za\[w13,16\],\[x17,#16,mul vl\]' +[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `ldr za\[w13,-1\],\[x17,#1,mul vl\]' +[^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `str za\[w13,-1\],\[x17,#1,mul vl\]' [^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `ldr za\[w13,1\],\[x17,#-1,mul vl\]' [^:]*:[0-9]+: Error: operand 2 must have the same immediate value as operand 1 -- `str za\[w13,1\],\[x17,#-1,mul vl\]' diff --git a/gas/testsuite/gas/aarch64/sme-9-illegal.l b/gas/testsuite/gas/aarch64/sme-9-illegal.l index 6bab29f..4d4520c 100644 --- a/gas/testsuite/gas/aarch64/sme-9-illegal.l +++ b/gas/testsuite/gas/aarch64/sme-9-illegal.l @@ -1,13 +1,21 @@ [^:]*: Assembler messages: -[^:]*:[0-9]+: Error: wrong predicate register element size, allowed b, h, s and d at operand 3 -- `psel p1,p15,p3.q\[w15\]' +[^:]*:[0-9]+: Error: expected ',' at operand 3 -- `psel p1,p15,p3.b\[w12\]' +[^:]*:[0-9]+: Error: expected ',' at operand 3 -- `psel p1,p15,p3.q\[w15\]' +[^:]*:[0-9]+: Error: operand mismatch -- `psel p1,p15,p3.q\[w15,#0\]' +[^:]*:[0-9]+: Info: did you mean this\? +[^:]*:[0-9]+: Info: psel p1, p15, p3.b\[w15, 0\] +[^:]*:[0-9]+: Info: other valid variant\(s\): +[^:]*:[0-9]+: Info: psel p1, p15, p3.h\[w15, 0\] +[^:]*:[0-9]+: Info: psel p1, p15, p3.s\[w15, 0\] +[^:]*:[0-9]+: Info: psel p1, p15, p3.d\[w15, 0\] [^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `psel p1,p15,p3.b\[w11\]' [^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `psel p8,p11,p15.h\[w16\]' [^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `psel p2,p7,p15.s\[w3\]' [^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `psel p13,p3,p1.d\[w17\]' -[^:]*:[0-9]+: Error: element index out of range for given variant at operand 3 -- `psel p5,p12,p9.b\[w15,#16\]' -[^:]*:[0-9]+: Error: element index out of range for given variant at operand 3 -- `psel p1,p8,p6.h\[w14,#8\]' -[^:]*:[0-9]+: Error: element index out of range for given variant at operand 3 -- `psel p8,p4,p15.s\[w13,#4\]' -[^:]*:[0-9]+: Error: element index out of range for given variant at operand 3 -- `psel p1,p1,p1.d\[w12,#2\]' +[^:]*:[0-9]+: Error: immediate offset out of range 0 to 15 at operand 3 -- `psel p5,p12,p9.b\[w15,#16\]' +[^:]*:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 3 -- `psel p1,p8,p6.h\[w14,#8\]' +[^:]*:[0-9]+: Error: immediate offset out of range 0 to 3 at operand 3 -- `psel p8,p4,p15.s\[w13,#4\]' +[^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 3 -- `psel p1,p1,p1.d\[w12,#2\]' [^:]*:[0-9]+: Error: operand mismatch -- `revd z0.q,p0/m,z0.b' [^:]*:[0-9]+: Info: did you mean this\? [^:]*:[0-9]+: Info: revd z0.q, p0/m, z0.q diff --git a/gas/testsuite/gas/aarch64/sme-9-illegal.s b/gas/testsuite/gas/aarch64/sme-9-illegal.s index 308d52c..88d25fc 100644 --- a/gas/testsuite/gas/aarch64/sme-9-illegal.s +++ b/gas/testsuite/gas/aarch64/sme-9-illegal.s @@ -1,6 +1,8 @@ /* Scalable Matrix Extension (SME). */ +psel p1, p15, p3.b[w12] psel p1, p15, p3.q[w15] +psel p1, p15, p3.q[w15, #0] psel p1, p15, p3.b[w11] psel p8, p11, p15.h[w16] psel p2, p7, p15.s[w3] diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index aeb3d9a..cc0ddf0 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -225,6 +225,7 @@ enum aarch64_operand_class AARCH64_OPND_CLASS_SIMD_REGLIST, AARCH64_OPND_CLASS_SVE_REG, AARCH64_OPND_CLASS_PRED_REG, + AARCH64_OPND_CLASS_ZA_ACCESS, AARCH64_OPND_CLASS_ADDRESS, AARCH64_OPND_CLASS_IMMEDIATE, AARCH64_OPND_CLASS_SYSTEM, diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c index 6e22690..3603f2c 100644 --- a/opcodes/aarch64-opc-2.c +++ b/opcodes/aarch64-opc-2.c @@ -236,12 +236,12 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_SVE_REG, "SVE_ZtxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "a list of SVE vector registers"}, {AARCH64_OPND_CLASS_SVE_REG, "SME_ZAda_2b", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZAda_2b}, "an SME ZA tile ZA0-ZA3"}, {AARCH64_OPND_CLASS_SVE_REG, "SME_ZAda_3b", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZAda_3b}, "an SME ZA tile ZA0-ZA7"}, - {AARCH64_OPND_CLASS_SVE_REG, "SME_ZA_HV_idx_src", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_10,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_5}, "an SME horizontal or vertical vector access register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SME_ZA_HV_idx_dest", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_10,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_2}, "an SME horizontal or vertical vector access register"}, + {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_src", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_10,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_5}, "an SME horizontal or vertical vector access register"}, + {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_dest", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_10,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_2}, "an SME horizontal or vertical vector access register"}, {AARCH64_OPND_CLASS_PRED_REG, "SME_Pm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Pm}, "an SVE predicate register"}, {AARCH64_OPND_CLASS_SVE_REG, "SME_list_of_64bit_tiles", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_zero_mask}, "a list of 64-bit ZA element tiles"}, - {AARCH64_OPND_CLASS_SVE_REG, "SME_ZA_HV_idx_ldstr", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_10,FLD_index2,FLD_SME_V,FLD_SME_Rv,FLD_imm4_2}, "an SME horizontal or vertical vector access register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SME_ZA_array", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rv,FLD_imm4_2}, "ZA array"}, + {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_ldstr", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_10,FLD_index2,FLD_SME_V,FLD_SME_Rv,FLD_imm4_2}, "an SME horizontal or vertical vector access register"}, + {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rv,FLD_imm4_2}, "ZA array"}, {AARCH64_OPND_CLASS_ADDRESS, "SME_ADDR_RI_U4xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm4_2}, "memory offset"}, {AARCH64_OPND_CLASS_ADDRESS, "SME_SM_ZA", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm}, "streaming mode"}, {AARCH64_OPND_CLASS_SVE_REG, "SME_PnT_Wm_imm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rm,FLD_SVE_Pn,FLD_SME_i1,FLD_SME_tszh,FLD_SME_tszl}, "Source scalable predicate register with index "}, diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index c92b4e8..746edde 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -1438,6 +1438,22 @@ set_other_error (aarch64_operand_error *mismatch_detail, int idx, set_error (mismatch_detail, AARCH64_OPDE_OTHER_ERROR, idx, error); } +/* Check that indexed ZA operand OPND has a vector select offset + in the range [0, MAX_VALUE]. */ + +static bool +check_za_access (const aarch64_opnd_info *opnd, + aarch64_operand_error *mismatch_detail, int idx, + int max_value) +{ + if (!value_in_range_p (opnd->indexed_za.index.imm, 0, max_value)) + { + set_offset_out_of_range_error (mismatch_detail, idx, 0, max_value); + return false; + } + return true; +} + /* General constraint checking based on operand code. Return 1 if OPNDS[IDX] meets the general constraint of operand code TYPE @@ -1574,11 +1590,40 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, } break; + case AARCH64_OPND_SME_PnT_Wm_imm: + size = aarch64_get_qualifier_esize (opnd->qualifier); + max_value = 16 / size - 1; + if (!check_za_access (opnd, mismatch_detail, idx, max_value)) + return 0; + break; + default: break; } break; + case AARCH64_OPND_CLASS_ZA_ACCESS: + switch (type) + { + case AARCH64_OPND_SME_ZA_HV_idx_src: + case AARCH64_OPND_SME_ZA_HV_idx_dest: + case AARCH64_OPND_SME_ZA_HV_idx_ldstr: + size = aarch64_get_qualifier_esize (opnd->qualifier); + max_value = 16 / size - 1; + if (!check_za_access (opnd, mismatch_detail, idx, max_value)) + return 0; + break; + + case AARCH64_OPND_SME_ZA_array: + if (!check_za_access (opnd, mismatch_detail, idx, 15)) + return 0; + break; + + default: + abort (); + } + break; + case AARCH64_OPND_CLASS_PRED_REG: if (opnd->reg.regno >= 8 && get_operand_fields_width (get_operand_from_code (type)) == 3) diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index ff0b04a..98b2b01 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -5909,32 +5909,29 @@ const struct aarch64_opcode aarch64_opcode_table[] = Y(SVE_REG, sve_reglist, "SVE_ZtxN", 0, F(FLD_SVE_Zt), \ "a list of SVE vector registers") \ Y(SVE_REG, regno, "SME_ZAda_2b", 0, F(FLD_SME_ZAda_2b), \ - "an SME ZA tile ZA0-ZA3") \ + "an SME ZA tile ZA0-ZA3") \ Y(SVE_REG, regno, "SME_ZAda_3b", 0, F(FLD_SME_ZAda_3b), \ - "an SME ZA tile ZA0-ZA7") \ - Y(SVE_REG, sme_za_hv_tiles, "SME_ZA_HV_idx_src", 0, \ - F(FLD_SME_size_10,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_5),\ - "an SME horizontal or vertical vector access register") \ - Y(SVE_REG, sme_za_hv_tiles, "SME_ZA_HV_idx_dest", 0, \ - F(FLD_SME_size_10,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_2),\ - "an SME horizontal or vertical vector access register") \ + "an SME ZA tile ZA0-ZA7") \ + Y(ZA_ACCESS, sme_za_hv_tiles, "SME_ZA_HV_idx_src", 0, \ + F(FLD_SME_size_10,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_5), \ + "an SME horizontal or vertical vector access register") \ + Y(ZA_ACCESS, sme_za_hv_tiles, "SME_ZA_HV_idx_dest", 0, \ + F(FLD_SME_size_10,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_2), \ + "an SME horizontal or vertical vector access register") \ Y(PRED_REG, regno, "SME_Pm", 0, F(FLD_SME_Pm), \ "an SVE predicate register") \ - Y(SVE_REG, imm, "SME_list_of_64bit_tiles", 0, \ - F(FLD_SME_zero_mask), "a list of 64-bit ZA element tiles") \ - Y(SVE_REG, sme_za_hv_tiles, "SME_ZA_HV_idx_ldstr", 0, \ + Y(SVE_REG, imm, "SME_list_of_64bit_tiles", 0, \ + F(FLD_SME_zero_mask), "a list of 64-bit ZA element tiles") \ + Y(ZA_ACCESS, sme_za_hv_tiles, "SME_ZA_HV_idx_ldstr", 0, \ F(FLD_SME_size_10,FLD_index2,FLD_SME_V,FLD_SME_Rv,FLD_imm4_2), \ - "an SME horizontal or vertical vector access register") \ - Y(SVE_REG, sme_za_array, "SME_ZA_array", 0, \ - F(FLD_SME_Rv,FLD_imm4_2), \ - "ZA array") \ + "an SME horizontal or vertical vector access register") \ + Y(ZA_ACCESS, sme_za_array, "SME_ZA_array", 0, \ + F(FLD_SME_Rv,FLD_imm4_2), "ZA array") \ Y(ADDRESS, sme_addr_ri_u4xvl, "SME_ADDR_RI_U4xVL", 0 << OPD_F_OD_LSB, \ - F(FLD_Rn,FLD_imm4_2), \ - "memory offset") \ - Y(ADDRESS, sme_sm_za, "SME_SM_ZA", 0, \ - F(FLD_CRm), \ - "streaming mode") \ - Y(SVE_REG, sme_pred_reg_with_index, "SME_PnT_Wm_imm", 0, \ + F(FLD_Rn,FLD_imm4_2), "memory offset") \ + Y(ADDRESS, sme_sm_za, "SME_SM_ZA", 0, \ + F(FLD_CRm), "streaming mode") \ + Y(SVE_REG, sme_pred_reg_with_index, "SME_PnT_Wm_imm", 0, \ F(FLD_SME_Rm,FLD_SVE_Pn,FLD_SME_i1,FLD_SME_tszh,FLD_SME_tszl), \ "Source scalable predicate register with index ") \ Y(IMMEDIATE, imm, "TME_UIMM16", 0, F(FLD_imm16), \ |