aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
Diffstat
-rw-r--r--bfd/elf32-hppa.c88
-rw-r--r--bfd/elf32-i386.c9
-rw-r--r--bfd/elf64-ppc.c9
-rw-r--r--bfd/elf64-x86-64.c9
-rw-r--r--bfd/elflink.c32
-rw-r--r--bfd/elfnn-loongarch.c28
-rw-r--r--bfd/version.h2
-rw-r--r--gas/config/tc-s390.c9
-rw-r--r--gas/doc/as.texi3
-rw-r--r--gas/doc/c-s390.texi8
-rw-r--r--gas/testsuite/gas/s390/s390.exp1
-rw-r--r--gas/testsuite/gas/s390/zarch-arch15.d106
-rw-r--r--gas/testsuite/gas/s390/zarch-arch15.s100
-rw-r--r--gas/testsuite/gas/s390/zarch-z10.d12
-rw-r--r--gas/testsuite/gas/s390/zarch-z10.s12
-rw-r--r--include/opcode/s390.h5
-rw-r--r--ld/testsuite/ld-elf/dl5.cc13
-rw-r--r--ld/testsuite/ld-elf/dl5.h10
-rw-r--r--ld/testsuite/ld-elf/dwarf.exp2
-rw-r--r--ld/testsuite/ld-elf/new.cc6
-rw-r--r--ld/testsuite/ld-elf/shared.exp2
-rw-r--r--ld/testsuite/ld-x86-64/x86-64.exp7
-rw-r--r--libctf/ctf-create.c8
-rw-r--r--opcodes/s390-dis.c14
-rw-r--r--opcodes/s390-mkopc.c15
-rw-r--r--opcodes/s390-opc.c70
-rw-r--r--opcodes/s390-opc.txt136
27 files changed, 571 insertions, 145 deletions
diff --git a/bfd/elf32-hppa.c b/bfd/elf32-hppa.c
index 99ec789..c2a7ad9 100644
--- a/bfd/elf32-hppa.c
+++ b/bfd/elf32-hppa.c
@@ -3432,48 +3432,62 @@ final_link_relocate (asection *input_section,
break;
}
- r_format = bfd_hppa_insn2fmt (input_bfd, insn);
- switch (r_format)
+ switch (r_type)
{
- case 10:
- case -10:
- if (val & 7)
- {
- _bfd_error_handler
- /* xgettext:c-format */
- (_("%pB(%pA+%#" PRIx64 "): displacement %#x for insn %#x "
- "is not a multiple of 8 (gp %#x)"),
- input_bfd,
- input_section,
- (uint64_t) offset,
- val,
- insn,
- (unsigned int) elf_gp (input_section->output_section->owner));
- bfd_set_error (bfd_error_bad_value);
- return bfd_reloc_notsupported;
- }
+ case R_PARISC_DIR32:
+ case R_PARISC_SECREL32:
+ case R_PARISC_SEGBASE:
+ case R_PARISC_SEGREL32:
+ case R_PARISC_PLABEL32:
+ /* These relocations apply to data. */
+ r_format = howto->bitsize;
break;
- case -11:
- case -16:
- if (val & 3)
+ default:
+ r_format = bfd_hppa_insn2fmt (input_bfd, insn);
+ switch (r_format)
{
- _bfd_error_handler
- /* xgettext:c-format */
- (_("%pB(%pA+%#" PRIx64 "): displacement %#x for insn %#x "
- "is not a multiple of 4 (gp %#x)"),
- input_bfd,
- input_section,
- (uint64_t) offset,
- val,
- insn,
- (unsigned int) elf_gp (input_section->output_section->owner));
- bfd_set_error (bfd_error_bad_value);
- return bfd_reloc_notsupported;
- }
- break;
+ case 10:
+ case -10:
+ if (val & 7)
+ {
+ _bfd_error_handler
+ /* xgettext:c-format */
+ (_("%pB(%pA+%#" PRIx64 "): displacement %#x for insn %#x "
+ "is not a multiple of 8 (gp %#x)"),
+ input_bfd,
+ input_section,
+ (uint64_t) offset,
+ val,
+ insn,
+ (unsigned int) elf_gp (input_section->output_section->owner));
+ bfd_set_error (bfd_error_bad_value);
+ return bfd_reloc_notsupported;
+ }
+ break;
- default:
+ case -11:
+ case -16:
+ if (val & 3)
+ {
+ _bfd_error_handler
+ /* xgettext:c-format */
+ (_("%pB(%pA+%#" PRIx64 "): displacement %#x for insn %#x "
+ "is not a multiple of 4 (gp %#x)"),
+ input_bfd,
+ input_section,
+ (uint64_t) offset,
+ val,
+ insn,
+ (unsigned int) elf_gp (input_section->output_section->owner));
+ bfd_set_error (bfd_error_bad_value);
+ return bfd_reloc_notsupported;
+ }
+ break;
+
+ default:
+ break;
+ }
break;
}
insn = hppa_rebuild_insn (insn, val, r_format);
diff --git a/bfd/elf32-i386.c b/bfd/elf32-i386.c
index e2f88a1..f11500f 100644
--- a/bfd/elf32-i386.c
+++ b/bfd/elf32-i386.c
@@ -1335,6 +1335,15 @@ elf_i386_convert_load_reloc (bfd *abfd, Elf_Internal_Shdr *symtab_hdr,
if (opcode == 0xff)
{
+ switch (modrm & 0x38)
+ {
+ case 0x10: /* CALL */
+ case 0x20: /* JMP */
+ break;
+ default:
+ return true;
+ }
+
/* We have "call/jmp *foo@GOT[(%reg)]". */
if ((h->root.type == bfd_link_hash_defined
|| h->root.type == bfd_link_hash_defweak)
diff --git a/bfd/elf64-ppc.c b/bfd/elf64-ppc.c
index e95f9fb..720d6ac 100644
--- a/bfd/elf64-ppc.c
+++ b/bfd/elf64-ppc.c
@@ -4915,6 +4915,15 @@ ppc64_elf_check_relocs (bfd *abfd, struct bfd_link_info *info,
tls_type = 0;
switch (r_type)
{
+ case R_PPC64_PLTSEQ:
+ case R_PPC64_PLTSEQ_NOTOC:
+ /* Inline plt call code emitted by gcc doesn't support
+ modifying the tls_index words to short-circuit
+ __tls_get_addr calls. See PR32387. */
+ if (h != NULL && (h == tga || h == dottga))
+ htab->params->tls_get_addr_opt = 0;
+ break;
+
case R_PPC64_TLSGD:
case R_PPC64_TLSLD:
/* These special tls relocs tie a call to __tls_get_addr with
diff --git a/bfd/elf64-x86-64.c b/bfd/elf64-x86-64.c
index 2ed120a..abf97b2 100644
--- a/bfd/elf64-x86-64.c
+++ b/bfd/elf64-x86-64.c
@@ -1851,6 +1851,15 @@ elf_x86_64_convert_load_reloc (bfd *abfd,
/* Convert R_X86_64_GOTPCRELX and R_X86_64_REX_GOTPCRELX to
R_X86_64_PC32. */
modrm = bfd_get_8 (abfd, contents + roff - 1);
+ switch (modrm & 0x38)
+ {
+ case 0x10: /* CALL */
+ case 0x20: /* JMP */
+ break;
+ default:
+ return true;
+ }
+
if (modrm == 0x25)
{
/* Convert to "jmp foo nop". */
diff --git a/bfd/elflink.c b/bfd/elflink.c
index c2494b3..0fd06d1 100644
--- a/bfd/elflink.c
+++ b/bfd/elflink.c
@@ -2206,16 +2206,19 @@ _bfd_elf_export_symbol (struct elf_link_hash_entry *h, void *data)
/* Return the glibc version reference if VERSION_DEP is added to the
list of glibc version dependencies successfully. VERSION_DEP will
- be put into the .gnu.version_r section. */
+ be put into the .gnu.version_r section. GLIBC_MINOR_BASE is the
+ pointer to the glibc minor base version. */
static Elf_Internal_Verneed *
elf_link_add_glibc_verneed (struct elf_find_verdep_info *rinfo,
Elf_Internal_Verneed *glibc_verref,
- const char *version_dep)
+ const char *version_dep,
+ int *glibc_minor_base)
{
Elf_Internal_Verneed *t;
Elf_Internal_Vernaux *a;
size_t amt;
+ int minor_version = -1;
if (glibc_verref != NULL)
{
@@ -2231,8 +2234,6 @@ elf_link_add_glibc_verneed (struct elf_find_verdep_info *rinfo,
}
else
{
- bool is_glibc;
-
for (t = elf_tdata (rinfo->info->output_bfd)->verref;
t != NULL;
t = t->vn_nextref)
@@ -2246,7 +2247,6 @@ elf_link_add_glibc_verneed (struct elf_find_verdep_info *rinfo,
if (t == NULL)
return t;
- is_glibc = false;
for (a = t->vn_auxptr; a != NULL; a = a->vna_nextptr)
{
/* Return if VERSION_DEP dependency has been added. */
@@ -2255,12 +2255,24 @@ elf_link_add_glibc_verneed (struct elf_find_verdep_info *rinfo,
return t;
/* Check if libc.so provides GLIBC_2.XX version. */
- if (!is_glibc && startswith (a->vna_nodename, "GLIBC_2."))
- is_glibc = true;
+ if (startswith (a->vna_nodename, "GLIBC_2."))
+ {
+ minor_version = strtol (a->vna_nodename + 8, NULL, 10);
+ if (minor_version < *glibc_minor_base)
+ *glibc_minor_base = minor_version;
+ }
}
/* Skip if it isn't linked against glibc. */
- if (!is_glibc)
+ if (minor_version < 0)
+ return NULL;
+ }
+
+ /* Skip if 2.GLIBC_MINOR_BASE includes VERSION_DEP. */
+ if (startswith (version_dep, "GLIBC_2."))
+ {
+ minor_version = strtol (version_dep + 8, NULL, 10);
+ if (minor_version <= *glibc_minor_base)
return NULL;
}
@@ -2292,10 +2304,12 @@ _bfd_elf_link_add_glibc_version_dependency
const char *version_dep[])
{
Elf_Internal_Verneed *t = NULL;
+ int glibc_minor_base = INT_MAX;
do
{
- t = elf_link_add_glibc_verneed (rinfo, t, *version_dep);
+ t = elf_link_add_glibc_verneed (rinfo, t, *version_dep,
+ &glibc_minor_base);
/* Return if there is no glibc version reference. */
if (t == NULL)
return;
diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c
index b6e62f0..a7daea6 100644
--- a/bfd/elfnn-loongarch.c
+++ b/bfd/elfnn-loongarch.c
@@ -84,6 +84,14 @@ struct _bfd_loongarch_elf_obj_tdata
&& elf_tdata (bfd) != NULL \
&& elf_object_id (bfd) == LARCH_ELF_DATA)
+static bool
+elfNN_loongarch_object (bfd *abfd)
+{
+ return bfd_elf_allocate_object (abfd,
+ sizeof (struct _bfd_loongarch_elf_obj_tdata),
+ LARCH_ELF_DATA);
+}
+
struct loongarch_elf_link_hash_table
{
struct elf_link_hash_table elf;
@@ -656,7 +664,14 @@ loongarch_can_trans_tls (bfd *input_bfd,
&& ELFNN_R_TYPE (rel[1].r_info) == R_LARCH_RELAX))
return false;
- symbol_tls_type = _bfd_loongarch_elf_tls_type (input_bfd, h, r_symndx);
+ /* Obtaining tls got type here may occur before
+ loongarch_elf_record_tls_and_got_reference, so it is necessary
+ to ensure that tls got type has been initialized, otherwise it
+ is set to GOT_UNKNOWN. */
+ symbol_tls_type = GOT_UNKNOWN;
+ if (_bfd_loongarch_elf_local_got_tls_type (input_bfd) || h)
+ symbol_tls_type = _bfd_loongarch_elf_tls_type (input_bfd, h, r_symndx);
+
reloc_got_type = loongarch_reloc_got_type (r_type);
if (symbol_tls_type == GOT_TLS_IE && GOT_TLS_GD_ANY_P (reloc_got_type))
@@ -2673,9 +2688,14 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
bfd_vma relocation, off, ie_off, desc_off;
int i, j;
+ /* When an unrecognized relocation is encountered, which usually
+ occurs when using a newer assembler but an older linker, an error
+ should be reported instead of continuing to the next relocation. */
howto = loongarch_elf_rtype_to_howto (input_bfd, r_type);
- if (howto == NULL || r_type == R_LARCH_GNU_VTINHERIT
- || r_type == R_LARCH_GNU_VTENTRY)
+ if (howto == NULL)
+ return _bfd_unrecognized_reloc (input_bfd, input_section, r_type);
+
+ if (r_type == R_LARCH_GNU_VTINHERIT || r_type == R_LARCH_GNU_VTENTRY)
continue;
/* This is a final link. */
@@ -5331,6 +5351,8 @@ elf_loongarch64_hash_symbol (struct elf_link_hash_entry *h)
#define bfd_elfNN_bfd_reloc_name_lookup loongarch_reloc_name_lookup
#define elf_info_to_howto_rel NULL /* Fall through to elf_info_to_howto. */
#define elf_info_to_howto loongarch_info_to_howto_rela
+#define bfd_elfNN_mkobject \
+ elfNN_loongarch_object
#define bfd_elfNN_bfd_merge_private_bfd_data \
elfNN_loongarch_merge_private_bfd_data
diff --git a/bfd/version.h b/bfd/version.h
index f807e57..156818e 100644
--- a/bfd/version.h
+++ b/bfd/version.h
@@ -16,7 +16,7 @@
In releases, the date is not included in either version strings or
sonames. */
-#define BFD_VERSION_DATE 20240627
+#define BFD_VERSION_DATE 20240723
#define BFD_VERSION @bfd_version@
#define BFD_VERSION_STRING @bfd_version_package@ @bfd_version_string@
#define REPORT_BUGS_TO @report_bugs_to@
diff --git a/gas/config/tc-s390.c b/gas/config/tc-s390.c
index 09a903a..719cb93 100644
--- a/gas/config/tc-s390.c
+++ b/gas/config/tc-s390.c
@@ -292,6 +292,8 @@ s390_parse_cpu (const char *arg,
{ STRING_COMMA_LEN ("z15"), STRING_COMMA_LEN ("arch13"),
S390_INSTR_FLAG_HTM | S390_INSTR_FLAG_VX },
{ STRING_COMMA_LEN ("z16"), STRING_COMMA_LEN ("arch14"),
+ S390_INSTR_FLAG_HTM | S390_INSTR_FLAG_VX },
+ { STRING_COMMA_LEN ("z17"), STRING_COMMA_LEN ("arch15"),
S390_INSTR_FLAG_HTM | S390_INSTR_FLAG_VX }
};
static struct
@@ -690,13 +692,6 @@ s390_insert_operand (unsigned char *insn,
uval &= 0xf;
}
- if (operand->flags & S390_OPERAND_OR1)
- uval |= 1;
- if (operand->flags & S390_OPERAND_OR2)
- uval |= 2;
- if (operand->flags & S390_OPERAND_OR8)
- uval |= 8;
-
/* Duplicate the GPR/VR operand at bit pos 12 to 16. */
if (operand->flags & S390_OPERAND_CP16)
{
diff --git a/gas/doc/as.texi b/gas/doc/as.texi
index 50c0543..af6338d 100644
--- a/gas/doc/as.texi
+++ b/gas/doc/as.texi
@@ -1956,7 +1956,8 @@ Specify which s390 processor variant is the target, @samp{g5} (or
@samp{arch6}), @samp{z9-109}, @samp{z9-ec} (or @samp{arch7}), @samp{z10} (or
@samp{arch8}), @samp{z196} (or @samp{arch9}), @samp{zEC12} (or @samp{arch10}),
@samp{z13} (or @samp{arch11}), @samp{z14} (or @samp{arch12}), @samp{z15}
-(or @samp{arch13}), or @samp{z16} (or @samp{arch14}).
+(or @samp{arch13}), @samp{z16} (or @samp{arch14}), or @samp{z17} (or
+@samp{arch15}).
@item -mregnames
@itemx -mno-regnames
Allow or disallow symbolic names for registers.
diff --git a/gas/doc/c-s390.texi b/gas/doc/c-s390.texi
index f73dfde..2ddfc55 100644
--- a/gas/doc/c-s390.texi
+++ b/gas/doc/c-s390.texi
@@ -18,7 +18,8 @@ and eleven chip levels. The architecture modes are the Enterprise System
Architecture (ESA) and the newer z/Architecture mode. The chip levels
are g5 (or arch3), g6, z900 (or arch5), z990 (or arch6), z9-109, z9-ec
(or arch7), z10 (or arch8), z196 (or arch9), zEC12 (or arch10), z13
-(or arch11), z14 (or arch12), z15 (or arch13), or z16 (or arch14).
+(or arch11), z14 (or arch12), z15 (or arch13), z16 (or arch14), or
+z17 (arch15).
@menu
* s390 Options:: Command-line Options.
@@ -71,8 +72,9 @@ are recognized:
@code{zEC12} (or @code{arch10}),
@code{z13} (or @code{arch11}),
@code{z14} (or @code{arch12}),
-@code{z15} (or @code{arch13}), and
-@code{z16} (or @code{arch14}).
+@code{z15} (or @code{arch13}),
+@code{z16} (or @code{arch14}), and
+@code{z17} (or @code{arch15}).
Assembling an instruction that is not supported on the target
processor results in an error message.
diff --git a/gas/testsuite/gas/s390/s390.exp b/gas/testsuite/gas/s390/s390.exp
index 86e2dd4..c50f695 100644
--- a/gas/testsuite/gas/s390/s390.exp
+++ b/gas/testsuite/gas/s390/s390.exp
@@ -33,6 +33,7 @@ if [expr [istarget "s390-*-*"] || [istarget "s390x-*-*"]] then {
run_dump_test "zarch-arch12" "{as -m64} {as -march=arch12}"
run_dump_test "zarch-arch13" "{as -m64} {as -march=arch13}"
run_dump_test "zarch-arch14" "{as -m64} {as -march=arch14}"
+ run_dump_test "zarch-arch15" "{as -m64} {as -march=arch15}"
run_dump_test "zarch-reloc" "{as -m64}"
run_dump_test "zarch-operands" "{as -m64} {as -march=z9-109}"
run_dump_test "zarch-machine" "{as -m64} {as -march=z900}"
diff --git a/gas/testsuite/gas/s390/zarch-arch15.d b/gas/testsuite/gas/s390/zarch-arch15.d
new file mode 100644
index 0000000..9cd99b7
--- /dev/null
+++ b/gas/testsuite/gas/s390/zarch-arch15.d
@@ -0,0 +1,106 @@
+#name: s390x opcode
+#objdump: -dr
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+.* <foo>:
+.*: e7 f1 4d 00 87 89 [ ]*vblend %v15,%v17,%v20,%v24,13
+.*: e7 f1 40 00 87 89 [ ]*vblendb %v15,%v17,%v20,%v24
+.*: e7 f1 41 00 87 89 [ ]*vblendh %v15,%v17,%v20,%v24
+.*: e7 f1 42 00 87 89 [ ]*vblendf %v15,%v17,%v20,%v24
+.*: e7 f1 43 00 87 89 [ ]*vblendg %v15,%v17,%v20,%v24
+.*: e7 f1 44 00 87 89 [ ]*vblendq %v15,%v17,%v20,%v24
+.*: e7 f1 40 fd 87 88 [ ]*veval %v15,%v17,%v20,%v24,253
+.*: e7 f1 00 00 d4 54 [ ]*vgem %v15,%v17,13
+.*: e7 f1 00 00 04 54 [ ]*vgemb %v15,%v17
+.*: e7 f1 00 00 14 54 [ ]*vgemh %v15,%v17
+.*: e7 f1 00 00 24 54 [ ]*vgemf %v15,%v17
+.*: e7 f1 00 00 34 54 [ ]*vgemg %v15,%v17
+.*: e7 f1 00 00 44 54 [ ]*vgemq %v15,%v17
+.*: e7 f1 00 00 34 d7 [ ]*vuphg %v15,%v17
+.*: e7 f1 00 00 34 d5 [ ]*vuplhg %v15,%v17
+.*: e7 f1 00 00 34 d6 [ ]*vuplg %v15,%v17
+.*: e7 f1 00 00 34 d4 [ ]*vupllg %v15,%v17
+.*: e7 f1 40 00 46 f2 [ ]*vavgq %v15,%v17,%v20
+.*: e7 f1 40 00 46 f0 [ ]*vavglq %v15,%v17,%v20
+.*: e7 f1 00 00 44 db [ ]*vecq %v15,%v17
+.*: e7 f1 00 00 44 d9 [ ]*veclq %v15,%v17
+.*: e7 f1 40 00 46 f8 [ ]*vceqq %v15,%v17,%v20
+.*: e7 f1 40 10 46 f8 [ ]*vceqqs %v15,%v17,%v20
+.*: e7 f1 40 00 46 fb [ ]*vchq %v15,%v17,%v20
+.*: e7 f1 40 10 46 fb [ ]*vchqs %v15,%v17,%v20
+.*: e7 f1 40 00 46 f9 [ ]*vchlq %v15,%v17,%v20
+.*: e7 f1 40 10 46 f9 [ ]*vchlqs %v15,%v17,%v20
+.*: e7 f1 00 00 44 53 [ ]*vclzq %v15,%v17
+.*: e7 f1 00 00 44 52 [ ]*vctzq %v15,%v17
+.*: e7 f1 00 00 44 de [ ]*vlcq %v15,%v17
+.*: e7 f1 00 00 44 df [ ]*vlpq %v15,%v17
+.*: e7 f1 40 00 46 ff [ ]*vmxq %v15,%v17,%v20
+.*: e7 f1 40 00 46 fd [ ]*vmxlq %v15,%v17,%v20
+.*: e7 f1 40 00 46 fe [ ]*vmnq %v15,%v17,%v20
+.*: e7 f1 40 00 46 fc [ ]*vmnlq %v15,%v17,%v20
+.*: e7 f1 43 00 87 aa [ ]*vmalg %v15,%v17,%v20,%v24
+.*: e7 f1 44 00 87 aa [ ]*vmalq %v15,%v17,%v20,%v24
+.*: e7 f1 43 00 87 ab [ ]*vmahg %v15,%v17,%v20,%v24
+.*: e7 f1 44 00 87 ab [ ]*vmahq %v15,%v17,%v20,%v24
+.*: e7 f1 43 00 87 a9 [ ]*vmalhg %v15,%v17,%v20,%v24
+.*: e7 f1 44 00 87 a9 [ ]*vmalhq %v15,%v17,%v20,%v24
+.*: e7 f1 43 00 87 ae [ ]*vmaeg %v15,%v17,%v20,%v24
+.*: e7 f1 43 00 87 ac [ ]*vmaleg %v15,%v17,%v20,%v24
+.*: e7 f1 43 00 87 af [ ]*vmaog %v15,%v17,%v20,%v24
+.*: e7 f1 43 00 87 ad [ ]*vmalog %v15,%v17,%v20,%v24
+.*: e7 f1 40 00 36 a3 [ ]*vmhg %v15,%v17,%v20
+.*: e7 f1 40 00 46 a3 [ ]*vmhq %v15,%v17,%v20
+.*: e7 f1 40 00 36 a1 [ ]*vmlhg %v15,%v17,%v20
+.*: e7 f1 40 00 46 a1 [ ]*vmlhq %v15,%v17,%v20
+.*: e7 f1 40 00 36 a2 [ ]*vmlg %v15,%v17,%v20
+.*: e7 f1 40 00 46 a2 [ ]*vmlq %v15,%v17,%v20
+.*: e7 f1 40 00 36 a6 [ ]*vmeg %v15,%v17,%v20
+.*: e7 f1 40 00 36 a4 [ ]*vmleg %v15,%v17,%v20
+.*: e7 f1 40 00 36 a7 [ ]*vmog %v15,%v17,%v20
+.*: e7 f1 40 00 36 a5 [ ]*vmlog %v15,%v17,%v20
+.*: e7 f1 40 0c d6 b2 [ ]*vd %v15,%v17,%v20,13,12
+.*: e7 f1 40 0d 26 b2 [ ]*vdf %v15,%v17,%v20,13
+.*: e7 f1 40 0d 36 b2 [ ]*vdg %v15,%v17,%v20,13
+.*: e7 f1 40 0d 46 b2 [ ]*vdq %v15,%v17,%v20,13
+.*: e7 f1 40 0c d6 b0 [ ]*vdl %v15,%v17,%v20,13,12
+.*: e7 f1 40 0d 26 b0 [ ]*vdlf %v15,%v17,%v20,13
+.*: e7 f1 40 0d 36 b0 [ ]*vdlg %v15,%v17,%v20,13
+.*: e7 f1 40 0d 46 b0 [ ]*vdlq %v15,%v17,%v20,13
+.*: e7 f1 40 0c d6 b3 [ ]*vr %v15,%v17,%v20,13,12
+.*: e7 f1 40 0d 26 b3 [ ]*vrf %v15,%v17,%v20,13
+.*: e7 f1 40 0d 36 b3 [ ]*vrg %v15,%v17,%v20,13
+.*: e7 f1 40 0d 46 b3 [ ]*vrq %v15,%v17,%v20,13
+.*: e7 f1 40 0c d6 b1 [ ]*vrl %v15,%v17,%v20,13,12
+.*: e7 f1 40 0d 26 b1 [ ]*vrlf %v15,%v17,%v20,13
+.*: e7 f1 40 0d 36 b1 [ ]*vrlg %v15,%v17,%v20,13
+.*: e7 f1 40 0d 46 b1 [ ]*vrlq %v15,%v17,%v20,13
+.*: b9 68 00 69 [ ]*clzg %r6,%r9
+.*: b9 69 00 69 [ ]*ctzg %r6,%r9
+.*: e3 69 b8 f0 fd 60 [ ]*lxab %r6,-10000\(%r9,%r11\)
+.*: e3 69 b8 f0 fd 62 [ ]*lxah %r6,-10000\(%r9,%r11\)
+.*: e3 69 b8 f0 fd 64 [ ]*lxaf %r6,-10000\(%r9,%r11\)
+.*: e3 69 b8 f0 fd 66 [ ]*lxag %r6,-10000\(%r9,%r11\)
+.*: e3 69 b8 f0 fd 68 [ ]*lxaq %r6,-10000\(%r9,%r11\)
+.*: e3 69 b8 f0 fd 61 [ ]*llxab %r6,-10000\(%r9,%r11\)
+.*: e3 69 b8 f0 fd 63 [ ]*llxah %r6,-10000\(%r9,%r11\)
+.*: e3 69 b8 f0 fd 65 [ ]*llxaf %r6,-10000\(%r9,%r11\)
+.*: e3 69 b8 f0 fd 67 [ ]*llxag %r6,-10000\(%r9,%r11\)
+.*: e3 69 b8 f0 fd 69 [ ]*llxaq %r6,-10000\(%r9,%r11\)
+.*: b9 6c b0 69 [ ]*bextg %r6,%r9,%r11
+.*: b9 6d b0 69 [ ]*bdepg %r6,%r9,%r11
+.*: b9 3e 00 69 [ ]*kimd %r6,%r9
+.*: b9 3e d0 69 [ ]*kimd %r6,%r9,13
+.*: b9 3f 00 69 [ ]*klmd %r6,%r9
+.*: b9 3f d0 69 [ ]*klmd %r6,%r9,13
+.*: e6 f1 00 d0 04 4e [ ]*vcvbq %v15,%v17,13
+.*: e6 f1 00 cf d4 4a [ ]*vcvdq %v15,%v17,253,12
+.*: e6 0f 00 00 00 5f [ ]*vtp %v15
+.*: e6 0f 0f ff d0 5f [ ]*vtp %v15,65533
+.*: e6 0f 1f ff d2 7f [ ]*vtz %v15,%v17,65533
+.*: c8 36 10 0a 20 14 [ ]*cal %r3,10\(%r1\),20\(%r2\)
+.*: c8 37 10 0a 20 14 [ ]*calg %r3,10\(%r1\),20\(%r2\)
+.*: c8 3f 10 0a 20 14 [ ]*calgf %r3,10\(%r1\),20\(%r2\)
+.*: eb 13 28 f0 fd 16 [ ]*pfcr %r1,%r3,-10000\(%r2\)
diff --git a/gas/testsuite/gas/s390/zarch-arch15.s b/gas/testsuite/gas/s390/zarch-arch15.s
new file mode 100644
index 0000000..d9b8965
--- /dev/null
+++ b/gas/testsuite/gas/s390/zarch-arch15.s
@@ -0,0 +1,100 @@
+.text
+foo:
+ vblend %v15,%v17,%v20,%v24,13
+ vblendb %v15,%v17,%v20,%v24
+ vblendh %v15,%v17,%v20,%v24
+ vblendf %v15,%v17,%v20,%v24
+ vblendg %v15,%v17,%v20,%v24
+ vblendq %v15,%v17,%v20,%v24
+ veval %v15,%v17,%v20,%v24,253
+ vgem %v15,%v17,13
+ vgemb %v15,%v17
+ vgemh %v15,%v17
+ vgemf %v15,%v17
+ vgemg %v15,%v17
+ vgemq %v15,%v17
+ vuphg %v15,%v17
+ vuplhg %v15,%v17
+ vuplg %v15,%v17
+ vupllg %v15,%v17
+ vavgq %v15,%v17,%v20
+ vavglq %v15,%v17,%v20
+ vecq %v15,%v17
+ veclq %v15,%v17
+ vceqq %v15,%v17,%v20
+ vceqqs %v15,%v17,%v20
+ vchq %v15,%v17,%v20
+ vchqs %v15,%v17,%v20
+ vchlq %v15,%v17,%v20
+ vchlqs %v15,%v17,%v20
+ vclzq %v15,%v17
+ vctzq %v15,%v17
+ vlcq %v15,%v17
+ vlpq %v15,%v17
+ vmxq %v15,%v17,%v20
+ vmxlq %v15,%v17,%v20
+ vmnq %v15,%v17,%v20
+ vmnlq %v15,%v17,%v20
+ vmalg %v15,%v17,%v20,%v24
+ vmalq %v15,%v17,%v20,%v24
+ vmahg %v15,%v17,%v20,%v24
+ vmahq %v15,%v17,%v20,%v24
+ vmalhg %v15,%v17,%v20,%v24
+ vmalhq %v15,%v17,%v20,%v24
+ vmaeg %v15,%v17,%v20,%v24
+ vmaleg %v15,%v17,%v20,%v24
+ vmaog %v15,%v17,%v20,%v24
+ vmalog %v15,%v17,%v20,%v24
+ vmhg %v15,%v17,%v20
+ vmhq %v15,%v17,%v20
+ vmlhg %v15,%v17,%v20
+ vmlhq %v15,%v17,%v20
+ vmlg %v15,%v17,%v20
+ vmlq %v15,%v17,%v20
+ vmeg %v15,%v17,%v20
+ vmleg %v15,%v17,%v20
+ vmog %v15,%v17,%v20
+ vmlog %v15,%v17,%v20
+ vd %v15,%v17,%v20,13,12
+ vdf %v15,%v17,%v20,13
+ vdg %v15,%v17,%v20,13
+ vdq %v15,%v17,%v20,13
+ vdl %v15,%v17,%v20,13,12
+ vdlf %v15,%v17,%v20,13
+ vdlg %v15,%v17,%v20,13
+ vdlq %v15,%v17,%v20,13
+ vr %v15,%v17,%v20,13,12
+ vrf %v15,%v17,%v20,13
+ vrg %v15,%v17,%v20,13
+ vrq %v15,%v17,%v20,13
+ vrl %v15,%v17,%v20,13,12
+ vrlf %v15,%v17,%v20,13
+ vrlg %v15,%v17,%v20,13
+ vrlq %v15,%v17,%v20,13
+ clzg %r6,%r9
+ ctzg %r6,%r9
+ lxab %r6,-10000(%r9,%r11)
+ lxah %r6,-10000(%r9,%r11)
+ lxaf %r6,-10000(%r9,%r11)
+ lxag %r6,-10000(%r9,%r11)
+ lxaq %r6,-10000(%r9,%r11)
+ llxab %r6,-10000(%r9,%r11)
+ llxah %r6,-10000(%r9,%r11)
+ llxaf %r6,-10000(%r9,%r11)
+ llxag %r6,-10000(%r9,%r11)
+ llxaq %r6,-10000(%r9,%r11)
+ bextg %r6,%r9,%r11
+ bdepg %r6,%r9,%r11
+ kimd %r6,%r9
+ kimd %r6,%r9,13
+ klmd %r6,%r9
+ klmd %r6,%r9,13
+ vcvbq %v15,%v17,13
+ vcvdq %v15,%v17,253,12
+ vtp %v15
+ vtp %v15,65533
+ vtz %v15,%v17,65533
+ cal %r3,10(%r1),20(%r2)
+ calg %r3,10(%r1),20(%r2)
+ calgf %r3,10(%r1),20(%r2)
+ pfcr %r1,%r3,-10000(%r2)
diff --git a/gas/testsuite/gas/s390/zarch-z10.d b/gas/testsuite/gas/s390/zarch-z10.d
index 4a05153..beb0578 100644
--- a/gas/testsuite/gas/s390/zarch-z10.d
+++ b/gas/testsuite/gas/s390/zarch-z10.d
@@ -359,20 +359,20 @@ Disassembly of section .text:
.*: c2 60 ff fe 79 60 [ ]*msgfi %r6,-100000
.*: e3 a6 75 b3 01 36 [ ]*pfd 10,5555\(%r6,%r7\)
*([\da-f]+): c6 a2 00 00 00 00 [ ]*pfdrl 10,\1 <foo\+0x\1>
-.*: ec 67 d2 dc e6 54 [ ]*rnsbg %r6,%r7,210,220,230
-.*: ec 67 d2 dc 00 54 [ ]*rnsbg %r6,%r7,210,220
+.*: ec 67 6e dc e6 54 [ ]*rnsbg %r6,%r7,110,220,230
+.*: ec 67 6e dc 00 54 [ ]*rnsbg %r6,%r7,110,220
.*: ec 67 92 dc e6 54 [ ]*rnsbgt %r6,%r7,18,220,230
.*: ec 67 92 dc 00 54 [ ]*rnsbgt %r6,%r7,18,220
.*: ec 67 92 1c 26 54 [ ]*rnsbgt %r6,%r7,18,28,38
.*: ec 67 92 1c 00 54 [ ]*rnsbgt %r6,%r7,18,28
-.*: ec 67 d2 dc e6 57 [ ]*rxsbg %r6,%r7,210,220,230
-.*: ec 67 d2 dc 00 57 [ ]*rxsbg %r6,%r7,210,220
+.*: ec 67 6e dc e6 57 [ ]*rxsbg %r6,%r7,110,220,230
+.*: ec 67 6e dc 00 57 [ ]*rxsbg %r6,%r7,110,220
.*: ec 67 92 dc e6 57 [ ]*rxsbgt %r6,%r7,18,220,230
.*: ec 67 92 dc 00 57 [ ]*rxsbgt %r6,%r7,18,220
.*: ec 67 92 1c 26 57 [ ]*rxsbgt %r6,%r7,18,28,38
.*: ec 67 92 1c 00 57 [ ]*rxsbgt %r6,%r7,18,28
-.*: ec 67 d2 dc e6 56 [ ]*rosbg %r6,%r7,210,220,230
-.*: ec 67 d2 dc 00 56 [ ]*rosbg %r6,%r7,210,220
+.*: ec 67 6e dc e6 56 [ ]*rosbg %r6,%r7,110,220,230
+.*: ec 67 6e dc 00 56 [ ]*rosbg %r6,%r7,110,220
.*: ec 67 92 dc e6 56 [ ]*rosbgt %r6,%r7,18,220,230
.*: ec 67 92 dc 00 56 [ ]*rosbgt %r6,%r7,18,220
.*: ec 67 92 1c 26 56 [ ]*rosbgt %r6,%r7,18,28,38
diff --git a/gas/testsuite/gas/s390/zarch-z10.s b/gas/testsuite/gas/s390/zarch-z10.s
index 45bb894..a624588 100644
--- a/gas/testsuite/gas/s390/zarch-z10.s
+++ b/gas/testsuite/gas/s390/zarch-z10.s
@@ -353,20 +353,20 @@ foo:
msgfi %r6,-100000
pfd 10,5555(%r6,%r7)
pfdrl 10,.
- rnsbg %r6,%r7,210,220,230
- rnsbg %r6,%r7,210,220
+ rnsbg %r6,%r7,110,220,230
+ rnsbg %r6,%r7,110,220
rnsbg %r6,%r7,146,220,230
rnsbg %r6,%r7,146,220
rnsbgt %r6,%r7,18,28,38
rnsbgt %r6,%r7,18,28
- rxsbg %r6,%r7,210,220,230
- rxsbg %r6,%r7,210,220
+ rxsbg %r6,%r7,110,220,230
+ rxsbg %r6,%r7,110,220
rxsbg %r6,%r7,146,220,230
rxsbg %r6,%r7,146,220
rxsbgt %r6,%r7,18,28,38
rxsbgt %r6,%r7,18,28
- rosbg %r6,%r7,210,220,230
- rosbg %r6,%r7,210,220
+ rosbg %r6,%r7,110,220,230
+ rosbg %r6,%r7,110,220
rosbg %r6,%r7,146,220,230
rosbg %r6,%r7,146,220
rosbgt %r6,%r7,18,28,38
diff --git a/include/opcode/s390.h b/include/opcode/s390.h
index 5656368..9aed391 100644
--- a/include/opcode/s390.h
+++ b/include/opcode/s390.h
@@ -45,6 +45,7 @@ enum s390_opcode_cpu_val
S390_OPCODE_ARCH12,
S390_OPCODE_ARCH13,
S390_OPCODE_ARCH14,
+ S390_OPCODE_ARCH15,
S390_OPCODE_MAXCPU
};
@@ -190,8 +191,4 @@ extern const struct s390_operand s390_operands[];
#define S390_OPERAND_CP16 0x1000
-#define S390_OPERAND_OR1 0x2000
-#define S390_OPERAND_OR2 0x4000
-#define S390_OPERAND_OR8 0x8000
-
#endif /* S390_H */
diff --git a/ld/testsuite/ld-elf/dl5.cc b/ld/testsuite/ld-elf/dl5.cc
index cc40455..1cd33c0 100644
--- a/ld/testsuite/ld-elf/dl5.cc
+++ b/ld/testsuite/ld-elf/dl5.cc
@@ -1,6 +1,7 @@
#include <stdio.h>
#include <stdlib.h>
#include <new>
+#include "dl5.h"
int pass = 0;
@@ -30,22 +31,14 @@ operator delete (void *ptr) throw ()
free (ptr);
}
-class A
-{
-public:
- A() {}
- ~A() { }
- int a;
- int b;
-};
-
-
int
main (void)
{
A *bb = new A[10];
+ foo (bb);
delete [] bb;
bb = new (std::nothrow) A [10];
+ foo (bb);
delete [] bb;
if (pass == 4)
diff --git a/ld/testsuite/ld-elf/dl5.h b/ld/testsuite/ld-elf/dl5.h
new file mode 100644
index 0000000..0d4a7c1
--- /dev/null
+++ b/ld/testsuite/ld-elf/dl5.h
@@ -0,0 +1,10 @@
+class A
+{
+public:
+ A() {}
+ ~A() { }
+ int a;
+ int b;
+};
+
+extern void foo (A *);
diff --git a/ld/testsuite/ld-elf/dwarf.exp b/ld/testsuite/ld-elf/dwarf.exp
index 6a63269..670551f 100644
--- a/ld/testsuite/ld-elf/dwarf.exp
+++ b/ld/testsuite/ld-elf/dwarf.exp
@@ -50,7 +50,7 @@ set build_tests {
"-s -shared" "-fPIC -g -feliminate-dwarf2-dups"
{dwarf1.c} {} "libdwarf1.so"}
{"DWARF parse during linker error"
- "" "-fno-toplevel-reorder"
+ "" "-g -fno-toplevel-reorder"
{dwarf2a.c dwarf2b.c} {{error_output "dwarf2.err"}} "dwarf2.x"}
{"Handle no DWARF information"
"" "-g0"
diff --git a/ld/testsuite/ld-elf/new.cc b/ld/testsuite/ld-elf/new.cc
index 513cf2f..b038d77 100644
--- a/ld/testsuite/ld-elf/new.cc
+++ b/ld/testsuite/ld-elf/new.cc
@@ -1,4 +1,5 @@
#include <new>
+#include "dl5.h"
using std::bad_alloc;
@@ -45,3 +46,8 @@ operator new[] (std::size_t sz, const std::nothrow_t& nothrow) throw()
{
return ::operator new(sz, nothrow);
}
+
+void
+foo (A *)
+{
+}
diff --git a/ld/testsuite/ld-elf/shared.exp b/ld/testsuite/ld-elf/shared.exp
index 277dc7b..d811738 100644
--- a/ld/testsuite/ld-elf/shared.exp
+++ b/ld/testsuite/ld-elf/shared.exp
@@ -552,7 +552,7 @@ set build_tests {
"-shared" "-fPIC"
{begin.c end.c} {} "libbar.so"}
{"Build warn libbar.so"
- "-shared" "-fPIC"
+ "-shared" "-fPIC -g"
{beginwarn.c end.c}
{{readelf {-S --wide} libbarw.rd}
{warning {^.*beginwarn.c:7:\(.*\): warning: function foo is deprecated\n?$}}}
diff --git a/ld/testsuite/ld-x86-64/x86-64.exp b/ld/testsuite/ld-x86-64/x86-64.exp
index e370f39..2a40f0b 100644
--- a/ld/testsuite/ld-x86-64/x86-64.exp
+++ b/ld/testsuite/ld-x86-64/x86-64.exp
@@ -2250,6 +2250,13 @@ run_dump_test "ibt-plt-3a-x32"
run_dump_test "ibt-plt-3b-x32"
run_dump_test "ibt-plt-3c-x32"
run_dump_test "ibt-plt-3d-x32"
+
+# Skip -z mark-plt tests on MUSL.
+if { [istarget "x86_64-*-musl*"]} {
+ set ASFLAGS "$saved_ASFLAGS"
+ return
+}
+
run_dump_test "mark-plt-1a"
run_dump_test "mark-plt-1b"
run_dump_test "mark-plt-1c"
diff --git a/libctf/ctf-create.c b/libctf/ctf-create.c
index d0255e5..2f332e0 100644
--- a/libctf/ctf-create.c
+++ b/libctf/ctf-create.c
@@ -284,11 +284,11 @@ ctf_dtd_delete (ctf_dict_t *fp, ctf_dtdef_t *dtd)
dtd->dtd_vlen_alloc = 0;
if (dtd->dtd_data.ctt_name
- && (name = ctf_strraw (fp, dtd->dtd_data.ctt_name)) != NULL
- && LCTF_INFO_ISROOT (fp, dtd->dtd_data.ctt_info))
+ && (name = ctf_strraw (fp, dtd->dtd_data.ctt_name)) != NULL)
{
- ctf_dynhash_remove (ctf_name_table (fp, name_kind)->ctn_writable,
- name);
+ if (LCTF_INFO_ISROOT (fp, dtd->dtd_data.ctt_info))
+ ctf_dynhash_remove (ctf_name_table (fp, name_kind)->ctn_writable,
+ name);
ctf_str_remove_ref (fp, name, &dtd->dtd_data.ctt_name);
}
diff --git a/opcodes/s390-dis.c b/opcodes/s390-dis.c
index 3c21f9b..dd10a5d 100644
--- a/opcodes/s390-dis.c
+++ b/opcodes/s390-dis.c
@@ -288,12 +288,14 @@ s390_print_insn_with_opcode (bfd_vma memaddr,
{
enum disassembler_style style;
- if (flags & S390_OPERAND_OR1)
- val.u &= ~1;
- if (flags & S390_OPERAND_OR2)
- val.u &= ~2;
- if (flags & S390_OPERAND_OR8)
- val.u &= ~8;
+ if (!(flags & S390_OPERAND_LENGTH))
+ {
+ union operand_value insn_opval;
+
+ /* Mask any constant operand bits set in insn template. */
+ insn_opval = s390_extract_operand (opcode->opcode, operand);
+ val.u &= ~insn_opval.u;
+ }
if ((opcode->flags & S390_INSTR_FLAG_OPTPARM)
&& val.u == 0
diff --git a/opcodes/s390-mkopc.c b/opcodes/s390-mkopc.c
index 3a4aae3..1c4f01c 100644
--- a/opcodes/s390-mkopc.c
+++ b/opcodes/s390-mkopc.c
@@ -150,8 +150,8 @@ struct s390_cond_ext_format
the '*' tag. */
#define NUM_COND_EXTENSIONS 20
const struct s390_cond_ext_format s390_cond_extensions[NUM_COND_EXTENSIONS] =
-{ { '1', "o", "on overflow / if ones"}, /* jump on overflow / if ones */
- { '2', "h", "on A high"}, /* jump on A high */
+{ { '1', "o", "on overflow / if ones" }, /* jump on overflow / if ones */
+ { '2', "h", "on A high" }, /* jump on A high */
{ '2', "p", "on plus" }, /* jump on plus */
{ '3', "nle", "on not low or equal" }, /* jump on not low or equal */
{ '4', "l", "on A low" }, /* jump on A low */
@@ -162,7 +162,7 @@ const struct s390_cond_ext_format s390_cond_extensions[NUM_COND_EXTENSIONS] =
{ '7', "nz", "on not zero / if not zeros" }, /* jump on not zero / if not zeros */
{ '8', "e", "on A equal B" }, /* jump on A equal B */
{ '8', "z", "on zero / if zeros" }, /* jump on zero / if zeros */
- { '9', "nlh", "on not low or high " }, /* jump on not low or high */
+ { '9', "nlh", "on not low or high" }, /* jump on not low or high */
{ 'a', "he", "on high or equal" }, /* jump on high or equal */
{ 'b', "nl", "on A not low" }, /* jump on A not low */
{ 'b', "nm", "on not minus / if not mixed" }, /* jump on not minus / if not mixed */
@@ -443,6 +443,9 @@ main (void)
else if (strcmp (cpu_string, "z16") == 0
|| strcmp (cpu_string, "arch14") == 0)
min_cpu = S390_OPCODE_ARCH14;
+ else if (strcmp (cpu_string, "z17") == 0
+ || strcmp (cpu_string, "arch15") == 0)
+ min_cpu = S390_OPCODE_ARCH15;
else {
print_error ("Mnemonic \"%s\": Couldn't parse CPU string: %s\n",
mnemonic, cpu_string);
@@ -491,15 +494,15 @@ main (void)
&& (str[2] == 0 || str[2] == ',')) {
flag_bits |= S390_INSTR_FLAG_VX;
str += 2;
- } else if (strncmp (str, "jump", 7) == 0
+ } else if (strncmp (str, "jump", 4) == 0
&& (str[4] == 0 || str[4] == ',')) {
flag_bits |= S390_INSTR_FLAGS_CLASS_JUMP;
str += 4;
- } else if (strncmp (str, "condjump", 7) == 0
+ } else if (strncmp (str, "condjump", 8) == 0
&& (str[8] == 0 || str[8] == ',')) {
flag_bits |= S390_INSTR_FLAGS_CLASS_CONDJUMP;
str += 8;
- } else if (strncmp (str, "jumpsr", 7) == 0
+ } else if (strncmp (str, "jumpsr", 6) == 0
&& (str[6] == 0 || str[6] == ',')) {
flag_bits |= S390_INSTR_FLAGS_CLASS_JUMPSR;
str += 6;
diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c
index 377a4a9..0c00506 100644
--- a/opcodes/s390-opc.c
+++ b/opcodes/s390-opc.c
@@ -208,31 +208,17 @@ const struct s390_operand s390_operands[] =
{ 4, 20, 0 },
#define U4_24 (U4_20 + 1) /* 4 bit unsigned value starting at 24 */
{ 4, 24, 0 },
-#define U4_OR1_24 (U4_24 + 1) /* 4 bit unsigned value ORed with 1 */
- { 4, 24, S390_OPERAND_OR1 }, /* starting at 24 */
-#define U4_OR2_24 (U4_OR1_24+1) /* 4 bit unsigned value ORed with 2 */
- { 4, 24, S390_OPERAND_OR2 }, /* starting at 24 */
-#define U4_OR3_24 (U4_OR2_24+1) /* 4 bit unsigned value ORed with 3 */
- { 4, 24, S390_OPERAND_OR1 | S390_OPERAND_OR2 }, /* starting at 24 */
-#define U4_28 (U4_OR3_24+1) /* 4 bit unsigned value starting at 28 */
+#define U4_28 (U4_24+1) /* 4 bit unsigned value starting at 28 */
{ 4, 28, 0 },
-#define U4_OR8_28 (U4_28 + 1) /* 4 bit unsigned value ORed with 8 */
- { 4, 28, S390_OPERAND_OR8 }, /* starting at 28 */
-#define U4_32 (U4_OR8_28+1) /* 4 bit unsigned value starting at 32 */
+#define U4_32 (U4_28+1) /* 4 bit unsigned value starting at 32 */
{ 4, 32, 0 },
#define U4_36 (U4_32 + 1) /* 4 bit unsigned value starting at 36 */
{ 4, 36, 0 },
#define U8_8 (U4_36 + 1) /* 8 bit unsigned value starting at 8 */
{ 8, 8, 0 },
-#define U6_18 (U8_8 + 1) /* 6 bit unsigned value starting at 18 */
- { 6, 18, 0 },
-#define U8_16 (U6_18 + 1) /* 8 bit unsigned value starting at 16 */
+#define U8_16 (U8_8 + 1) /* 8 bit unsigned value starting at 16 */
{ 8, 16, 0 },
-#define U5_27 (U8_16 + 1) /* 5 bit unsigned value starting at 27 */
- { 5, 27, 0 },
-#define U6_26 (U5_27 + 1) /* 6 bit unsigned value starting at 26 */
- { 6, 26, 0 },
-#define U8_24 (U6_26 + 1) /* 8 bit unsigned value starting at 24 */
+#define U8_24 (U8_16 + 1) /* 8 bit unsigned value starting at 24 */
{ 8, 24, 0 },
#define U8_28 (U8_24 + 1) /* 8 bit unsigned value starting at 28 */
{ 8, 28, 0 },
@@ -242,7 +228,9 @@ const struct s390_operand s390_operands[] =
{ 12, 16, 0 },
#define U16_16 (U12_16 + 1) /* 16 bit unsigned value starting at 16 */
{ 16, 16, 0 },
-#define U16_32 (U16_16 + 1) /* 16 bit unsigned value starting at 32 */
+#define U16_20 (U16_16 + 1) /* 16 bit unsigned value starting at 20 */
+ { 16, 20, 0 },
+#define U16_32 (U16_20 + 1) /* 16 bit unsigned value starting at 32 */
{ 16, 32, 0 },
#define U32_16 (U16_32 + 1) /* 32 bit unsigned value starting at 16 */
{ 32, 16, 0 },
@@ -296,7 +284,7 @@ unused_s390_operands_static_asserts (void)
p - pc relative
r - general purpose register
re - gpr extended operand, a valid general purpose register pair
- u - unsigned integer, 4, 6, 8, 16 or 32 bit
+ u - unsigned integer, 4, 8, 16 or 32 bit
m - mode field, 4 bit
0 - operand skipped.
The order of the letters reflects the layout of the format in
@@ -332,9 +320,9 @@ unused_s390_operands_static_asserts (void)
#define INSTR_RIE_R0U0 6, { R_8,U16_16,0,0,0,0 } /* e.g. clfitne */
#define INSTR_RIE_RUI0 6, { R_8,I16_16,U4_12,0,0,0 } /* e.g. lochi */
#define INSTR_RIE_RRUUU 6, { R_8,R_12,U8_16,U8_24,U8_32,0 } /* e.g. rnsbg */
-#define INSTR_RIE_RRUUU2 6, { R_8,R_12,U8_16,U6_26,U8_32,0 } /* e.g. risbgz */
-#define INSTR_RIE_RRUUU3 6, { R_8,R_12,U8_16,U5_27,U8_32,0 } /* e.g. risbhg */
-#define INSTR_RIE_RRUUU4 6, { R_8,R_12,U6_18,U8_24,U8_32,0 } /* e.g. rnsbgt */
+#define INSTR_RIE_RRUUU2 INSTR_RIE_RRUUU /* e.g. risbgz */
+#define INSTR_RIE_RRUUU3 INSTR_RIE_RRUUU /* e.g. risbhg */
+#define INSTR_RIE_RRUUU4 INSTR_RIE_RRUUU /* e.g. rnsbgt */
#define INSTR_RIL_0P 6, { J32_16,0,0,0,0 } /* e.g. jg */
#define INSTR_RIL_RP 6, { R_8,J32_16,0,0,0,0 } /* e.g. brasl */
#define INSTR_RIL_UP 6, { U4_8,J32_16,0,0,0,0 } /* e.g. brcl */
@@ -478,6 +466,7 @@ unused_s390_operands_static_asserts (void)
#define INSTR_SS_RRRDRD2 6, { R_8,D_20,B_16,R_12,D_36,B_32 } /* e.g. plo */
#define INSTR_SS_RRRDRD3 6, { R_8,R_12,D_20,B_16,D_36,B_32 } /* e.g. lmd */
#define INSTR_SSF_RRDRD 6, { D_20,B_16,D_36,B_32,R_8,0 } /* e.g. mvcos */
+#define INSTR_SSF_RRDRD2 6, { R_8,D_20,B_16,D_36,B_32,0 } /* e.g. cal */
#define INSTR_SSF_RERDRD2 6, { RE_8,D_20,B_16,D_36,B_32,0 } /* e.g. lpd */
#define INSTR_S_00 4, { 0,0,0,0,0,0 } /* e.g. hsch */
#define INSTR_S_RD 4, { D_20,B_16,0,0,0,0 } /* e.g. stck */
@@ -498,6 +487,8 @@ unused_s390_operands_static_asserts (void)
#define INSTR_VRI_VVUUU 6, { V_8,V_12,U12_16,U4_32,U4_28,0 } /* e.g. vftci */
#define INSTR_VRI_VVUUU2 6, { V_8,V_12,U8_28,U8_16,U4_24,0 } /* e.g. vpsop */
#define INSTR_VRI_VR0UU 6, { V_8,R_12,U8_28,U4_24,0,0 } /* e.g. vcvd */
+#define INSTR_VRI_VV0UU 6, { V_8,V_12,U8_28,U4_24,0,0 } /* e.g. vcvdq */
+#define INSTR_VRI_VVV0UV 6, { V_8,V_12,V_16,V_32,U8_24,0 } /* e.g. veval */
#define INSTR_VRX_VRRD 6, { V_8,D_20,X_12,B_16,0,0 } /* e.g. vl */
#define INSTR_VRX_VV 6, { V_8,V_12,0,0,0,0 } /* e.g. vlr */
#define INSTR_VRX_VRRDU 6, { V_8,D_20,X_12,B_16,U4_32,0 } /* e.g. vlrep */
@@ -508,27 +499,27 @@ unused_s390_operands_static_asserts (void)
#define INSTR_VRS_VRRDU 6, { V_8,R_12,D_20,B_16,U4_32,0 } /* e.g. vlvg */
#define INSTR_VRS_VRRD 6, { V_8,R_12,D_20,B_16,0,0 } /* e.g. vlvgb */
#define INSTR_VRS_RRDV 6, { V_32,R_12,D_20,B_16,0,0 } /* e.g. vlrlr */
-#define INSTR_VRR_0V 6, { V_12,0,0,0,0,0 } /* e.g. vtp */
#define INSTR_VRR_VRR 6, { V_8,R_12,R_16,0,0,0 } /* e.g. vlvgp */
#define INSTR_VRR_VVV0U 6, { V_8,V_12,V_16,U4_32,0,0 } /* e.g. vmrh */
#define INSTR_VRR_VVV0U0 6, { V_8,V_12,V_16,U4_24,0,0 } /* e.g. vfaeb */
-#define INSTR_VRR_VVV0U1 6, { V_8,V_12,V_16,U4_OR1_24,0,0 } /* e.g. vfaebs*/
-#define INSTR_VRR_VVV0U2 6, { V_8,V_12,V_16,U4_OR2_24,0,0 } /* e.g. vfaezb*/
-#define INSTR_VRR_VVV0U3 6, { V_8,V_12,V_16,U4_OR3_24,0,0 } /* e.g. vfaezbs*/
+#define INSTR_VRR_VVV0U02 6, { V_8,V_12,V_16,U4_28,0,0 } /* e.g. vd */
+#define INSTR_VRR_VVV0U1 INSTR_VRR_VVV0U0 /* e.g. vfaebs*/
+#define INSTR_VRR_VVV0U2 INSTR_VRR_VVV0U0 /* e.g. vfaezb*/
+#define INSTR_VRR_VVV0U3 INSTR_VRR_VVV0U0 /* e.g. vfaezbs*/
#define INSTR_VRR_VVV 6, { V_8,V_12,V_16,0,0,0 } /* e.g. vmrhb */
#define INSTR_VRR_VVV2 6, { V_8,V_CP16_12,0,0,0,0 } /* e.g. vnot */
#define INSTR_VRR_VV0U 6, { V_8,V_12,U4_32,0,0,0 } /* e.g. vseg */
#define INSTR_VRR_VV0U2 6, { V_8,V_12,U4_24,0,0,0 } /* e.g. vistrb*/
#define INSTR_VRR_VV0UU 6, { V_8,V_12,U4_28,U4_24,0,0 } /* e.g. vcdgb */
#define INSTR_VRR_VV0UU2 6, { V_8,V_12,U4_32,U4_28,0,0 } /* e.g. wfc */
-#define INSTR_VRR_VV0UU8 6, { V_8,V_12,U4_OR8_28,U4_24,0,0 } /* e.g. wcdgb */
+#define INSTR_VRR_VV0UU8 INSTR_VRR_VV0UU /* e.g. wcdgb */
#define INSTR_VRR_VV 6, { V_8,V_12,0,0,0,0 } /* e.g. vsegb */
#define INSTR_VRR_VVVUU0V 6, { V_8,V_12,V_16,V_32,U4_20,U4_24 } /* e.g. vstrc */
#define INSTR_VRR_VVVU0V 6, { V_8,V_12,V_16,V_32,U4_20,0 } /* e.g. vac */
#define INSTR_VRR_VVVU0VB 6, { V_8,V_12,V_16,V_32,U4_24,0 } /* e.g. vstrcb*/
-#define INSTR_VRR_VVVU0VB1 6, { V_8,V_12,V_16,V_32,U4_OR1_24,0 } /* e.g. vstrcbs*/
-#define INSTR_VRR_VVVU0VB2 6, { V_8,V_12,V_16,V_32,U4_OR2_24,0 } /* e.g. vstrczb*/
-#define INSTR_VRR_VVVU0VB3 6, { V_8,V_12,V_16,V_32,U4_OR3_24,0 } /* e.g. vstrczbs*/
+#define INSTR_VRR_VVVU0VB1 INSTR_VRR_VVVU0VB /* e.g. vstrcbs*/
+#define INSTR_VRR_VVVU0VB2 INSTR_VRR_VVVU0VB /* e.g. vstrczb*/
+#define INSTR_VRR_VVVU0VB3 INSTR_VRR_VVVU0VB /* e.g. vstrczbs*/
#define INSTR_VRR_VVV0V 6, { V_8,V_12,V_16,V_32,0,0 } /* e.g. vacq */
#define INSTR_VRR_VVV0U0U 6, { V_8,V_12,V_16,U4_32,U4_24,0 } /* e.g. vfae */
#define INSTR_VRR_VVVV 6, { V_8,V_12,V_16,V_32,0,0 } /* e.g. vfmadb*/
@@ -537,6 +528,9 @@ unused_s390_operands_static_asserts (void)
#define INSTR_VRR_VV0UUU 6, { V_8,V_12,U4_32,U4_28,U4_24,0 } /* e.g. vcdg */
#define INSTR_VRR_VVVU0UV 6, { V_8,V_12,V_16,V_32,U4_28,U4_20 } /* e.g. vfma */
#define INSTR_VRR_VV0U0U 6, { V_8,V_12,U4_32,U4_24,0,0 } /* e.g. vistr */
+#define INSTR_VRR_0V 6, { V_12,0,0,0,0,0 } /* e.g. vtp */
+#define INSTR_VRR_0V0U 6, { V_12,U16_20,0,0,0,0 } /* e.g. vtp */
+#define INSTR_VRR_0VVU 6, { V_12,V_16,U16_20,0,0,0 } /* e.g. vtz */
#define INSTR_VRR_0VV0U 6, { V_12,V_16,U4_24,0,0,0 } /* e.g. vcp */
#define INSTR_VRR_RV0U 6, { R_8,V_12,U4_24,0,0,0 } /* e.g. vcvb */
#define INSTR_VRR_RV0UU 6, { R_8,V_12,U4_24,U4_28,0,0 } /* e.g. vcvb */
@@ -559,9 +553,9 @@ unused_s390_operands_static_asserts (void)
#define MASK_RIE_R0U0 { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff }
#define MASK_RIE_RUI0 { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff }
#define MASK_RIE_RRUUU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
-#define MASK_RIE_RRUUU2 { 0xff, 0x00, 0x00, 0xc0, 0x00, 0xff }
-#define MASK_RIE_RRUUU3 { 0xff, 0x00, 0x00, 0xe0, 0x00, 0xff }
-#define MASK_RIE_RRUUU4 { 0xff, 0x00, 0xc0, 0x00, 0x00, 0xff }
+#define MASK_RIE_RRUUU2 { 0xff, 0x00, 0x00, 0x80, 0x00, 0xff }
+#define MASK_RIE_RRUUU3 { 0xff, 0x00, 0x00, 0x80, 0x00, 0xff }
+#define MASK_RIE_RRUUU4 { 0xff, 0x00, 0x80, 0x00, 0x00, 0xff }
#define MASK_RIL_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RIL_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RIL_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
@@ -705,6 +699,7 @@ unused_s390_operands_static_asserts (void)
#define MASK_SS_RRRDRD2 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_SS_RRRDRD3 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_SSF_RRDRD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_SSF_RRDRD2 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
#define MASK_SSF_RERDRD2 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
#define MASK_S_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 }
#define MASK_S_RD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
@@ -725,6 +720,8 @@ unused_s390_operands_static_asserts (void)
#define MASK_VRI_VVUUU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
#define MASK_VRI_VVUUU2 { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
#define MASK_VRI_VR0UU { 0xff, 0x00, 0xff, 0x00, 0x00, 0xff }
+#define MASK_VRI_VV0UU { 0xff, 0x00, 0xff, 0x00, 0x00, 0xff }
+#define MASK_VRI_VVV0UV { 0xff, 0x00, 0x0f, 0x00, 0x00, 0xff }
#define MASK_VRX_VRRD { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff }
#define MASK_VRX_VV { 0xff, 0x00, 0xff, 0xff, 0xf0, 0xff }
#define MASK_VRX_VRRDU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
@@ -735,10 +732,10 @@ unused_s390_operands_static_asserts (void)
#define MASK_VRS_VRRDU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
#define MASK_VRS_VRRD { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff }
#define MASK_VRS_RRDV { 0xff, 0xf0, 0x00, 0x00, 0x00, 0xff }
-#define MASK_VRR_0V { 0xff, 0xf0, 0xff, 0xff, 0xf0, 0xff }
#define MASK_VRR_VRR { 0xff, 0x00, 0x0f, 0xff, 0xf0, 0xff }
#define MASK_VRR_VVV0U { 0xff, 0x00, 0x0f, 0xff, 0x00, 0xff }
#define MASK_VRR_VVV0U0 { 0xff, 0x00, 0x0f, 0x0f, 0xf0, 0xff }
+#define MASK_VRR_VVV0U02 { 0xff, 0x00, 0x0f, 0xf0, 0xf0, 0xff }
#define MASK_VRR_VVV0U1 { 0xff, 0x00, 0x0f, 0x1f, 0xf0, 0xff }
#define MASK_VRR_VVV0U2 { 0xff, 0x00, 0x0f, 0x2f, 0xf0, 0xff }
#define MASK_VRR_VVV0U3 { 0xff, 0x00, 0x0f, 0x3f, 0xf0, 0xff }
@@ -764,6 +761,9 @@ unused_s390_operands_static_asserts (void)
#define MASK_VRR_VV0UUU { 0xff, 0x00, 0xff, 0x00, 0x00, 0xff }
#define MASK_VRR_VVVU0UV { 0xff, 0x00, 0x00, 0xf0, 0x00, 0xff }
#define MASK_VRR_VV0U0U { 0xff, 0x00, 0xff, 0x0f, 0x00, 0xff }
+#define MASK_VRR_0V { 0xff, 0xf0, 0xff, 0xff, 0xf0, 0xff }
+#define MASK_VRR_0V0U { 0xff, 0xf0, 0xf0, 0x00, 0x00, 0xff }
+#define MASK_VRR_0VVU { 0xff, 0xf0, 0x00, 0x00, 0x00, 0xff }
#define MASK_VRR_0VV0U { 0xff, 0xf0, 0x0f, 0x0f, 0xf0, 0xff }
#define MASK_VRR_RV0U { 0xff, 0x00, 0xff, 0x0f, 0xf0, 0xff }
#define MASK_VRR_RV0UU { 0xff, 0x00, 0xff, 0x00, 0xf0, 0xff }
diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt
index 83ca22f..68d8896 100644
--- a/opcodes/s390-opc.txt
+++ b/opcodes/s390-opc.txt
@@ -942,10 +942,10 @@ ec00000000ff clib$12 RIS_R0RDU "compare logical immediate and branch (32<8)" z10
ec00000000ff clib RIS_RURDU "compare logical immediate and branch (32<8)" z10 zarch
ec00000000fd clgib$12 RIS_R0RDU "compare logical immediate and branch (64<8)" z10 zarch
ec00000000fd clgib RIS_RURDU "compare logical immediate and branch (64<8)" z10 zarch
-ec000000007f clij$12 RIE_R0PU "compare logical immediate and branch relative (32<8)" z10 zarch
-ec000000007f clij RIE_RUPU "compare logical immediate and branch relative (32<8)" z10 zarch
-ec000000007d clgij$12 RIE_R0PU "compare logical immediate and branch relative (64<8)" z10 zarch
-ec000000007d clgij RIE_RUPU "compare logical immediate and branch relative (64<8)" z10 zarch
+ec000000007f clij$12 RIE_R0PU "compare logical immediate and branch relative (32<8)" z10 zarch condjump
+ec000000007f clij RIE_RUPU "compare logical immediate and branch relative (32<8)" z10 zarch condjump
+ec000000007d clgij$12 RIE_R0PU "compare logical immediate and branch relative (64<8)" z10 zarch condjump
+ec000000007d clgij RIE_RUPU "compare logical immediate and branch relative (64<8)" z10 zarch condjump
b9730000 clrt$16 RRF_00RR "compare logical and trap (32)" z10 zarch
b973 clrt RRF_U0RR "compare logical and trap (32)" z10 zarch
b9610000 clgrt$16 RRF_00RR "compare logical and trap (64)" z10 zarch
@@ -2061,7 +2061,7 @@ e60000000055 vcnf VRR_VV0UU2 "vector fp convert to nnp" arch14 zarch
# Reset-DAT-Protection Facility
-b98B rdp RRF_RURR2 "reset dat protection" arch14 zarch optparm
+b98b rdp RRF_RURR2 "reset dat protection" arch14 zarch optparm
# BEAR-Enhancement Facility
@@ -2072,3 +2072,129 @@ b201 stbear S_RD "store bear" arch14 zarch
# Processor-Activity-Instrumentation Facility
b28f qpaci S_RD "query processor activity counter information" arch14 zarch
+
+
+# arch15 instructions
+
+# Vector-Enhancements Facility 3
+
+e70000000089 vblend VRR_VVVU0V "vector blend" arch15 zarch
+e70000000089 vblendb VRR_VVV0V "vector blend byte" arch15 zarch
+e70001000089 vblendh VRR_VVV0V "vector blend halfword" arch15 zarch
+e70002000089 vblendf VRR_VVV0V "vector blend word" arch15 zarch
+e70003000089 vblendg VRR_VVV0V "vector blend doubleword" arch15 zarch
+e70004000089 vblendq VRR_VVV0V "vector blend quadword" arch15 zarch
+
+e70000000088 veval VRI_VVV0UV "vector evaluate" arch15 zarch
+
+e70000000054 vgem VRR_VV0U "vector generate element masks" arch15 zarch
+e70000000054 vgemb VRR_VV "vector generate element masks byte" arch15 zarch
+e70000001054 vgemh VRR_VV "vector generate element masks halfword" arch15 zarch
+e70000002054 vgemf VRR_VV "vector generate element masks word" arch15 zarch
+e70000003054 vgemg VRR_VV "vector generate element masks doubleword" arch15 zarch
+e70000004054 vgemq VRR_VV "vector generate element masks quadword" arch15 zarch
+
+e700000030d7 vuphg VRR_VV "vector unpack high doubleword" arch15 zarch
+e700000030d5 vuplhg VRR_VV "vector unpack logical high doubleword" arch15 zarch
+e700000030d6 vuplg VRR_VV "vector unpack low doubleword" arch15 zarch
+e700000030d4 vupllg VRR_VV "vector unpack logical low doubleword" arch15 zarch
+
+e700000040f2 vavgq VRR_VVV "vector average quadword" arch15 zarch
+e700000040f0 vavglq VRR_VVV "vector average logical quadword" arch15 zarch
+e700000040db vecq VRR_VV "vector element compare quadword" arch15 zarch
+e700000040d9 veclq VRR_VV "vector element compare logical quadword" arch15 zarch
+e700000040f8 vceqq VRR_VVV "vector compare equal quadword" arch15 zarch
+e700001040f8 vceqqs VRR_VVV "vector compare equal quadword" arch15 zarch
+e700000040fb vchq VRR_VVV "vector compare high quadword" arch15 zarch
+e700001040fb vchqs VRR_VVV "vector compare high quadword" arch15 zarch
+e700000040f9 vchlq VRR_VVV "vector compare high logical quadword" arch15 zarch
+e700001040f9 vchlqs VRR_VVV "vector compare high logical quadword" arch15 zarch
+e70000004053 vclzq VRR_VV "vector count leading zeros quadword" arch15 zarch
+e70000004052 vctzq VRR_VV "vector count trailing zeros quadword" arch15 zarch
+e700000040de vlcq VRR_VV "vector load complement quadword" arch15 zarch
+e700000040df vlpq VRR_VV "vector load positive quadword" arch15 zarch
+e700000040ff vmxq VRR_VVV "vector maximum quadword" arch15 zarch
+e700000040fd vmxlq VRR_VVV "vector maximum logical quadword" arch15 zarch
+e700000040fe vmnq VRR_VVV "vector minimum quadword" arch15 zarch
+e700000040fc vmnlq VRR_VVV "vector minimum logical quadword" arch15 zarch
+e700030000aa vmalg VRR_VVV0V "vector multiply and add low doubleword" arch15 zarch
+e700040000aa vmalq VRR_VVV0V "vector multiply and add low quadword" arch15 zarch
+e700030000ab vmahg VRR_VVV0V "vector multiply and add high doubleword" arch15 zarch
+e700040000ab vmahq VRR_VVV0V "vector multiply and add high quadword" arch15 zarch
+e700030000a9 vmalhg VRR_VVV0V "vector multiply and add logical high doubleword" arch15 zarch
+e700040000a9 vmalhq VRR_VVV0V "vector multiply and add logical high quadword" arch15 zarch
+e700030000ae vmaeg VRR_VVV0V "vector multiply and add even doubleword" arch15 zarch
+e700030000ac vmaleg VRR_VVV0V "vector multiply and add logical even doubleword" arch15 zarch
+e700030000af vmaog VRR_VVV0V "vector multiply and add odd doubleword" arch15 zarch
+e700030000ad vmalog VRR_VVV0V "vector multiply and add logical odd doubleword" arch15 zarch
+e700000030a3 vmhg VRR_VVV "vector multiply high doubleword" arch15 zarch
+e700000040a3 vmhq VRR_VVV "vector multiply high quadword" arch15 zarch
+e700000030a1 vmlhg VRR_VVV "vector multiply logical high doubleword" arch15 zarch
+e700000040a1 vmlhq VRR_VVV "vector multiply logical high quadword" arch15 zarch
+e700000030a2 vmlg VRR_VVV "vector multiply low doubleword" arch15 zarch
+e700000040a2 vmlq VRR_VVV "vector multiply low quadword" arch15 zarch
+e700000030a6 vmeg VRR_VVV "vector multiply even doubleword" arch15 zarch
+e700000030a4 vmleg VRR_VVV "vector multiply logical even doubleword" arch15 zarch
+e700000030a7 vmog VRR_VVV "vector multiply odd doubleword" arch15 zarch
+e700000030a5 vmlog VRR_VVV "vector multiply logical odd doubleword" arch15 zarch
+
+e700000000b2 vd VRR_VVV0UU "vector divide" arch15 zarch
+e700000020b2 vdf VRR_VVV0U02 "vector divide word" arch15 zarch
+e700000030b2 vdg VRR_VVV0U02 "vector divide doubleword" arch15 zarch
+e700000040b2 vdq VRR_VVV0U02 "vector divide quadword" arch15 zarch
+
+e700000000b0 vdl VRR_VVV0UU "vector divide logical" arch15 zarch
+e700000020b0 vdlf VRR_VVV0U02 "vector divide logical word" arch15 zarch
+e700000030b0 vdlg VRR_VVV0U02 "vector divide logical doubleword" arch15 zarch
+e700000040b0 vdlq VRR_VVV0U02 "vector divide logical quadword" arch15 zarch
+
+e700000000b3 vr VRR_VVV0UU "vector remainder" arch15 zarch
+e700000020b3 vrf VRR_VVV0U02 "vector remainder word" arch15 zarch
+e700000030b3 vrg VRR_VVV0U02 "vector remainder doubleword" arch15 zarch
+e700000040b3 vrq VRR_VVV0U02 "vector remainder quadword" arch15 zarch
+
+e700000000b1 vrl VRR_VVV0UU "vector remainder logical" arch15 zarch
+e700000020b1 vrlf VRR_VVV0U02 "vector remainder logical word" arch15 zarch
+e700000030b1 vrlg VRR_VVV0U02 "vector remainder logical doubleword" arch15 zarch
+e700000040b1 vrlq VRR_VVV0U02 "vector remainder logical quadword" arch15 zarch
+
+# Miscellaneous-Instruction-Extensions Facility 4
+
+b968 clzg RRE_RR "count leading zeros" arch15 zarch
+b969 ctzg RRE_RR "count trailing zeros" arch15 zarch
+
+e30000000060 lxab RXY_RRRD "load indexed address (shift left 0)" arch15 zarch
+e30000000062 lxah RXY_RRRD "load indexed address (shift left 1)" arch15 zarch
+e30000000064 lxaf RXY_RRRD "load indexed address (shift left 2)" arch15 zarch
+e30000000066 lxag RXY_RRRD "load indexed address (shift left 3)" arch15 zarch
+e30000000068 lxaq RXY_RRRD "load indexed address (shift left 4)" arch15 zarch
+
+e30000000061 llxab RXY_RRRD "load logical indexed address (shift left 0)" arch15 zarch
+e30000000063 llxah RXY_RRRD "load logical indexed address (shift left 1)" arch15 zarch
+e30000000065 llxaf RXY_RRRD "load logical indexed address (shift left 2)" arch15 zarch
+e30000000067 llxag RXY_RRRD "load logical indexed address (shift left 3)" arch15 zarch
+e30000000069 llxaq RXY_RRRD "load logical indexed address (shift left 4)" arch15 zarch
+
+b96c bextg RRF_R0RR2 "bit extract" arch15 zarch
+b96d bdepg RRF_R0RR2 "bit deposit" arch15 zarch
+
+# Message-Security-Assist Extension 12
+
+b93e kimd RRF_U0RR "compute intermediate message digest" arch15 zarch optparm
+b93f klmd RRF_U0RR "compute last message digest" arch15 zarch optparm
+
+# Vector-Packed-Decimal-Enhancement Facility 3
+
+e6000000004e vcvbq VRR_VV0U2 "vector convert to binary 128 bit" arch15 zarch
+e6000000004a vcvdq VRI_VV0UU "vector convert to decimal 128 bit" arch15 zarch
+
+e6000000005f vtp VRR_0V0U "vector test decimal" arch15 zarch optparm
+e6000000007f vtz VRR_0VVU "vector test zoned" arch15 zarch
+
+# Concurrent-Functions Facility
+
+c806 cal SSF_RRDRD2 "compare and load 32" arch15 zarch
+c807 calg SSF_RRDRD2 "compare and load 64" arch15 zarch
+c80f calgf SSF_RRDRD2 "compare and load 64<32" arch15 zarch
+
+eb0000000016 pfcr RSY_RRRD "perform functions with concurrent results" arch15 zarch
generated by cgit v1.1 at 2025-07-16 03:08:03 +0000