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authorAndrew Burgess <andrew.burgess@embecosm.com>2020-11-27 14:39:23 +0000
committerAndrew Burgess <andrew.burgess@embecosm.com>2021-03-05 17:21:41 +0000
commitb2668f28eee60cca8d4f271e2fbc5de32a86c7ea (patch)
tree180f7da74c56e584d43773f97353af56ecb36a81 /sim/m32c
parentd782d24b3297d0eebdc3c823bd41993e5d670c88 (diff)
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gdb/riscv: write CSRs into baremetal core dumps
Use the current target description to include CSRs into the RISC-V baremetal core dumps. Every CSR declared in the current target description will be included in the core dump. It will be critical for users that they have the same target description in use when loading the core file as was in use when writing the core file. This should be fine if the user allows the target description to be written into the core file. In more detail, this commit adds a NT_RISCV_CSR note type. The contents of this section is a series of either 4-byte (on RV32 targets), or 8-byte (on RV64 targets) values. Every CSR that is mentioned in the current target description is written out in the order the registers appear in the target description. As a consequence it is critical that the exact same target description, including the same register order, is in use when the CSRs are loaded from the core file. gdb/ChangeLog: * riscv-none-tdep.c: Add 'user-regs.h' and 'target-description.h' includes. (riscv_csrset): New static global. (riscv_update_csrmap): New function. (riscv_iterate_over_regset_sections): Process CSRs.
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