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| author | Nelson Chu <nelson.chu@sifive.com> | 2021-09-27 01:29:58 -0700 |
|---|---|---|
| committer | Nelson Chu <nelson.chu@sifive.com> | 2021-10-28 08:52:25 +0800 |
| commit | 19b58b26585b296ce0e506333e17a49dd2acf4c5 (patch) | |
| tree | 07758f4c25eb75959935304475e70bba004e8917 /include | |
| parent | 77dd5c805f4347c5de657ddeed032a2e9bd7abc7 (diff) | |
| download | binutils-users/riscv/binutils-integration-branch.zip binutils-users/riscv/binutils-integration-branch.tar.gz binutils-users/riscv/binutils-integration-branch.tar.bz2 | |
RISC-V/SiFive: Added SiFive custom cache control instructions.users/riscv/binutils-integration-branch
According to the chapter 10 of the following U74-MC manual,
https://sifive.cdn.prismic.io/sifive/6d9a2510-2632-44f3-adb9-d0430f139372_sifive_coreip_U74MC_AXI4_rtl_v19_08p2p0_release_manual.pdf
and the implementations of freedom-metal,
https://github.com/sifive/freedom-metal/blob/v201908-branch/src/cache.c
* Encodings,
31-25 24-20 19-15 14-12 11-7 6-0
FUNCT7 RS2 RS1 FUNCT3 RD OPCODE
1111110 00000 xxxxx 000 00000 1110011 CFLUSH.D.L1
1111110 00010 xxxxx 000 00000 1110011 CDISCARD.D.L1
1111110 00001 00000 000 00000 1110011 CFLUSH.I.L1
* Extension names,
xsfcflushdlone: CFLUSH.D.L1.
xsfcdiscarddlone: CDISCARD.D.L1.
xsfcflushilone: CFLUSH.I.L1.
* Vendor target triples,
For assembler, the target vendor is defined as TARGET_VENDOR in the
gas/config.h, but I don't see any related settings in bfd/config.h
and opcode/config. Since we may have vendor relocations in the future,
and these relocation numbers may repeat, I add a new RISCV_TARGET_VENDOR
in the bfd/config.h for riscv. The vendor name will be stored in the
bfd/cpu-riscv.c, so that all tools (gas, bfd, opcode, ...) can get
the vendor name from the configure setting.
If the --with-arch configure option, -march gas option and elf architecture
attributes are not set, then we will generate the default ISA string
according to the chosen target vendor. For example, if you build the
binutils with the configure option, --target=riscv64-sifive-elf, then
the assembler will find the whole supported extension tables in the
bfd/elfxx-riscv.c, and generate the suitable ISA string.
bfd/
* configure.ac (RISCV_TARGET_VENDOR): Defined to store target_vendor,
only when the target is riscv*.
* config.in: Regenerated.
* configure: Regenerated.
* cpu-riscv.c (riscv_vendor_name): Defined to RISCV_TARGET_VENDOR.
* cpu-riscv.h (enum riscv_spec_class): Added VENDOR_SPEC_CLASS_SIFIVE.
* elfxx-riscv. (EXT_SIFIVE): Defined to choose the default extensions
for sifive.
(riscv_supported_vendor_sifive_ext): Added extensions for sifive cache
control instructions.
(riscv_supported_std_ext, riscv_all_supported_ext): Updated.
(riscv_get_default_ext_version): Updated.
(riscv_set_default_arch): Updated.
gas/
* config/tc-riscv.c (VENDOR_SIFIVE_EXT): Added.
(riscv_extended_subset_supports): Handle INSN_CLASS_XSF*.
(op_vendor_sifive_hash): Added to store sifive opcodes.
(md_begin): Init the op_vendor_sifive_hash.
(riscv_find_extended_opcode_hash): Find the opcodes from
op_vendor_sifive_hash.
* testsuite/gas/riscv/extended/sifive-insns.d: New testcase.
* testsuite/gas/riscv/extended/sifive-insns.s: Likewise.
include/
* opcode/riscv-opc-extended.h: Added opcodes for sifive cache
instructions.
* opcode/riscv.h (enum riscv_extended_insn_class): Added INSN_CLASS_XSF*.
opcodes/
* riscv-opc.c (riscv_vendor_sifive_opcodes): Added.
(riscv_extended_opcodes): Updated.
Diffstat (limited to 'include')
| -rw-r--r-- | include/opcode/riscv-opc-extended.h | 11 | ||||
| -rw-r--r-- | include/opcode/riscv.h | 5 |
2 files changed, 16 insertions, 0 deletions
diff --git a/include/opcode/riscv-opc-extended.h b/include/opcode/riscv-opc-extended.h index de9741f..1010661 100644 --- a/include/opcode/riscv-opc-extended.h +++ b/include/opcode/riscv-opc-extended.h @@ -2078,3 +2078,14 @@ DECLARE_CSR(shpmcounter29, CSR_SHPMCOUNTER29, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_ DECLARE_CSR(shpmcounter30, CSR_SHPMCOUNTER30, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) DECLARE_CSR(shpmcounter31, CSR_SHPMCOUNTER31, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) #endif /* DECLARE_CSR */ + +#ifndef __RISCV_OPC_SIFIVE_THEAD__ +#define __RISCV_OPC_SIFIVE_THEAD__ +/* SiFive cache control instructions. */ +#define MATCH_CFLUSH_D_L1 0xfc000073 +#define MASK_CFLUSH_D_L1 0xfff07fff +#define MATCH_CDISCARD_D_L1 0xfc200073 +#define MASK_CDISCARD_D_L1 0xfff07fff +#define MATCH_CFLUSH_I_L1 0xfc100073 +#define MASK_CFLUSH_I_L1 0xffffffff +#endif /* __RISCV_OPC_SIFIVE_THEAD__ */ diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 8cef449..568e33b 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -529,6 +529,11 @@ enum riscv_extended_insn_class INSN_CLASS_THEADC_OR_THEADE_OR_THEADSE, INSN_CLASS_THEADE, INSN_CLASS_THEADSE, + + /* SiFive. */ + INSN_CLASS_XSF_CDISCARDDLONE, + INSN_CLASS_XSF_CFLUSHDLONE, + INSN_CLASS_XSF_CFLUSHILONE, }; /* This is a list of macro expanded instructions for extended |