mve: Fix encoding for vcvt[bt] single-half float conversion instructions

The encoding was previously not taking into account that the Quad vector
registers were being encoded using their Q-register numbers rather than their
D-register equivalent (multiply by 2).

gas/

	* config/tc-arm.c (do_neon_cvttb_1): Use Q-register vector number
	rather than their D-register equivalent.

gas/testsuite/

	* gas/arm/mve-vcvt-3.d: Correct expected values in test.

2 files changed, 81 insertions, 72 deletions

diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index becaecd..540ab48 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -19233,13 +19233,22 @@ do_neon_cvttb_1 (bool t)
 	  return;
 	}
 
+      unsigned op0 = inst.operands[0].reg;
+      unsigned op1 = inst.operands[1].reg;
+      /* NS_QQ so both registers are quads but inst.operands has their
+	 D-register values, so halve before encoding.  */
+      if (rs == NS_QQ)
+	{
+	  op0 >>= 1;
+	  op1 >>= 1;
+	}
       inst.instruction = 0xee3f0e01;
       inst.instruction |= single_to_half << 28;
-      inst.instruction |= HI1 (inst.operands[0].reg) << 22;
-      inst.instruction |= LOW4 (inst.operands[0].reg) << 13;
+      inst.instruction |= HI1 (op0) << 22;
+      inst.instruction |= LOW4 (op0) << 13;
       inst.instruction |= t << 12;
-      inst.instruction |= HI1 (inst.operands[1].reg) << 5;
-      inst.instruction |= LOW4 (inst.operands[1].reg) << 1;
+      inst.instruction |= HI1 (op1) << 5;
+      inst.instruction |= LOW4 (op1) << 1;
       inst.is_neon = 1;
     }
   else if (neon_check_type (2, rs, N_F16, N_F32 | N_VFP).type != NT_invtype)
diff --git a/gas/testsuite/gas/arm/mve-vcvt-3.d b/gas/testsuite/gas/arm/mve-vcvt-3.d
index 6a2a1ff..756ff21 100644
--- a/gas/testsuite/gas/arm/mve-vcvt-3.d
+++ b/gas/testsuite/gas/arm/mve-vcvt-3.d
@@ -7,106 +7,106 @@
 Disassembly of section .text:
 [^>]*> ee3f 1e01 	vcvtt.f16.f32	q0, q0
 [^>]*> ee3f 0e01 	vcvtb.f16.f32	q0, q0
+[^>]*> ee3f 1e03 	vcvtt.f16.f32	q0, q1
+[^>]*> ee3f 0e03 	vcvtb.f16.f32	q0, q1
 [^>]*> ee3f 1e05 	vcvtt.f16.f32	q0, q2
 [^>]*> ee3f 0e05 	vcvtb.f16.f32	q0, q2
 [^>]*> ee3f 1e09 	vcvtt.f16.f32	q0, q4
 [^>]*> ee3f 0e09 	vcvtb.f16.f32	q0, q4
-[^>]*> ee3f 1e11 			@ <UNDEFINED> instruction: 0xee3f1e11
-[^>]*> ee3f 0e11 			@ <UNDEFINED> instruction: 0xee3f0e11
-[^>]*> ee3f 1e1d 			@ <UNDEFINED> instruction: 0xee3f1e1d
-[^>]*> ee3f 0e1d 			@ <UNDEFINED> instruction: 0xee3f0e1d
+[^>]*> ee3f 1e0f 	vcvtt.f16.f32	q0, q7
+[^>]*> ee3f 0e0f 	vcvtb.f16.f32	q0, q7
+[^>]*> ee3f 3e01 	vcvtt.f16.f32	q1, q0
+[^>]*> ee3f 2e01 	vcvtb.f16.f32	q1, q0
+[^>]*> ee3f 3e03 	vcvtt.f16.f32	q1, q1
+[^>]*> ee3f 2e03 	vcvtb.f16.f32	q1, q1
+[^>]*> ee3f 3e05 	vcvtt.f16.f32	q1, q2
+[^>]*> ee3f 2e05 	vcvtb.f16.f32	q1, q2
+[^>]*> ee3f 3e09 	vcvtt.f16.f32	q1, q4
+[^>]*> ee3f 2e09 	vcvtb.f16.f32	q1, q4
+[^>]*> ee3f 3e0f 	vcvtt.f16.f32	q1, q7
+[^>]*> ee3f 2e0f 	vcvtb.f16.f32	q1, q7
 [^>]*> ee3f 5e01 	vcvtt.f16.f32	q2, q0
 [^>]*> ee3f 4e01 	vcvtb.f16.f32	q2, q0
+[^>]*> ee3f 5e03 	vcvtt.f16.f32	q2, q1
+[^>]*> ee3f 4e03 	vcvtb.f16.f32	q2, q1
 [^>]*> ee3f 5e05 	vcvtt.f16.f32	q2, q2
 [^>]*> ee3f 4e05 	vcvtb.f16.f32	q2, q2
 [^>]*> ee3f 5e09 	vcvtt.f16.f32	q2, q4
 [^>]*> ee3f 4e09 	vcvtb.f16.f32	q2, q4
-[^>]*> ee3f 5e11 			@ <UNDEFINED> instruction: 0xee3f5e11
-[^>]*> ee3f 4e11 			@ <UNDEFINED> instruction: 0xee3f4e11
-[^>]*> ee3f 5e1d 			@ <UNDEFINED> instruction: 0xee3f5e1d
-[^>]*> ee3f 4e1d 			@ <UNDEFINED> instruction: 0xee3f4e1d
+[^>]*> ee3f 5e0f 	vcvtt.f16.f32	q2, q7
+[^>]*> ee3f 4e0f 	vcvtb.f16.f32	q2, q7
 [^>]*> ee3f 9e01 	vcvtt.f16.f32	q4, q0
 [^>]*> ee3f 8e01 	vcvtb.f16.f32	q4, q0
+[^>]*> ee3f 9e03 	vcvtt.f16.f32	q4, q1
+[^>]*> ee3f 8e03 	vcvtb.f16.f32	q4, q1
 [^>]*> ee3f 9e05 	vcvtt.f16.f32	q4, q2
 [^>]*> ee3f 8e05 	vcvtb.f16.f32	q4, q2
 [^>]*> ee3f 9e09 	vcvtt.f16.f32	q4, q4
 [^>]*> ee3f 8e09 	vcvtb.f16.f32	q4, q4
-[^>]*> ee3f 9e11 			@ <UNDEFINED> instruction: 0xee3f9e11
-[^>]*> ee3f 8e11 			@ <UNDEFINED> instruction: 0xee3f8e11
-[^>]*> ee3f 9e1d 			@ <UNDEFINED> instruction: 0xee3f9e1d
-[^>]*> ee3f 8e1d 			@ <UNDEFINED> instruction: 0xee3f8e1d
-[^>]*> ee3f 1e01 	vcvtt.f16.f32	q0, q0
-[^>]*> ee3f 0e01 	vcvtb.f16.f32	q0, q0
-[^>]*> ee3f 1e05 	vcvtt.f16.f32	q0, q2
-[^>]*> ee3f 0e05 	vcvtb.f16.f32	q0, q2
-[^>]*> ee3f 1e09 	vcvtt.f16.f32	q0, q4
-[^>]*> ee3f 0e09 	vcvtb.f16.f32	q0, q4
-[^>]*> ee3f 1e11 			@ <UNDEFINED> instruction: 0xee3f1e11
-[^>]*> ee3f 0e11 			@ <UNDEFINED> instruction: 0xee3f0e11
-[^>]*> ee3f 1e1d 			@ <UNDEFINED> instruction: 0xee3f1e1d
-[^>]*> ee3f 0e1d 			@ <UNDEFINED> instruction: 0xee3f0e1d
-[^>]*> ee3f de01 	vcvtt.f16.f32	q6, q0
-[^>]*> ee3f ce01 	vcvtb.f16.f32	q6, q0
-[^>]*> ee3f de05 	vcvtt.f16.f32	q6, q2
-[^>]*> ee3f ce05 	vcvtb.f16.f32	q6, q2
-[^>]*> ee3f de09 	vcvtt.f16.f32	q6, q4
-[^>]*> ee3f ce09 	vcvtb.f16.f32	q6, q4
-[^>]*> ee3f de11 			@ <UNDEFINED> instruction: 0xee3fde11
-[^>]*> ee3f ce11 			@ <UNDEFINED> instruction: 0xee3fce11
-[^>]*> ee3f de1d 			@ <UNDEFINED> instruction: 0xee3fde1d
-[^>]*> ee3f ce1d 			@ <UNDEFINED> instruction: 0xee3fce1d
+[^>]*> ee3f 9e0f 	vcvtt.f16.f32	q4, q7
+[^>]*> ee3f 8e0f 	vcvtb.f16.f32	q4, q7
+[^>]*> ee3f fe01 	vcvtt.f16.f32	q7, q0
+[^>]*> ee3f ee01 	vcvtb.f16.f32	q7, q0
+[^>]*> ee3f fe03 	vcvtt.f16.f32	q7, q1
+[^>]*> ee3f ee03 	vcvtb.f16.f32	q7, q1
+[^>]*> ee3f fe05 	vcvtt.f16.f32	q7, q2
+[^>]*> ee3f ee05 	vcvtb.f16.f32	q7, q2
+[^>]*> ee3f fe09 	vcvtt.f16.f32	q7, q4
+[^>]*> ee3f ee09 	vcvtb.f16.f32	q7, q4
+[^>]*> ee3f fe0f 	vcvtt.f16.f32	q7, q7
+[^>]*> ee3f ee0f 	vcvtb.f16.f32	q7, q7
 [^>]*> fe3f 1e01 	vcvtt.f32.f16	q0, q0
 [^>]*> fe3f 0e01 	vcvtb.f32.f16	q0, q0
+[^>]*> fe3f 1e03 	vcvtt.f32.f16	q0, q1
+[^>]*> fe3f 0e03 	vcvtb.f32.f16	q0, q1
 [^>]*> fe3f 1e05 	vcvtt.f32.f16	q0, q2
 [^>]*> fe3f 0e05 	vcvtb.f32.f16	q0, q2
 [^>]*> fe3f 1e09 	vcvtt.f32.f16	q0, q4
 [^>]*> fe3f 0e09 	vcvtb.f32.f16	q0, q4
-[^>]*> fe3f 1e11 			@ <UNDEFINED> instruction: 0xfe3f1e11
-[^>]*> fe3f 0e11 			@ <UNDEFINED> instruction: 0xfe3f0e11
-[^>]*> fe3f 1e1d 			@ <UNDEFINED> instruction: 0xfe3f1e1d
-[^>]*> fe3f 0e1d 			@ <UNDEFINED> instruction: 0xfe3f0e1d
+[^>]*> fe3f 1e0f 	vcvtt.f32.f16	q0, q7
+[^>]*> fe3f 0e0f 	vcvtb.f32.f16	q0, q7
+[^>]*> fe3f 3e01 	vcvtt.f32.f16	q1, q0
+[^>]*> fe3f 2e01 	vcvtb.f32.f16	q1, q0
+[^>]*> fe3f 3e03 	vcvtt.f32.f16	q1, q1
+[^>]*> fe3f 2e03 	vcvtb.f32.f16	q1, q1
+[^>]*> fe3f 3e05 	vcvtt.f32.f16	q1, q2
+[^>]*> fe3f 2e05 	vcvtb.f32.f16	q1, q2
+[^>]*> fe3f 3e09 	vcvtt.f32.f16	q1, q4
+[^>]*> fe3f 2e09 	vcvtb.f32.f16	q1, q4
+[^>]*> fe3f 3e0f 	vcvtt.f32.f16	q1, q7
+[^>]*> fe3f 2e0f 	vcvtb.f32.f16	q1, q7
 [^>]*> fe3f 5e01 	vcvtt.f32.f16	q2, q0
 [^>]*> fe3f 4e01 	vcvtb.f32.f16	q2, q0
+[^>]*> fe3f 5e03 	vcvtt.f32.f16	q2, q1
+[^>]*> fe3f 4e03 	vcvtb.f32.f16	q2, q1
 [^>]*> fe3f 5e05 	vcvtt.f32.f16	q2, q2
 [^>]*> fe3f 4e05 	vcvtb.f32.f16	q2, q2
 [^>]*> fe3f 5e09 	vcvtt.f32.f16	q2, q4
 [^>]*> fe3f 4e09 	vcvtb.f32.f16	q2, q4
-[^>]*> fe3f 5e11 			@ <UNDEFINED> instruction: 0xfe3f5e11
-[^>]*> fe3f 4e11 			@ <UNDEFINED> instruction: 0xfe3f4e11
-[^>]*> fe3f 5e1d 			@ <UNDEFINED> instruction: 0xfe3f5e1d
-[^>]*> fe3f 4e1d 			@ <UNDEFINED> instruction: 0xfe3f4e1d
+[^>]*> fe3f 5e0f 	vcvtt.f32.f16	q2, q7
+[^>]*> fe3f 4e0f 	vcvtb.f32.f16	q2, q7
 [^>]*> fe3f 9e01 	vcvtt.f32.f16	q4, q0
 [^>]*> fe3f 8e01 	vcvtb.f32.f16	q4, q0
+[^>]*> fe3f 9e03 	vcvtt.f32.f16	q4, q1
+[^>]*> fe3f 8e03 	vcvtb.f32.f16	q4, q1
 [^>]*> fe3f 9e05 	vcvtt.f32.f16	q4, q2
 [^>]*> fe3f 8e05 	vcvtb.f32.f16	q4, q2
 [^>]*> fe3f 9e09 	vcvtt.f32.f16	q4, q4
 [^>]*> fe3f 8e09 	vcvtb.f32.f16	q4, q4
-[^>]*> fe3f 9e11 			@ <UNDEFINED> instruction: 0xfe3f9e11
-[^>]*> fe3f 8e11 			@ <UNDEFINED> instruction: 0xfe3f8e11
-[^>]*> fe3f 9e1d 			@ <UNDEFINED> instruction: 0xfe3f9e1d
-[^>]*> fe3f 8e1d 			@ <UNDEFINED> instruction: 0xfe3f8e1d
-[^>]*> fe3f 1e01 	vcvtt.f32.f16	q0, q0
-[^>]*> fe3f 0e01 	vcvtb.f32.f16	q0, q0
-[^>]*> fe3f 1e05 	vcvtt.f32.f16	q0, q2
-[^>]*> fe3f 0e05 	vcvtb.f32.f16	q0, q2
-[^>]*> fe3f 1e09 	vcvtt.f32.f16	q0, q4
-[^>]*> fe3f 0e09 	vcvtb.f32.f16	q0, q4
-[^>]*> fe3f 1e11 			@ <UNDEFINED> instruction: 0xfe3f1e11
-[^>]*> fe3f 0e11 			@ <UNDEFINED> instruction: 0xfe3f0e11
-[^>]*> fe3f 1e1d 			@ <UNDEFINED> instruction: 0xfe3f1e1d
-[^>]*> fe3f 0e1d 			@ <UNDEFINED> instruction: 0xfe3f0e1d
-[^>]*> fe3f de01 	vcvtt.f32.f16	q6, q0
-[^>]*> fe3f ce01 	vcvtb.f32.f16	q6, q0
-[^>]*> fe3f de05 	vcvtt.f32.f16	q6, q2
-[^>]*> fe3f ce05 	vcvtb.f32.f16	q6, q2
-[^>]*> fe3f de09 	vcvtt.f32.f16	q6, q4
-[^>]*> fe3f ce09 	vcvtb.f32.f16	q6, q4
-[^>]*> fe3f de11 			@ <UNDEFINED> instruction: 0xfe3fde11
-[^>]*> fe3f ce11 			@ <UNDEFINED> instruction: 0xfe3fce11
-[^>]*> fe3f de1d 			@ <UNDEFINED> instruction: 0xfe3fde1d
-[^>]*> fe3f ce1d 			@ <UNDEFINED> instruction: 0xfe3fce1d
+[^>]*> fe3f 9e0f 	vcvtt.f32.f16	q4, q7
+[^>]*> fe3f 8e0f 	vcvtb.f32.f16	q4, q7
+[^>]*> fe3f fe01 	vcvtt.f32.f16	q7, q0
+[^>]*> fe3f ee01 	vcvtb.f32.f16	q7, q0
+[^>]*> fe3f fe03 	vcvtt.f32.f16	q7, q1
+[^>]*> fe3f ee03 	vcvtb.f32.f16	q7, q1
+[^>]*> fe3f fe05 	vcvtt.f32.f16	q7, q2
+[^>]*> fe3f ee05 	vcvtb.f32.f16	q7, q2
+[^>]*> fe3f fe09 	vcvtt.f32.f16	q7, q4
+[^>]*> fe3f ee09 	vcvtb.f32.f16	q7, q4
+[^>]*> fe3f fe0f 	vcvtt.f32.f16	q7, q7
+[^>]*> fe3f ee0f 	vcvtb.f32.f16	q7, q7
 [^>]*> fe31 af4d 	vpsttee
-[^>]*> ee3f 1e05 	vcvttt.f16.f32	q0, q2
-[^>]*> ee3f 0e05 	vcvtbt.f16.f32	q0, q2
-[^>]*> fe3f 5e09 	vcvtte.f32.f16	q2, q4
-[^>]*> fe3f 4e09 	vcvtbe.f32.f16	q2, q4
+[^>]*> ee3f 1e03 	vcvttt.f16.f32	q0, q1
+[^>]*> ee3f 0e03 	vcvtbt.f16.f32	q0, q1
+[^>]*> fe3f be05 	vcvtte.f32.f16	q5, q2
+[^>]*> fe3f ae05 	vcvtbe.f32.f16	q5, q2