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author | Srinath Parvathaneni <srinath.parvathaneni@arm.com> | 2024-07-08 17:44:26 +0100 |
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committer | Srinath Parvathaneni <srinath.parvathaneni@arm.com> | 2024-07-08 17:46:00 +0100 |
commit | 2da3319873b794c0cef97ae2db2db96d016cccf5 (patch) | |
tree | fd8da86ae4bd05fca116315156fb29eec1a1d764 /gas | |
parent | 984f5ebb7b54da4aefb26efd70caa01df98cdaf5 (diff) | |
download | binutils-2da3319873b794c0cef97ae2db2db96d016cccf5.zip binutils-2da3319873b794c0cef97ae2db2db96d016cccf5.tar.gz binutils-2da3319873b794c0cef97ae2db2db96d016cccf5.tar.bz2 |
aarch64: Add support for sve2p1 uzpq[1-2] instructions.
This patch adds support for SVE2p1 "uzpq1" and "uzpq2" instructions, spec is
available here [1]
[1]: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions?lang=en
Diffstat (limited to 'gas')
-rw-r--r-- | gas/testsuite/gas/aarch64/sve2p1-6-invalid.d | 2 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/sve2p1-6-invalid.l | 24 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/sve2p1-6-invalid.s | 12 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/sve2p1-6.d | 18 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/sve2p1-6.s | 18 |
5 files changed, 72 insertions, 2 deletions
diff --git a/gas/testsuite/gas/aarch64/sve2p1-6-invalid.d b/gas/testsuite/gas/aarch64/sve2p1-6-invalid.d index 1aa2b39..0971a58 100644 --- a/gas/testsuite/gas/aarch64/sve2p1-6-invalid.d +++ b/gas/testsuite/gas/aarch64/sve2p1-6-invalid.d @@ -1,3 +1,3 @@ -#name: Test of illegal SVE2.1 TBLQ instruction. +#name: Test of illegal SVE2.1 tblq, uzpq1 and uzpq2 instruction. #as: -march=armv9.4-a #error_output: sve2p1-6-invalid.l diff --git a/gas/testsuite/gas/aarch64/sve2p1-6-invalid.l b/gas/testsuite/gas/aarch64/sve2p1-6-invalid.l index 0fea325..c784ca6 100644 --- a/gas/testsuite/gas/aarch64/sve2p1-6-invalid.l +++ b/gas/testsuite/gas/aarch64/sve2p1-6-invalid.l @@ -16,3 +16,27 @@ .*: Info: tblq z0.h, {z31.h}, z0.h .*: Info: tblq z0.d, {z31.d}, z0.d .*: Error: expected an SVE vector register at operand 3 -- `tblq z0.b,{z0.b},{z31.b}' +.*: Error: expected an SVE vector register at operand 2 -- `uzpq1 z0.s,{z0.b},z0.b' +.*: Error: operand mismatch -- `uzpq1 z31.s,z0.b,z0.h' +.*: Info: did you mean this\? +.*: Info: uzpq1 z31.b, z0.b, z0.b +.*: Info: other valid variant\(s\): +.*: Info: uzpq1 z31.h, z0.h, z0.h +.*: Info: uzpq1 z31.s, z0.s, z0.s +.*: Info: uzpq1 z31.d, z0.d, z0.d +.*: Error: expected an SVE vector register at operand 2 -- `uzpq1 z0.s,{z0.s,z1.s},z0.s' +.*: Error: expected an SVE vector register at operand 2 -- `uzpq1 z0.h,{z0.h-z1.h},z0.h' +.*: Error: expected an SVE vector register at operand 1 -- `uzpq1 {z0.s},z31.s,z0.b' +.*: Error: expected an SVE vector register at operand 2 -- `uzpq1 z0.b,{z0.b},{z31.b}' +.*: Error: expected an SVE vector register at operand 2 -- `uzpq2 z0.s,{z0.b},z0.b' +.*: Error: operand mismatch -- `uzpq2 z31.s,z0.b,z0.h' +.*: Info: did you mean this\? +.*: Info: uzpq2 z31.b, z0.b, z0.b +.*: Info: other valid variant\(s\): +.*: Info: uzpq2 z31.h, z0.h, z0.h +.*: Info: uzpq2 z31.s, z0.s, z0.s +.*: Info: uzpq2 z31.d, z0.d, z0.d +.*: Error: expected an SVE vector register at operand 2 -- `uzpq2 z0.s,{z0.s,z1.s},z0.s' +.*: Error: expected an SVE vector register at operand 2 -- `uzpq2 z0.h,{z0.h-z1.h},z0.h' +.*: Error: expected an SVE vector register at operand 1 -- `uzpq2 {z0.s},z31.s,z0.b' +.*: Error: expected an SVE vector register at operand 2 -- `uzpq2 z0.b,{z0.b},{z31.b}' diff --git a/gas/testsuite/gas/aarch64/sve2p1-6-invalid.s b/gas/testsuite/gas/aarch64/sve2p1-6-invalid.s index 0f8300e..8a6df86 100644 --- a/gas/testsuite/gas/aarch64/sve2p1-6-invalid.s +++ b/gas/testsuite/gas/aarch64/sve2p1-6-invalid.s @@ -4,3 +4,15 @@ tblq z0.s, {z0.s, z1.s}, z0.s tblq z0.s, {z0.s - z1.s}, z0.s tblq z0.s, {z31.s}, z0.b tblq z0.b, {z0.b}, {z31.b} +uzpq1 z0.s, {z0.b}, z0.b +uzpq1 z31.s, z0.b, z0.h +uzpq1 z0.s, {z0.s, z1.s}, z0.s +uzpq1 z0.h, {z0.h - z1.h}, z0.h +uzpq1 {z0.s}, z31.s, z0.b +uzpq1 z0.b, {z0.b}, {z31.b} +uzpq2 z0.s, {z0.b}, z0.b +uzpq2 z31.s, z0.b, z0.h +uzpq2 z0.s, {z0.s, z1.s}, z0.s +uzpq2 z0.h, {z0.h - z1.h}, z0.h +uzpq2 {z0.s}, z31.s, z0.b +uzpq2 z0.b, {z0.b}, {z31.b} diff --git a/gas/testsuite/gas/aarch64/sve2p1-6.d b/gas/testsuite/gas/aarch64/sve2p1-6.d index d146903..b36515f 100644 --- a/gas/testsuite/gas/aarch64/sve2p1-6.d +++ b/gas/testsuite/gas/aarch64/sve2p1-6.d @@ -1,4 +1,4 @@ -#name: Test of SVE2.1 TBLQ instruction. +#name: Test of SVE2.1 tblq, uzpq1 and uzpq2 instruction. #as: -march=armv9.4-a #objdump: -dr @@ -16,3 +16,19 @@ .*: 44dffbff tblq z31.d, {z31.d}, z31.d .*: 444ff945 tblq z5.h, {z10.h}, z15.h .*: 4487f861 tblq z1.s, {z3.s}, z7.s +.*: 4400e800 uzpq1 z0.b, z0.b, z0.b +.*: 4400e81f uzpq1 z31.b, z0.b, z0.b +.*: 44c0e800 uzpq1 z0.d, z0.d, z0.d +.*: 4400ebe0 uzpq1 z0.b, z31.b, z0.b +.*: 441fe800 uzpq1 z0.b, z0.b, z31.b +.*: 44dfebff uzpq1 z31.d, z31.d, z31.d +.*: 448fe945 uzpq1 z5.s, z10.s, z15.s +.*: 4454e9ea uzpq1 z10.h, z15.h, z20.h +.*: 4400ec00 uzpq2 z0.b, z0.b, z0.b +.*: 4400ec1f uzpq2 z31.b, z0.b, z0.b +.*: 44c0ec00 uzpq2 z0.d, z0.d, z0.d +.*: 4400efe0 uzpq2 z0.b, z31.b, z0.b +.*: 441fec00 uzpq2 z0.b, z0.b, z31.b +.*: 44dfefff uzpq2 z31.d, z31.d, z31.d +.*: 448fed45 uzpq2 z5.s, z10.s, z15.s +.*: 4454edea uzpq2 z10.h, z15.h, z20.h diff --git a/gas/testsuite/gas/aarch64/sve2p1-6.s b/gas/testsuite/gas/aarch64/sve2p1-6.s index d2a0ef5..b8c6ed7 100644 --- a/gas/testsuite/gas/aarch64/sve2p1-6.s +++ b/gas/testsuite/gas/aarch64/sve2p1-6.s @@ -6,3 +6,21 @@ tblq z0.b, {z0.b}, z31.b tblq z31.d, {z31.d}, z31.d tblq z5.h, {z10.h}, z15.h tblq z1.s, {z3.s}, z7.s + +uzpq1 z0.b, z0.b, z0.b +uzpq1 z31.b, z0.b, z0.b +uzpq1 z0.d, z0.d, z0.d +uzpq1 z0.b, z31.b, z0.b +uzpq1 z0.b, z0.b, z31.b +uzpq1 z31.d, z31.d, z31.d +uzpq1 z5.s, z10.s, z15.s +uzpq1 z10.h, z15.h, z20.h + +uzpq2 z0.b, z0.b, z0.b +uzpq2 z31.b, z0.b, z0.b +uzpq2 z0.d, z0.d, z0.d +uzpq2 z0.b, z31.b, z0.b +uzpq2 z0.b, z0.b, z31.b +uzpq2 z31.d, z31.d, z31.d +uzpq2 z5.s, z10.s, z15.s +uzpq2 z10.h, z15.h, z20.h |