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author | Stafford Horne <shorne@gmail.com> | 2020-05-19 20:40:27 +0900 |
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committer | Stafford Horne <shorne@gmail.com> | 2020-05-19 20:40:27 +0900 |
commit | ae440402f54c634baddc462f8561442befe2cafe (patch) | |
tree | 052696f415d762f88db1d5f92179d225740eb2de /cpu/or1k.cpu | |
parent | 7e05773767820b441b23a16628b55c98cb1aef46 (diff) | |
download | binutils-ae440402f54c634baddc462f8561442befe2cafe.zip binutils-ae440402f54c634baddc462f8561442befe2cafe.tar.gz binutils-ae440402f54c634baddc462f8561442befe2cafe.tar.bz2 |
or1k: Remove 64-bit support, it's not used and it breaks 32-bit hosts
Reported by Rich Felker when building on 32-bit hosts. Backwards jump
negative offsets were not calculated correctly due to improper 32-bit
to 64-bit zero-extension. The 64-bit fields are present because we
are mixing 32-bit and 64-bit architectures in our cpu descriptions.
Removing 64-bit fixes the issue. We don't use 64-bit, there is an architecture
spec for 64-bit but no implementations or simulators. My thought is if
we need them in the future we should do the proper work to support both
32-bit and 64-bit implementations co-existing then.
cpu/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
PR 25184
* or1k.cpu (arch or1k): Remove or64 and or64nd machs.
(ORBIS-MACHS, ORFPX32-MACHS): Remove pmacros.
(cpu or1k64bf, mach or64, mach or64nd): Remove definitions.
* or1kcommon.cpu (h-fdr): Remove hardware.
* or1korfpx.cpu (rDDF, rADF, rBDF): Remove operand definitions.
(float-regreg-insn): Remove lf- mnemonic -d instruction pattern.
(float-setflag-insn-base): Remove lf-sf mnemonic -d pattern.
(float-cust-insn): Remove "lf-cust" cust-num "-d" pattern.
(lf-rem-d, lf-itof-d, lf-ftoi-d, lf-madd-d): Remove.
Diffstat (limited to 'cpu/or1k.cpu')
-rw-r--r-- | cpu/or1k.cpu | 35 |
1 files changed, 3 insertions, 32 deletions
diff --git a/cpu/or1k.cpu b/cpu/or1k.cpu index b796862..9784f7a 100644 --- a/cpu/or1k.cpu +++ b/cpu/or1k.cpu @@ -31,7 +31,7 @@ (comment "OpenRISC 1000") (default-alignment aligned) (insn-lsb0? #t) - (machs or32 or32nd or64 or64nd) + (machs or32 or32nd) (isas openrisc) ) @@ -44,10 +44,8 @@ ) (define-pmacro OR32-MACHS or32,or32nd) -(define-pmacro OR64-MACHS or64,or64nd) -(define-pmacro ORBIS-MACHS or32,or32nd,or64,or64nd) -(define-pmacro ORFPX32-MACHS or32,or32nd,or64,or64nd) -(define-pmacro ORFPX64-MACHS or64,or64nd) +(define-pmacro ORBIS-MACHS or32,or32nd) +(define-pmacro ORFPX32-MACHS or32,or32nd) (define-pmacro ORFPX64A32-MACHS or32,or32nd) ; float64 for 32-bit machs (define-attr @@ -100,33 +98,6 @@ ) ) -(if (keep-mach? (or64 or64nd)) - (begin - (define-cpu - (name or1k64bf) - (comment "OpenRISC 1000 64-bit CPU family") - (insn-endian big) - (data-endian big) - (word-bitsize 64) - (file-transform "64") - ) - - (define-mach - (name or64) - (comment "Generic OpenRISC 1000 64-bit CPU") - (cpu or1k64bf) - (bfd-name "or1k64") - ) - - (define-mach - (name or64nd) - (comment "Generic OpenRISC 1000 ND 64-bit CPU with no branch delay slot") - (cpu or1k64bf) - (bfd-name "or1k64nd") - ) - ) - ) - (include "or1kcommon.cpu") (include "or1korbis.cpu") (include "or1korfpx.cpu") |