cpu/or1k: Add support for orfp64a32 spec

This patch adds support for OpenRISC 64-bit FPU operations on 32-bit cores by
using register pairs.  The functionality has been added to OpenRISC architecture
specification version 1.3 as per architecture proposal 14[0].

For supporting assembly of both 64-bit and 32-bit precision instructions we have
defined CGEN_VALIDATE_INSN_SUPPORTED.  This allows cgen to use 64-bit bit
architecture assembly parsing on 64-bit toolchains and 32-bit architecture
assembly parsing on 32-bit toolchains.  Without this the assembler has issues
parsing register pairs.

This patch also contains a few fixes to the symantics for existing OpenRISC
single and double precision FPU operations.

[0] https://openrisc.io/proposals/orfpx64a32

cpu/ChangeLog:

yyyy-mm-dd  Andrey Bacherov  <avbacherov@opencores.org>
	    Stafford Horne  <shorne@gmail.com>

	* or1k.cpu (ORFPX64A32-MACHS): New pmacro.
	(ORFPX-MACHS): Removed pmacro.
	* or1k.opc (or1k_cgen_insn_supported): New function.
	(CGEN_VALIDATE_INSN_SUPPORTED): Define macro.
	(parse_regpair, print_regpair): New functions.
	* or1kcommon.cpu (h-spr, spr-shift, spr-address, h-gpr): Reorder
	and add comments.
	(h-fdr): Update comment to indicate or64.
	(reg-pair-reg-lo, reg-pair-reg-hi): New pmacros for register pairs.
	(h-fd32r): New hardware for 64-bit fpu registers.
	(h-i64r): New hardware for 64-bit int registers.
	* or1korbis.cpu (f-resv-8-1): New field.
	* or1korfpx.cpu (rDSF, rASF, rBSF): Update attribute to ORFPX32-MACHS.
	(rDDF, rADF, rBDF): Update operand comment to indicate or64.
	(f-rdoff-10-1, f-raoff-9-1, f-rboff-8-1): New fields.
	(h-roff1): New hardware.
	(double-field-and-ops mnemonic): New pmacro to generate operations
	rDD32F, rAD32F, rBD32F, rDDI and rADI.
	(float-regreg-insn): Update single precision generator to MACH
	ORFPX32-MACHS.  Add generator for or32 64-bit instructions.
	(float-setflag-insn): Update single precision generator to MACH
	ORFPX32-MACHS.  Fix double instructions from single to double
	precision.  Add generator for or32 64-bit instructions.
	(float-cust-insn cust-num): Update single precision generator to MACH
	ORFPX32-MACHS.  Add generator for or32 64-bit instructions.
	(lf-rem-s, lf-itof-s, lf-ftoi-s, lf-madd-s): Update MACH to
	ORFPX32-MACHS.
	(lf-rem-d): Fix operation from mod to rem.
	(lf-rem-d32, lf-itof-d32, lf-ftoi-d32, lf-madd-d32): New instruction.
	(lf-itof-d): Fix operands from single to double.
	(lf-ftoi-d): Update operand mode from DI to WI.

1 files changed, 8 insertions, 7 deletions

diff --git a/cpu/or1k.cpu b/cpu/or1k.cpu
index 3a932bc..e1ae1b8 100644
--- a/cpu/or1k.cpu
+++ b/cpu/or1k.cpu
@@ -1,8 +1,9 @@
 ; OpenRISC 1000 architecture.  -*- Scheme -*-
-; Copyright 2000-2014 Free Software Foundation, Inc.
+; Copyright 2000-2019 Free Software Foundation, Inc.
 ; Contributed for OR32 by Johan Rydberg, jrydberg@opencores.org
 ; Modified by Julius Baxter, juliusbaxter@gmail.com
 ; Modified by Peter Gavin, pgavin@gmail.com
+; Modified by Andrey Bacherov, avbacherov@opencores.org
 ;
 ; This program is free software; you can redistribute it and/or modify
 ; it under the terms of the GNU General Public License as published by
@@ -42,12 +43,12 @@
   (base-insn-bitsize 32)
   )
 
-(define-pmacro OR32-MACHS    or32,or32nd)
-(define-pmacro OR64-MACHS    or64,or64nd)
-(define-pmacro ORBIS-MACHS   or32,or32nd,or64,or64nd)
-(define-pmacro ORFPX-MACHS   or32,or32nd,or64,or64nd)
-(define-pmacro ORFPX32-MACHS or32,or32nd,or64,or64nd)
-(define-pmacro ORFPX64-MACHS or64,or64nd)
+(define-pmacro OR32-MACHS       or32,or32nd)
+(define-pmacro OR64-MACHS       or64,or64nd)
+(define-pmacro ORBIS-MACHS      or32,or32nd,or64,or64nd)
+(define-pmacro ORFPX32-MACHS    or32,or32nd,or64,or64nd)
+(define-pmacro ORFPX64-MACHS    or64,or64nd)
+(define-pmacro ORFPX64A32-MACHS or32,or32nd) ; float64 for 32-bit machs
 
 (define-attr
   (for model)