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| author | Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> | 2020-09-28 15:41:23 +0100 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2020-09-28 15:41:23 +0100 |
| commit | 3454861d897960237c852040ded04f70e1bda070 (patch) | |
| tree | fde951ea4dfdb560153b9c8dac8d5bb133f87421 | |
| parent | 1ff8e4010580a425e5f4e7bd14471154b2ab33c9 (diff) | |
| download | binutils-3454861d897960237c852040ded04f70e1bda070.zip binutils-3454861d897960237c852040ded04f70e1bda070.tar.gz binutils-3454861d897960237c852040ded04f70e1bda070.tar.bz2 | |
This patch introduces ETE (Embedded Trace Extension) system registers for the AArch64 architecture.
gas * testsuite/gas/aarch64/ete.d: New test.
* testsuite/gas/aarch64/ete.s: New test.
opcodes * aarch64-opc.c: Add ETE system registers TRCEXTINSELR<0-3> and TRCRSR.
| -rw-r--r-- | gas/ChangeLog | 5 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/ete.d | 18 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/ete.s | 15 | ||||
| -rw-r--r-- | opcodes/ChangeLog | 4 | ||||
| -rw-r--r-- | opcodes/aarch64-opc.c | 6 |
5 files changed, 48 insertions, 0 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 565c131..18c19ba 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,5 +1,10 @@ 2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> + * testsuite/gas/aarch64/ete.d: New test. + * testsuite/gas/aarch64/ete.s: New test. + +2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> + * testsuite/gas/aarch64/trbe-invalid.d: New test. * testsuite/gas/aarch64/trbe-invalid.l: New test. * testsuite/gas/aarch64/trbe-invalid.s: New test. diff --git a/gas/testsuite/gas/aarch64/ete.d b/gas/testsuite/gas/aarch64/ete.d new file mode 100644 index 0000000..511b4fb --- /dev/null +++ b/gas/testsuite/gas/aarch64/ete.d @@ -0,0 +1,18 @@ +#name: ETE System registers +#objdump: -dr + +.*: file format .* + +Disassembly of section \.text: + +0+ <.*>: +[^:]+: d5310880 mrs x0, trcextinselr0 +[^:]+: d5310980 mrs x0, trcextinselr1 +[^:]+: d5310a80 mrs x0, trcextinselr2 +[^:]+: d5310b80 mrs x0, trcextinselr3 +[^:]+: d5310a00 mrs x0, trcrsr +[^:]+: d5110880 msr trcextinselr0, x0 +[^:]+: d5110980 msr trcextinselr1, x0 +[^:]+: d5110a80 msr trcextinselr2, x0 +[^:]+: d5110b80 msr trcextinselr3, x0 +[^:]+: d5110a00 msr trcrsr, x0 diff --git a/gas/testsuite/gas/aarch64/ete.s b/gas/testsuite/gas/aarch64/ete.s new file mode 100644 index 0000000..72720ee --- /dev/null +++ b/gas/testsuite/gas/aarch64/ete.s @@ -0,0 +1,15 @@ +/* ETE System registers. */ + +/* Read from system register. */ +mrs x0, trcextinselr0 +mrs x0, trcextinselr1 +mrs x0, trcextinselr2 +mrs x0, trcextinselr3 +mrs x0, trcrsr + +/* Write to system register. */ +msr trcextinselr0, x0 +msr trcextinselr1, x0 +msr trcextinselr2, x0 +msr trcextinselr3, x0 +msr trcrsr, x0 diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 291c52e..e9dfb78 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,9 @@ 2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> + * aarch64-opc.c: Add ETE system registers TRCEXTINSELR<0-3> and TRCRSR. + +2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> + * aarch64-opc.c: Add TRBE system registers TRBIDR_EL1 , TRBBASER_EL1 , TRBLIMITR_EL1 , TRBMAR_EL1 , TRBPTR_EL1, TRBSR_EL1 and TRBTRG_EL1. diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 1be8d21..83afb1f 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -4319,6 +4319,12 @@ const aarch64_sys_reg aarch64_sys_regs [] = SR_CORE("trbsr_el1", CPENC (3,0,C9,C11,3), 0), SR_CORE("trbtrg_el1", CPENC (3,0,C9,C11,6), 0), + SR_CORE ("trcextinselr0", CPENC (2,1,C0,C8,4), 0), + SR_CORE ("trcextinselr1", CPENC (2,1,C0,C9,4), 0), + SR_CORE ("trcextinselr2", CPENC (2,1,C0,C10,4), 0), + SR_CORE ("trcextinselr3", CPENC (2,1,C0,C11,4), 0), + SR_CORE ("trcrsr", CPENC (2,1,C0,C10,0), 0), + { 0, CPENC (0,0,0,0,0), 0, 0 } }; |