From 5dac17852d746f6ea26736a7cdbd073b201ce08f Mon Sep 17 00:00:00 2001 From: Palmer Dabbelt Date: Wed, 3 May 2017 23:56:31 -0700 Subject: Bump binutils, for a host of backports * RISC-V: Change CALL macro to use ra as the temporary address register * RISC-V: Allow 32-bit BFD to handle 64-bit objects * RISC-V: Resurrect GP-relative disassembly hints * RISC-V/bfd: Hook elf_backend_object_p to set the mach type. --- riscv-binutils-gdb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/riscv-binutils-gdb b/riscv-binutils-gdb index 8b42551..98b857e 160000 --- a/riscv-binutils-gdb +++ b/riscv-binutils-gdb @@ -1 +1 @@ -Subproject commit 8b425518357ec18139d1613a8ff76edc363a6fe7 +Subproject commit 98b857eaace81a69c2dbc2ce4d59ac8eab6e63cf -- cgit v1.1 From 4b0a9f97c84f47253d6c88a7b8c44d11852b1f2e Mon Sep 17 00:00:00 2001 From: Palmer Dabbelt Date: Wed, 3 May 2017 23:53:55 -0700 Subject: Bump glibc, for a __global_pointer$ change * RISC-V: Prohibit relaxing the initial gp generation --- riscv-glibc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/riscv-glibc b/riscv-glibc index ee09c7b..23eb264 160000 --- a/riscv-glibc +++ b/riscv-glibc @@ -1 +1 @@ -Subproject commit ee09c7b159c68340ceb7e8d19a7ad00f4e89f080 +Subproject commit 23eb264299c083cff4e96315bdd644ce90782247 -- cgit v1.1