| Age | Commit message (Collapse) | Author | Files | Lines |
|---|
|
|
|
Commit ids changed on branch merge, so accidentally pointing at wrong
commit id, on deleted branch.
|
|
Backport following patches from upstream:
- RISC-V: Check multiletter extension has more than 1 letter
- RISC-V: Add configure option: --with-multilib-generator to flexible config multi-lib settings.
- RISC-V: Refine riscv_parse_arch_string
- RISC-V: Extend syntax for the multilib-generator
- RISC-V: Handle implied extension in multilib-generator
- RISC-V: Add support for -mcpu option.
- RISC-V: Define __riscv_cmodel_medany for PIC mode.
|
|
|
|
|
|
- Fix https://github.com/riscv/riscv-gcc/issues/190
|
|
Backport following patches:
- RISC-V: Add shorten_memrefs pass.
- RISC-V: Make unique SECCAT_SRODATA names start with .srodata (not .sdata2)
- RISC-V: Update march parser
- RISC-V: Handle implied extension for -march parser
- Fix alignment for local variable [PR90811]
- RISC-V: Optimize si to di zero-extend followed by left shift.
- RISC-V: Make __divdi3 handle div by zero same as hardware.
- RISC-V: Describe correct USEs for gpr_save pattern [PR95252]
- RISC-V: Unify the output asm pattern between gpr_save and gpr_restore pattern.
|
|
- With few bugfix backport:
- riscv: Fix up riscv_atomic_assign_expand_fenv [PR94950]
- testsuite: Require gnu-tm support for pr94856.C
|
|
|
|
|
|
Backport following patches:
- RISC-V: Fix bad insn splits with paradoxical subregs.
- RISC-V: Fix more splitters accidentally calling gen_reg_rtx.
- Fix for PR rtl-optimization/89795
|
|
|
|
Backport following patches:
- RISC-V: Handle g extension in multilib-generator
- RISC-V: Handle extensions combination correctly in multilib-generator.
- RISC-V: Promote type correctly for libcalls
- RISC-V: Fix testcase on rv64
- RISC-V: Raise error on unexpected ISA string at end.
|
|
backport following patches:
- RISC-V: Add -malign-data= option.
|
|
backport following patches:
- RISC-V: Fix epilogue unwind info with fp and single sp adjust
- RISC-V: Generalize -march support, add ELF attribute support.
- RISC-V: Add libstdc++ check-abi support.
- RISC-V: Fix %lo overflow with BLKmode references.
- RISC-V: Add sifive-7 pipeline description.
- RISC-V: Fix __riscv_compressed regression.
- RISC-V: Promode modes of constant loads for store insns.
- RISC-V: Short-forward-branch opt for SiFive 7 series cores.
- RISC-V: Move STARTFILE_PREFIX_SPEC into target OS files.
- RISC-V: Fix splitter for 32-bit AND on 64-bit target.
- https://github.com/riscv/riscv-gcc/issues/161
- Fix typo in riscv_get_interrupt_type and riscv_merge_decl_attributes.
- Correctly ignore empty C++ structs when flattening for ABI
- Add --disable-tm-clone-registry libgcc configure option.
|
|
|
|
|
|
|
|
|
|
This has no additional patches, but it does result in a whole host of
test suite failures.
|
|
b731149757b9 RISC-V: Implement movmemsi
605bc7b5e06a RISC-V: Define MUSL_DYNAMIC_LINKER
|
|
This has the same commits as the previous hash, it's just on the proper
branch now (so it's round-tripped through upstream's trunk). I archived
the old commit.
|
|
b66926e93524 RISC-V: Emit "i" suffix for instructions with immediate operands
a2fc54542b66 RISC-V: If -m[no-]strict-align is not passed, assume its value from -mtune
f34a83e82258 RISC-V: Set SLOW_BYTE_ACCESS=1
7dde69e2c5f7 RISC-V: Handle non-legitimate address in riscv_legitimize_move
1751fbe7b9e8 RISC-V: Use "@minus{}2 GB" instead of "-2 GB" in invoke.texi
6d1f1f891869 RISC-V: Document the medlow and medany code models
|
|
Much like the recent binutils changes, I've now moved to a different GCC
strategy. We have the following commits right now
d2d1f783b2c1 RISC-V: Correct and improve the "-mabi" documentation
d13dd0242604 RISC-V: Add Sign/Zero extend patterns for PIC loads
341375637a7d RISC-V: Add -mstrict-align option
f47f9c2b3b90 RISC-V: Unify indention in riscv.md
Note that this still fails a handful of the GCC regression tests, so
it's not ready to go yet.
|
|
|
|
|
|
16210e6 RISC-V: Handle non-legitimate address in riscv_legitimize_move
|
|
ff03ebe RISC-V: Add Sign/Zero extend patterns for PIC loads
2fe94d5 RISC-V: Add -mstrict-align option
f9771ad RISC-V: Unify indention in riscv.md
|
|
|
|
GCC has created a stable branch upstream for the 7 release series. This
patch moves our GCC sources over to that branch, just like we did for
binutils.
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
- -march controls which instructions may be emitted, and does not
affect ABI.
- -mno-float is equivalent to passing neither F for D to -march;
-msingle-float is equivalent to passing F but not D to -march;
and -mdouble-float is equivalent to passing F and D to -march.
- -mfloat-abi controls which calling convention is used: "soft" means
no args passed in registers; "single" means only single-precision
values are passed in regisers; "double" means single- and
double-precision values are passed in registers.
- -mfloat-abi defaults to "soft" if the D extension is not present,
or "double" if it is.
- GCC will issue an error if -mfloat-abi requires an extension not
provided by -march, but vice-versa is OK.
Closes #187 (I hope).
@kito-cheng can you test this and let me know what I need to fix?
|
|
Soft-float calling convention is default, but an alternate hard-float
calling convention (with doubles passed as in soft-float, but floats
passed as in hard-float) is supported.
|
|
|
|
|
|
|
|
|
