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This commit bumps GCC from 12.2.0 to 13.2.0 and adjusts the allowlist
accordingly (for glibc and newlib multilib builds).
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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* Bump gcc branch to 12.2 release.
* Adjust line style in allowlist
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We weren't using the global addressing peepholes.
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In addition to some small changes, here's the bigger ones:
* gen_rtx_SET no longer takes a VOIDmode, apparently that was the only
valid argument in that position so it's been dropped.
* GEN_CALL is now gen_call.
* The #defines in riscv.h need to be defined to 1, not just defined,
since they're now used in "if ()" statements.
* glibc is passed "--disable-werror", since the new GCC throws a bunch
of pointless errors like "misleading indentation". This is all in
upstream glibc code.
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I screwed up a couple commits back.
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I didn't properly check for changes required to support MEMMODEL_SYNC_*, this
looks like the last one I need to make (based on git grep). The rationale is
the same as the previous one.
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This way we'll be able to see what memory model is being passed, in case
someone has another problem with additional memory models in the future.
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There was one change required here: support for "MEMMODEL_SYNC_*". This
very long GCC post <https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65697>
talks about the formalization of the C++ memory model. It looks like
this is it to allow for some ARM stupidity where they can speculatively
issue some memory operations.
As far as I can tell, the right thing to do here is to just treat the
SYNC versions the same as the non-SYNC versions -- this is the same
thing ia64 and rs600 do. I can't find "MEMMODEL_SYNC" anywhere else
interesting, so there might be some flag to set to avoid doing this, but
I couldn't find it.
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An andi instruction is faster on implementations with 1bit per cycle
shifter units.
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LRA is the new register allocator, replacing the complicated reload pass.
It's a much better design, and it seems likely that it will ultimately
replace reload altogether. Rather than contending with the vagaries of
both schemes, I think we should abandon reload altogether.
For RISC-V, LRA seems to have a mixed performance impact, but it will
get better over time.
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We have no pattern for moving between a double-precision floating-point
register and an integer register in RV32. This makes the compiler choke.
This workaround raises the cost of those moves significantly. This has
no effect on -O0, which always worked; the other -Ox all seem to work
now. For obvious reasons, this makes me very uncomfortable. But,
as far as I can tell, MIPS is relying on the same behavior.
If this bug rears its head again, no big deal: we can add an "instruction"
for this, which does something like
addi sp, sp, -16
fsd f4, 0(sp)
lw x6, 0(sp)
lw x7, 4(sp)
addi sp, sp, 16
This is heinous, but it's always correct. If the cost model is right,
the compiler will only very rarely invoke it, so the performance cost
of this ingorious hack will be hidden. @palmer-dabbelt
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The codegen is crappy since it can't be scheduled, but at least it's
not broken like the split was.
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gcc: re-organize multilib hierarchy for newlib gcc.
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Fix 1st-level hierarchy to 64/32 not soft-float. It is same with glibc gcc, also.
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It's still flaky with respect to DWARF and so should be considered
experimental.
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Also, fix some whitespace errors.
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We were generating incorrect DWARF frame info.
This seems to resolve #85.
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We sometimes use t0 as a link register, e.g. for the compressed prologues
and epilogues, and so we want microarchitectures to push the RAS when
rd=t0 and pop the RAS when rs1=t0. Thus, we want to avoid using t0 for
indirect calls to avoid errant RAS operations.
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When a function clobbers only s0 and s1, but not ra, we don't want to use
the save/restore routines because the stack would grow more than needed.
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This simply stops GCC's parse whenever it sees an 'X' in an ISA
string. This is the best I can do until some clarafications are made
to the RISC-V user spec that allows ISA extensions to be parsed.
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These call library routines to save and restore the callee-saved registers
and link register.
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