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| author | Palmer Dabbelt <palmer.dabbelt@eecs.berkeley.edu> | 2015-12-27 19:56:47 -0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmer.dabbelt@eecs.berkeley.edu> | 2015-12-27 19:59:37 -0800 |
| commit | a347833d9c10c6058c9a5347ad5230688558be43 (patch) | |
| tree | 3009245ad25db89f43dbf564864339be2e365027 /gcc | |
| parent | cc5321b5a30c2eac394d61d070aea5293ee4a3f9 (diff) | |
| download | riscv-gnu-toolchain-a347833d9c10c6058c9a5347ad5230688558be43.zip riscv-gnu-toolchain-a347833d9c10c6058c9a5347ad5230688558be43.tar.gz riscv-gnu-toolchain-a347833d9c10c6058c9a5347ad5230688558be43.tar.bz2 | |
Print a bit before failing on invalid memory models
This way we'll be able to see what memory model is being passed, in case
someone has another problem with additional memory models in the future.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/gcc/config/riscv/sync.md | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/gcc/gcc/config/riscv/sync.md b/gcc/gcc/config/riscv/sync.md index e8c9a7a..576e84d 100644 --- a/gcc/gcc/config/riscv/sync.md +++ b/gcc/gcc/config/riscv/sync.md @@ -52,7 +52,9 @@ (match_operand:SI 1 "const_int_operand" "")] ;; model "" { - switch (INTVAL (operands[1])) + long model = INTVAL (operands[1]); + + switch (model) { case MEMMODEL_SEQ_CST: case MEMMODEL_SYNC_SEQ_CST: @@ -66,6 +68,7 @@ case MEMMODEL_SYNC_RELEASE: return "fence rw,w"; default: + fprintf(stderr, "mem_thread_fence_1(%ld)\n", model); gcc_unreachable(); } }) |