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| author | Joel Vandergriendt <joel@vectorblox.com> | 2015-12-14 12:35:58 -0800 |
|---|---|---|
| committer | Joel Vandergriendt <joel@vectorblox.com> | 2015-12-14 12:35:58 -0800 |
| commit | 14087f333d5baedb511935f60844a0b86042ed97 (patch) | |
| tree | 90af9372f26a15f76c12880d1beab27622b47585 /gcc | |
| parent | c85720ab93f5caab980884206e936bd037010526 (diff) | |
| download | riscv-gnu-toolchain-14087f333d5baedb511935f60844a0b86042ed97.zip riscv-gnu-toolchain-14087f333d5baedb511935f60844a0b86042ed97.tar.gz riscv-gnu-toolchain-14087f333d5baedb511935f60844a0b86042ed97.tar.bz2 | |
replace shift istruction with and instructuction in __mulsi3
An andi instruction is faster on implementations with 1bit per cycle
shifter units.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/libgcc/config/riscv/mul.S | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/gcc/libgcc/config/riscv/mul.S b/gcc/libgcc/config/riscv/mul.S index 5c93541..f5061b9 100644 --- a/gcc/libgcc/config/riscv/mul.S +++ b/gcc/libgcc/config/riscv/mul.S @@ -11,8 +11,8 @@ __muldi3: mv a2, a0 li a0, 0 .L1: - slli a3, a1, _RISCV_SZPTR-1 - bgez a3, .L2 + andi a3, a1, 1 + beqz a3, .L2 add a0, a0, a2 .L2: srli a1, a1, 1 |