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| author | Nelson Chu <nelson.chu@sifive.com> | 2019-12-19 09:34:15 +0800 |
|---|---|---|
| committer | Nelson Chu <nelson.chu@sifive.com> | 2019-12-19 09:34:20 +0800 |
| commit | 76019f2e39db8426254c6f6827e9c17c4472e1a4 (patch) | |
| tree | 56eef21145038e3f10bd021607a5875f872c0be9 | |
| parent | a6aebb9b58580646ec790e68d105f3d9b5c35a94 (diff) | |
| download | riscv-gnu-toolchain-76019f2e39db8426254c6f6827e9c17c4472e1a4.zip riscv-gnu-toolchain-76019f2e39db8426254c6f6827e9c17c4472e1a4.tar.gz riscv-gnu-toolchain-76019f2e39db8426254c6f6827e9c17c4472e1a4.tar.bz2 | |
Update binutils to version 0.8-draft-20191207.
This should be the last update for version 0.8-draft.
Please see the details as follows:
* Support limited vector load/store and move whole register.
* Accept constant 0 for address of vector amo instruction.
* Support the vector instruction constraints.
| m--------- | riscv-binutils | 0 |
1 files changed, 0 insertions, 0 deletions
diff --git a/riscv-binutils b/riscv-binutils -Subproject c2639356763a5346da3ff46f73bbfc82e3e4531 +Subproject 9251ca5ae8ed5558d88aac74e04d7521b6fd3e6 |