aboutsummaryrefslogtreecommitdiff
path: root/opcodes/rl78-dis.c
blob: 799cd3823e4042b29f732897633b294e9a162bc5 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
/* Disassembler code for Renesas RL78.
   Copyright (C) 2011-2017 Free Software Foundation, Inc.
   Contributed by Red Hat.
   Written by DJ Delorie.

   This file is part of the GNU opcodes library.

   This library is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3, or (at your option)
   any later version.

   It is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
   License for more details.

   You should have received a copy of the GNU General Public License
   along with this program; if not, write to the Free Software
   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
   MA 02110-1301, USA.  */

#include "sysdep.h"
#include <stdio.h>

#include "bfd.h"
#include "elf-bfd.h"
#include "dis-asm.h"
#include "opcode/rl78.h"
#include "elf/rl78.h"

#include <setjmp.h>

#define DEBUG_SEMANTICS 0

typedef struct
{
  bfd_vma pc;
  disassemble_info * dis;
} RL78_Data;

struct private
{
  OPCODES_SIGJMP_BUF bailout;
};

static int
rl78_get_byte (void * vdata)
{
  bfd_byte buf[1];
  RL78_Data *rl78_data = (RL78_Data *) vdata;
  int status;

  status = rl78_data->dis->read_memory_func (rl78_data->pc,
					     buf,
					     1,
					     rl78_data->dis);
  if (status != 0)
    {
      struct private *priv = (struct private *) rl78_data->dis->private_data;

      rl78_data->dis->memory_error_func (status, rl78_data->pc,
					 rl78_data->dis);
      OPCODES_SIGLONGJMP (priv->bailout, 1);
    }

  rl78_data->pc ++;
  return buf[0];
}

static char const *
register_names[] =
{
  "",
  "x", "a", "c", "b", "e", "d", "l", "h",
  "ax", "bc", "de", "hl",
  "sp", "psw", "cs", "es", "pmc", "mem"
};

static char const *
condition_names[] =
{
  "t", "f", "c", "nc", "h", "nh", "z", "nz"
};

static int
indirect_type (int t)
{
  switch (t)
    {
    case RL78_Operand_Indirect:
    case RL78_Operand_BitIndirect:
    case RL78_Operand_PostInc:
    case RL78_Operand_PreDec:
      return 1;
    default:
      return 0;
    }
}

static int
print_insn_rl78_common (bfd_vma addr, disassemble_info * dis, RL78_Dis_Isa isa)
{
  int rv;
  RL78_Data rl78_data;
  RL78_Opcode_Decoded opcode;
  const char * s;
#if DEBUG_SEMANTICS
  static char buf[200];
#endif
  struct private priv;

  dis->private_data = (PTR) &priv;
  rl78_data.pc = addr;
  rl78_data.dis = dis;

  if (OPCODES_SIGSETJMP (priv.bailout) != 0)
    {
      /* Error return.  */
      return -1;
    }

  rv = rl78_decode_opcode (addr, &opcode, rl78_get_byte, &rl78_data, isa);

  dis->bytes_per_line = 10;

#define PR (dis->fprintf_func)
#define PS (dis->stream)
#define PC(c) PR (PS, "%c", c)

  s = opcode.syntax;

#if DEBUG_SEMANTICS

  switch (opcode.id)
    {
    case RLO_unknown: s = "uknown"; break;
    case RLO_add: s = "add: %e0%0 += %e1%1"; break;
    case RLO_addc: s = "addc: %e0%0 += %e1%1 + CY"; break;
    case RLO_and: s = "and: %e0%0 &= %e1%1"; break;
    case RLO_branch: s = "branch: pc = %e0%0"; break;
    case RLO_branch_cond: s = "branch_cond: pc = %e0%0 if %c1 / %e1%1"; break;
    case RLO_branch_cond_clear: s = "branch_cond_clear: pc = %e0%0 if %c1 / %e1%1, %e1%1 = 0"; break;
    case RLO_call: s = "call: pc = %e1%0"; break;
    case RLO_cmp: s = "cmp: %e0%0 - %e1%1"; break;
    case RLO_mov: s = "mov: %e0%0 = %e1%1"; break;
    case RLO_or: s = "or: %e0%0 |= %e1%1"; break;
    case RLO_rol: s = "rol: %e0%0 <<= %e1%1"; break;
    case RLO_rolc: s = "rol: %e0%0 <<= %e1%1,CY"; break;
    case RLO_ror: s = "ror: %e0%0 >>= %e1%1"; break;
    case RLO_rorc: s = "ror: %e0%0 >>= %e1%1,CY"; break;
    case RLO_sar: s = "sar: %e0%0 >>= %e1%1 signed"; break;
    case RLO_sel: s = "sel: rb = %1"; break;
    case RLO_shr: s = "shr: %e0%0 >>= %e1%1 unsigned"; break;
    case RLO_shl: s = "shl: %e0%0 <<= %e1%1"; break;
    case RLO_skip: s = "skip: if %c1"; break;
    case RLO_sub: s = "sub: %e0%0 -= %e1%1"; break;
    case RLO_subc: s = "subc: %e0%0 -= %e1%1 - CY"; break;
    case RLO_xch: s = "xch: %e0%0 <-> %e1%1"; break;
    case RLO_xor: s = "xor: %e0%0 ^= %e1%1"; break;
    }

  sprintf(buf, "%s%%W%%f\t\033[32m%s\033[0m", s, opcode.syntax);
  s = buf;

#endif

  for (; *s; s++)
    {
      if (*s != '%')
	{
	  PC (*s);
	}
      else
	{
	  RL78_Opcode_Operand * oper;
	  int do_hex = 0;
	  int do_addr = 0;
	  int do_es = 0;
	  int do_sfr = 0;
	  int do_cond = 0;
	  int do_bang = 0;

	  while (1)
	    {
	      s ++;
	      switch (*s)
		{
		case 'x':
		  do_hex = 1;
		  break;
		case '!':
		  do_bang = 1;
		  break;
		case 'e':
		  do_es = 1;
		  break;
		case 'a':
		  do_addr = 1;
		  break;
		case 's':
		  do_sfr = 1;
		  break;
		case 'c':
		  do_cond = 1;
		  break;
		default:
		  goto no_more_modifiers;
		}
	    }
	no_more_modifiers:;

	  switch (*s)
	    {
	    case '%':
	      PC ('%');
	      break;

#if DEBUG_SEMANTICS

	    case 'W':
	      if (opcode.size == RL78_Word)
		PR (PS, " \033[33mW\033[0m");
	      break;

	    case 'f':
	      if (opcode.flags)
		{
		  char *comma = "";
		  PR (PS, "  \033[35m");

		  if (opcode.flags & RL78_PSW_Z)
		    { PR (PS, "Z"); comma = ","; }
		  if (opcode.flags & RL78_PSW_AC)
		    { PR (PS, "%sAC", comma); comma = ","; }
		  if (opcode.flags & RL78_PSW_CY)
		    { PR (PS, "%sCY", comma); comma = ","; }
		  PR (PS, "\033[0m");
		}
	      break;

#endif

	    case '0':
	    case '1':
	      oper = *s == '0' ? &opcode.op[0] : &opcode.op[1];
	    if (do_es)
	      {
		if (oper->use_es && indirect_type (oper->type))
		  PR (PS, "es:");
	      }

	    if (do_bang)
	      {
		/* If we are going to display SP by name, we must omit the bang.  */
		if ((oper->type == RL78_Operand_Indirect
		     || oper->type == RL78_Operand_BitIndirect)
		    && oper->reg == RL78_Reg_None
		    && do_sfr
		    && ((oper->addend == 0xffff8 && opcode.size == RL78_Word)
			|| (oper->addend == 0x0fff8 && do_es && opcode.size == RL78_Word)))
		  ;
		else
		  PC ('!');
	      }

	    if (do_cond)
	      {
		PR (PS, "%s", condition_names[oper->condition]);
		break;
	      }

	    switch (oper->type)
	      {
	      case RL78_Operand_Immediate:
		if (do_addr)
		  dis->print_address_func (oper->addend, dis);
		else if (do_hex
			 || oper->addend > 999
			 || oper->addend < -999)
		  PR (PS, "%#x", oper->addend);
		else
		  PR (PS, "%d", oper->addend);
		break;

	      case RL78_Operand_Register:
		PR (PS, "%s", register_names[oper->reg]);
		break;

	      case RL78_Operand_Bit:
		PR (PS, "%s.%d", register_names[oper->reg], oper->bit_number);
		break;

	      case RL78_Operand_Indirect:
	      case RL78_Operand_BitIndirect:
		switch (oper->reg)
		  {
		  case RL78_Reg_None:
		    if (oper->addend == 0xffffa && do_sfr && opcode.size == RL78_Byte)
		      PR (PS, "psw");
		    else if (oper->addend == 0xffff8 && do_sfr && opcode.size == RL78_Word)
		      PR (PS, "sp");
		    else if (oper->addend == 0x0fff8 && do_sfr && do_es && opcode.size == RL78_Word)
		      PR (PS, "sp");
                    else if (oper->addend == 0xffff8 && do_sfr && opcode.size == RL78_Byte)
                      PR (PS, "spl");
                    else if (oper->addend == 0xffff9 && do_sfr && opcode.size == RL78_Byte)
                      PR (PS, "sph");
                    else if (oper->addend == 0xffffc && do_sfr && opcode.size == RL78_Byte)
                      PR (PS, "cs");
                    else if (oper->addend == 0xffffd && do_sfr && opcode.size == RL78_Byte)
                      PR (PS, "es");
                    else if (oper->addend == 0xffffe && do_sfr && opcode.size == RL78_Byte)
                      PR (PS, "pmc");
                    else if (oper->addend == 0xfffff && do_sfr && opcode.size == RL78_Byte)
                      PR (PS, "mem");
		    else if (oper->addend >= 0xffe20)
		      PR (PS, "%#x", oper->addend);
		    else
		      {
			int faddr = oper->addend;
			if (do_es && ! oper->use_es)
			  faddr += 0xf0000;
			dis->print_address_func (faddr, dis);
		      }
		    break;

		  case RL78_Reg_B:
		  case RL78_Reg_C:
		  case RL78_Reg_BC:
		    PR (PS, "%d[%s]", oper->addend, register_names[oper->reg]);
		    break;

		  default:
		    PR (PS, "[%s", register_names[oper->reg]);
		    if (oper->reg2 != RL78_Reg_None)
		      PR (PS, "+%s", register_names[oper->reg2]);
		    if (oper->addend || do_addr)
		      PR (PS, "+%d", oper->addend);
		    PC (']');
		    break;

		  }
		if (oper->type == RL78_Operand_BitIndirect)
		  PR (PS, ".%d", oper->bit_number);
		break;

#if DEBUG_SEMANTICS
		/* Shouldn't happen - push and pop don't print
		   [SP] directly.  But we *do* use them for
		   semantic debugging.  */
	      case RL78_Operand_PostInc:
		PR (PS, "[%s++]", register_names[oper->reg]);
		break;
	      case RL78_Operand_PreDec:
		PR (PS, "[--%s]", register_names[oper->reg]);
		break;
#endif

	      default:
		/* If we ever print this, that means the
		   programmer tried to print an operand with a
		   type we don't expect.  Print the line and
		   operand number from rl78-decode.opc for
		   them.  */
		PR (PS, "???%d.%d", opcode.lineno, *s - '0');
		break;
	      }
	    }
	}
    }

#if DEBUG_SEMANTICS

  PR (PS, "\t\033[34m(line %d)\033[0m", opcode.lineno);

#endif

  return rv;
}

int
print_insn_rl78 (bfd_vma addr, disassemble_info * dis)
{
  return print_insn_rl78_common (addr, dis, RL78_ISA_DEFAULT);
}

int
print_insn_rl78_g10 (bfd_vma addr, disassemble_info * dis)
{
  return print_insn_rl78_common (addr, dis, RL78_ISA_G10);
}

int
print_insn_rl78_g13 (bfd_vma addr, disassemble_info * dis)
{
  return print_insn_rl78_common (addr, dis, RL78_ISA_G13);
}

int
print_insn_rl78_g14 (bfd_vma addr, disassemble_info * dis)
{
  return print_insn_rl78_common (addr, dis, RL78_ISA_G14);
}

disassembler_ftype
rl78_get_disassembler (bfd *abfd)
{
  int cpu = E_FLAG_RL78_ANY_CPU;

  if (abfd != NULL)
    cpu = abfd->tdata.elf_obj_data->elf_header->e_flags & E_FLAG_RL78_CPU_MASK;

  switch (cpu)
    {
    case E_FLAG_RL78_G10:
      return print_insn_rl78_g10;
    case E_FLAG_RL78_G13:
      return print_insn_rl78_g13;
    case E_FLAG_RL78_G14:
      return print_insn_rl78_g14;
    default:
      return print_insn_rl78;
    }
}