aboutsummaryrefslogtreecommitdiff
path: root/gas/config/tc-alpha.c
blob: ecc6a2f4b18f1670518db579cdbd2b7832d2b21d (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513
2514
2515
2516
2517
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534
2535
2536
2537
2538
2539
2540
2541
2542
2543
2544
2545
2546
2547
2548
2549
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577
2578
2579
2580
2581
2582
2583
2584
2585
2586
2587
2588
2589
2590
2591
2592
2593
2594
2595
2596
2597
2598
2599
2600
2601
2602
2603
2604
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641
2642
2643
2644
2645
2646
2647
2648
2649
2650
2651
2652
2653
2654
2655
2656
2657
2658
2659
2660
2661
2662
2663
2664
2665
2666
2667
2668
2669
2670
2671
2672
2673
2674
2675
2676
2677
2678
2679
2680
2681
2682
2683
2684
2685
2686
2687
2688
2689
2690
2691
2692
2693
2694
2695
2696
2697
2698
2699
2700
2701
2702
2703
2704
2705
2706
2707
2708
2709
2710
2711
2712
2713
2714
2715
2716
2717
2718
2719
2720
2721
2722
2723
2724
2725
2726
2727
2728
2729
2730
2731
2732
2733
2734
2735
2736
2737
2738
2739
2740
2741
2742
2743
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753
2754
2755
2756
2757
2758
2759
2760
2761
2762
2763
2764
2765
2766
2767
2768
2769
2770
2771
2772
2773
2774
2775
2776
2777
2778
2779
2780
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795
2796
2797
2798
2799
2800
2801
2802
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823
2824
2825
2826
2827
2828
2829
2830
2831
2832
2833
2834
2835
2836
2837
2838
2839
2840
2841
2842
2843
2844
2845
2846
2847
2848
2849
2850
2851
2852
2853
2854
2855
2856
2857
2858
2859
2860
2861
2862
2863
2864
2865
2866
2867
2868
2869
2870
2871
2872
2873
2874
2875
2876
2877
2878
2879
2880
2881
2882
2883
2884
2885
2886
2887
2888
2889
2890
2891
2892
2893
2894
2895
2896
2897
2898
2899
2900
2901
2902
2903
2904
2905
2906
2907
2908
2909
2910
2911
2912
2913
2914
2915
2916
2917
2918
2919
2920
2921
2922
2923
2924
2925
2926
2927
2928
2929
2930
2931
2932
2933
2934
2935
2936
2937
2938
2939
2940
2941
2942
2943
2944
2945
2946
2947
2948
2949
2950
2951
2952
2953
2954
2955
2956
2957
2958
2959
2960
2961
2962
2963
2964
2965
2966
2967
2968
2969
2970
2971
2972
2973
2974
2975
2976
2977
2978
2979
2980
2981
2982
2983
2984
2985
2986
2987
2988
2989
2990
2991
2992
2993
2994
2995
2996
2997
2998
2999
3000
3001
3002
3003
3004
3005
3006
3007
3008
3009
3010
3011
3012
3013
3014
3015
3016
3017
3018
3019
3020
3021
3022
3023
3024
3025
3026
3027
3028
3029
3030
3031
3032
3033
3034
3035
3036
3037
3038
3039
3040
3041
3042
3043
3044
3045
3046
3047
3048
3049
3050
3051
3052
3053
3054
3055
3056
3057
3058
3059
3060
3061
3062
3063
3064
3065
3066
3067
3068
3069
3070
3071
3072
3073
3074
3075
3076
3077
3078
3079
3080
3081
3082
3083
3084
3085
3086
3087
3088
3089
3090
3091
3092
3093
3094
3095
3096
3097
3098
3099
3100
3101
3102
3103
3104
3105
3106
3107
3108
3109
3110
3111
3112
3113
3114
3115
3116
3117
3118
3119
3120
3121
3122
3123
3124
3125
3126
3127
3128
3129
3130
3131
3132
3133
3134
3135
3136
3137
3138
3139
3140
3141
3142
3143
3144
3145
3146
3147
3148
3149
3150
3151
3152
3153
3154
3155
3156
3157
3158
3159
3160
3161
3162
3163
3164
3165
3166
3167
3168
3169
3170
3171
3172
3173
3174
3175
3176
3177
3178
3179
3180
3181
3182
3183
3184
3185
3186
3187
3188
3189
3190
3191
3192
3193
3194
3195
3196
3197
3198
3199
3200
3201
3202
3203
3204
3205
3206
3207
3208
3209
3210
3211
3212
3213
3214
3215
3216
3217
3218
3219
3220
3221
3222
3223
3224
3225
3226
3227
3228
3229
3230
3231
3232
3233
3234
3235
3236
3237
3238
3239
3240
3241
3242
3243
3244
3245
3246
3247
3248
3249
3250
3251
3252
3253
3254
3255
3256
3257
3258
3259
3260
3261
3262
3263
3264
3265
3266
3267
3268
3269
3270
3271
3272
3273
3274
3275
3276
3277
3278
3279
3280
3281
3282
3283
3284
3285
3286
3287
3288
3289
3290
3291
3292
3293
3294
3295
3296
3297
3298
3299
3300
3301
3302
3303
3304
3305
3306
3307
3308
3309
3310
3311
3312
3313
3314
3315
3316
3317
3318
3319
3320
3321
3322
3323
3324
3325
3326
3327
3328
3329
3330
3331
3332
3333
3334
3335
3336
3337
3338
3339
3340
3341
3342
3343
3344
3345
3346
3347
3348
3349
3350
3351
3352
3353
3354
3355
3356
3357
3358
3359
3360
3361
3362
3363
3364
3365
3366
3367
3368
3369
3370
3371
3372
3373
3374
3375
3376
3377
3378
3379
3380
3381
3382
3383
3384
3385
3386
3387
3388
3389
3390
3391
3392
3393
3394
3395
3396
3397
3398
3399
3400
3401
3402
3403
3404
3405
3406
3407
3408
3409
3410
3411
3412
3413
3414
3415
3416
3417
3418
3419
3420
3421
3422
3423
3424
3425
3426
3427
3428
3429
3430
3431
3432
3433
3434
3435
3436
3437
3438
3439
3440
3441
3442
3443
3444
3445
3446
3447
3448
3449
3450
3451
3452
3453
3454
3455
3456
3457
3458
3459
3460
3461
3462
3463
3464
3465
3466
3467
3468
3469
3470
3471
3472
3473
3474
3475
3476
3477
3478
3479
3480
3481
3482
3483
3484
3485
3486
3487
3488
3489
3490
3491
3492
3493
3494
3495
3496
3497
3498
3499
3500
3501
3502
3503
3504
3505
3506
3507
3508
3509
3510
3511
3512
3513
3514
3515
3516
3517
3518
3519
3520
3521
3522
3523
3524
3525
3526
3527
3528
3529
3530
3531
3532
3533
3534
3535
3536
3537
3538
3539
3540
3541
3542
3543
3544
3545
3546
3547
3548
3549
3550
3551
3552
3553
3554
3555
3556
3557
3558
3559
3560
3561
3562
3563
3564
3565
3566
3567
3568
3569
3570
3571
3572
3573
3574
3575
3576
3577
3578
3579
3580
3581
3582
3583
3584
3585
3586
3587
3588
3589
3590
3591
3592
3593
3594
3595
3596
3597
3598
3599
3600
3601
3602
3603
3604
3605
3606
3607
3608
3609
3610
3611
3612
3613
3614
3615
3616
3617
3618
3619
3620
3621
3622
3623
3624
3625
3626
3627
3628
3629
3630
3631
3632
3633
3634
3635
3636
3637
3638
3639
3640
3641
3642
3643
3644
3645
3646
3647
3648
3649
3650
3651
3652
3653
3654
3655
3656
3657
3658
3659
3660
3661
3662
3663
3664
3665
3666
3667
3668
3669
3670
3671
3672
3673
3674
3675
3676
3677
3678
3679
3680
3681
3682
3683
3684
3685
3686
3687
3688
3689
3690
3691
3692
3693
3694
3695
3696
3697
3698
3699
3700
3701
3702
3703
3704
3705
3706
3707
3708
3709
3710
3711
3712
3713
3714
3715
3716
3717
3718
3719
3720
3721
3722
3723
3724
3725
3726
3727
3728
3729
3730
3731
3732
3733
3734
3735
3736
3737
3738
3739
3740
3741
3742
3743
3744
3745
3746
3747
3748
3749
3750
3751
3752
3753
3754
3755
3756
3757
3758
3759
3760
3761
3762
3763
3764
3765
3766
3767
3768
3769
3770
3771
3772
3773
3774
3775
3776
3777
3778
3779
3780
3781
3782
3783
3784
3785
3786
3787
3788
3789
3790
3791
3792
3793
3794
3795
3796
3797
3798
3799
3800
3801
3802
3803
3804
3805
3806
3807
3808
3809
3810
3811
3812
3813
3814
3815
3816
3817
3818
3819
3820
3821
3822
3823
3824
3825
3826
3827
3828
3829
3830
3831
3832
3833
3834
3835
3836
3837
3838
3839
3840
3841
3842
3843
3844
3845
3846
3847
3848
3849
3850
3851
3852
3853
3854
3855
3856
3857
3858
3859
3860
3861
3862
3863
3864
3865
3866
3867
3868
3869
3870
3871
3872
3873
3874
3875
3876
3877
3878
3879
3880
3881
3882
3883
3884
3885
3886
3887
3888
3889
3890
3891
3892
3893
3894
3895
3896
3897
3898
3899
3900
3901
3902
3903
3904
3905
3906
3907
3908
3909
3910
3911
3912
3913
3914
3915
3916
3917
3918
3919
3920
3921
3922
3923
3924
3925
3926
3927
3928
3929
3930
3931
3932
3933
3934
3935
3936
3937
3938
3939
3940
3941
3942
3943
3944
3945
3946
3947
3948
3949
3950
3951
3952
3953
3954
3955
3956
3957
3958
3959
3960
3961
3962
3963
3964
3965
3966
3967
3968
3969
3970
3971
3972
3973
3974
3975
3976
3977
3978
3979
3980
3981
3982
3983
3984
3985
3986
3987
3988
3989
3990
3991
3992
3993
3994
3995
3996
3997
3998
3999
4000
4001
4002
4003
4004
4005
4006
4007
4008
4009
4010
4011
4012
4013
4014
4015
4016
4017
4018
4019
4020
4021
4022
4023
4024
4025
4026
4027
4028
4029
4030
4031
4032
4033
4034
4035
4036
4037
4038
4039
4040
4041
4042
4043
4044
4045
4046
4047
4048
4049
4050
4051
4052
4053
4054
4055
4056
4057
4058
4059
4060
4061
4062
4063
4064
4065
4066
4067
4068
4069
4070
4071
4072
4073
4074
4075
4076
4077
4078
4079
4080
4081
4082
4083
4084
4085
4086
4087
4088
4089
4090
4091
4092
4093
4094
4095
4096
4097
4098
4099
4100
4101
4102
4103
4104
4105
4106
4107
4108
4109
4110
4111
4112
4113
4114
4115
4116
4117
4118
4119
4120
4121
4122
4123
4124
4125
4126
4127
4128
4129
4130
4131
4132
4133
4134
4135
4136
4137
4138
4139
4140
4141
4142
4143
4144
4145
4146
4147
4148
4149
4150
4151
4152
4153
4154
4155
4156
4157
4158
4159
4160
4161
4162
4163
4164
4165
4166
4167
4168
4169
4170
4171
4172
4173
4174
4175
4176
4177
4178
4179
4180
4181
4182
4183
4184
4185
4186
4187
4188
4189
4190
4191
4192
4193
4194
4195
4196
4197
4198
4199
4200
4201
4202
4203
4204
4205
4206
4207
4208
4209
4210
4211
4212
4213
4214
4215
4216
4217
4218
4219
4220
4221
4222
4223
4224
4225
4226
4227
4228
4229
4230
4231
4232
4233
4234
4235
4236
4237
4238
4239
4240
4241
4242
4243
4244
4245
4246
4247
4248
4249
4250
4251
4252
4253
4254
4255
4256
4257
4258
4259
4260
4261
4262
4263
4264
4265
4266
4267
4268
4269
4270
4271
4272
4273
4274
4275
4276
4277
4278
4279
4280
4281
4282
4283
4284
4285
4286
4287
4288
4289
4290
4291
4292
4293
4294
4295
4296
4297
4298
4299
4300
4301
4302
4303
4304
4305
4306
4307
4308
4309
4310
4311
4312
4313
4314
4315
4316
4317
4318
4319
4320
4321
4322
4323
4324
4325
4326
4327
4328
4329
4330
4331
4332
4333
4334
4335
4336
4337
4338
4339
4340
4341
4342
4343
4344
4345
4346
4347
4348
4349
4350
4351
4352
4353
4354
4355
4356
4357
4358
4359
4360
4361
4362
4363
4364
4365
4366
4367
4368
4369
4370
4371
4372
4373
4374
4375
4376
4377
4378
4379
4380
4381
4382
4383
4384
4385
4386
4387
4388
4389
4390
4391
4392
4393
4394
4395
4396
4397
4398
4399
4400
4401
4402
4403
4404
4405
4406
4407
4408
4409
4410
4411
4412
4413
4414
4415
4416
4417
4418
4419
4420
4421
4422
4423
4424
4425
4426
4427
4428
4429
4430
4431
4432
4433
4434
4435
4436
4437
4438
4439
4440
4441
4442
4443
4444
4445
4446
4447
4448
4449
4450
4451
4452
4453
4454
4455
4456
4457
4458
4459
4460
4461
4462
4463
4464
4465
4466
4467
4468
4469
4470
4471
4472
4473
4474
4475
4476
4477
4478
4479
4480
4481
4482
4483
4484
4485
4486
4487
4488
4489
4490
4491
4492
4493
4494
4495
4496
4497
4498
4499
4500
4501
4502
4503
4504
4505
4506
4507
4508
4509
4510
4511
4512
4513
4514
4515
4516
4517
4518
4519
4520
4521
4522
4523
4524
4525
4526
4527
4528
4529
4530
4531
4532
4533
4534
4535
4536
4537
4538
4539
4540
4541
4542
4543
4544
4545
4546
4547
4548
4549
4550
4551
4552
4553
4554
4555
4556
4557
4558
4559
4560
4561
4562
4563
4564
4565
4566
4567
4568
4569
4570
4571
4572
4573
4574
4575
4576
4577
4578
4579
4580
4581
4582
4583
4584
4585
4586
4587
4588
4589
4590
4591
4592
4593
4594
4595
4596
4597
4598
4599
4600
4601
4602
4603
4604
4605
4606
4607
4608
4609
4610
4611
4612
4613
4614
4615
4616
4617
4618
4619
4620
4621
4622
4623
4624
4625
4626
4627
4628
4629
4630
4631
4632
4633
4634
4635
4636
4637
4638
4639
4640
4641
4642
4643
4644
4645
4646
4647
4648
4649
4650
4651
4652
4653
4654
4655
4656
4657
4658
4659
4660
4661
4662
4663
4664
4665
4666
4667
4668
4669
4670
4671
4672
4673
4674
4675
4676
4677
4678
4679
4680
4681
4682
4683
4684
4685
4686
4687
4688
4689
4690
4691
4692
4693
4694
4695
4696
4697
4698
4699
4700
4701
4702
4703
4704
4705
4706
4707
4708
4709
4710
4711
4712
4713
4714
4715
4716
4717
4718
4719
4720
4721
4722
4723
4724
4725
4726
4727
4728
4729
4730
4731
4732
4733
4734
4735
4736
4737
4738
4739
4740
4741
4742
4743
4744
4745
4746
4747
4748
4749
4750
4751
4752
4753
4754
4755
4756
4757
4758
4759
4760
4761
4762
4763
4764
4765
4766
4767
4768
4769
4770
4771
4772
4773
4774
4775
4776
4777
4778
4779
4780
4781
4782
4783
4784
4785
4786
4787
4788
4789
4790
4791
4792
4793
4794
4795
4796
4797
4798
4799
4800
4801
4802
4803
4804
4805
4806
4807
4808
4809
4810
4811
4812
4813
4814
4815
4816
4817
4818
4819
4820
4821
4822
4823
4824
4825
4826
4827
4828
4829
4830
4831
4832
4833
4834
4835
4836
4837
4838
4839
4840
4841
4842
4843
4844
4845
4846
4847
4848
4849
4850
4851
4852
4853
4854
4855
4856
4857
4858
4859
4860
4861
4862
4863
4864
4865
4866
4867
4868
4869
4870
4871
4872
4873
4874
4875
4876
4877
4878
4879
4880
4881
4882
4883
4884
4885
4886
4887
4888
4889
4890
4891
4892
4893
4894
4895
4896
4897
4898
4899
4900
4901
4902
4903
4904
4905
4906
4907
4908
4909
4910
4911
4912
4913
4914
4915
4916
4917
4918
4919
4920
4921
4922
4923
4924
4925
4926
4927
4928
4929
4930
4931
4932
4933
4934
4935
4936
4937
4938
4939
4940
4941
4942
4943
4944
4945
4946
4947
4948
4949
4950
4951
4952
4953
4954
4955
4956
4957
4958
4959
4960
4961
4962
4963
4964
4965
4966
4967
4968
4969
4970
4971
4972
4973
4974
4975
4976
4977
4978
4979
4980
4981
4982
4983
4984
4985
4986
4987
4988
4989
4990
4991
4992
4993
4994
4995
4996
4997
4998
4999
5000
5001
5002
5003
5004
5005
5006
5007
5008
5009
5010
5011
5012
5013
5014
5015
5016
5017
5018
5019
5020
5021
5022
5023
5024
5025
5026
5027
5028
5029
5030
5031
5032
5033
5034
5035
5036
5037
5038
5039
5040
5041
5042
5043
5044
5045
5046
5047
5048
5049
5050
5051
5052
5053
5054
5055
5056
5057
5058
5059
5060
5061
5062
5063
5064
5065
5066
5067
5068
5069
5070
5071
5072
5073
5074
5075
5076
5077
5078
5079
5080
5081
5082
5083
5084
5085
5086
5087
5088
5089
5090
5091
5092
5093
5094
5095
5096
5097
5098
5099
5100
5101
5102
5103
5104
5105
5106
5107
5108
5109
5110
5111
5112
5113
5114
5115
5116
5117
5118
5119
5120
5121
5122
5123
5124
5125
5126
5127
5128
5129
5130
5131
5132
5133
5134
5135
5136
5137
5138
5139
5140
5141
5142
5143
5144
5145
5146
5147
5148
5149
5150
5151
5152
5153
5154
5155
5156
5157
5158
5159
5160
5161
5162
5163
5164
5165
5166
5167
5168
5169
5170
5171
5172
5173
5174
5175
5176
5177
5178
5179
5180
5181
5182
5183
5184
5185
5186
5187
5188
5189
5190
5191
5192
5193
5194
5195
5196
5197
5198
5199
5200
5201
5202
5203
5204
5205
5206
5207
5208
5209
5210
5211
5212
5213
5214
5215
5216
5217
5218
5219
5220
5221
5222
5223
5224
5225
5226
5227
5228
5229
5230
5231
5232
5233
5234
5235
5236
5237
5238
5239
5240
5241
5242
5243
5244
5245
5246
5247
5248
5249
5250
5251
5252
5253
5254
5255
5256
5257
5258
5259
5260
5261
5262
5263
5264
5265
5266
5267
5268
5269
5270
5271
5272
5273
5274
5275
5276
5277
5278
5279
5280
5281
5282
5283
5284
5285
5286
5287
5288
5289
5290
5291
5292
5293
5294
5295
5296
5297
5298
5299
5300
5301
5302
5303
5304
5305
5306
5307
5308
5309
5310
5311
5312
5313
5314
5315
5316
5317
5318
5319
5320
5321
5322
5323
5324
5325
5326
5327
5328
5329
5330
5331
5332
5333
5334
5335
5336
5337
5338
5339
5340
5341
5342
5343
5344
5345
5346
5347
5348
5349
5350
5351
5352
5353
5354
5355
5356
5357
5358
5359
5360
5361
5362
5363
5364
5365
5366
5367
5368
5369
5370
5371
5372
5373
5374
5375
5376
5377
5378
5379
5380
5381
5382
5383
5384
5385
5386
5387
5388
5389
5390
5391
5392
5393
5394
5395
5396
5397
5398
5399
5400
5401
5402
5403
5404
5405
5406
5407
5408
5409
5410
5411
5412
5413
5414
5415
5416
5417
5418
5419
5420
5421
5422
5423
5424
5425
5426
5427
5428
5429
5430
5431
5432
5433
5434
5435
5436
5437
5438
5439
5440
5441
5442
5443
5444
5445
5446
5447
5448
5449
5450
5451
5452
5453
5454
5455
5456
5457
5458
5459
5460
5461
5462
5463
5464
5465
5466
5467
5468
5469
5470
5471
5472
5473
5474
5475
5476
5477
5478
5479
5480
5481
5482
5483
5484
5485
5486
5487
5488
5489
5490
5491
5492
5493
5494
5495
5496
5497
5498
5499
5500
5501
5502
5503
5504
5505
5506
5507
5508
5509
5510
5511
5512
5513
5514
5515
5516
5517
5518
5519
5520
5521
5522
5523
5524
5525
5526
5527
5528
5529
5530
5531
5532
5533
5534
5535
5536
5537
5538
5539
5540
5541
5542
5543
5544
5545
5546
5547
5548
5549
5550
5551
5552
5553
5554
5555
5556
5557
5558
5559
5560
5561
5562
5563
5564
5565
5566
5567
5568
5569
5570
5571
5572
5573
5574
5575
5576
5577
5578
5579
5580
5581
5582
5583
5584
5585
5586
5587
5588
5589
5590
5591
5592
5593
5594
5595
5596
5597
5598
5599
5600
5601
5602
5603
5604
5605
5606
5607
5608
5609
5610
5611
5612
5613
5614
5615
5616
5617
5618
5619
5620
5621
5622
5623
5624
5625
5626
5627
5628
5629
5630
5631
5632
5633
5634
5635
5636
5637
5638
5639
5640
5641
5642
5643
5644
5645
5646
5647
5648
5649
5650
5651
5652
5653
5654
5655
5656
5657
5658
5659
5660
5661
5662
5663
5664
5665
5666
5667
5668
5669
5670
5671
5672
5673
5674
5675
5676
5677
5678
5679
5680
5681
5682
5683
5684
5685
5686
5687
5688
5689
5690
5691
5692
5693
5694
5695
5696
5697
5698
5699
5700
5701
5702
5703
5704
5705
5706
5707
5708
5709
5710
5711
5712
5713
5714
5715
5716
5717
5718
5719
5720
5721
5722
5723
5724
5725
5726
5727
5728
5729
5730
5731
5732
5733
5734
5735
5736
5737
5738
5739
5740
5741
5742
5743
5744
5745
5746
5747
5748
5749
5750
5751
5752
5753
5754
5755
5756
5757
5758
5759
5760
5761
5762
5763
5764
5765
5766
5767
5768
5769
5770
5771
5772
5773
5774
5775
5776
5777
5778
5779
5780
5781
5782
5783
5784
5785
5786
5787
5788
5789
5790
5791
5792
5793
5794
5795
5796
5797
5798
5799
5800
5801
5802
5803
5804
5805
5806
5807
5808
5809
5810
5811
5812
5813
5814
5815
5816
5817
5818
5819
5820
5821
5822
5823
5824
5825
5826
5827
5828
5829
5830
5831
5832
5833
5834
5835
5836
5837
5838
5839
5840
5841
5842
5843
5844
5845
5846
5847
5848
5849
5850
5851
5852
5853
5854
5855
5856
5857
5858
5859
5860
5861
5862
5863
5864
5865
5866
5867
5868
5869
5870
5871
5872
5873
5874
5875
5876
5877
5878
5879
5880
5881
5882
5883
5884
5885
5886
5887
5888
5889
5890
5891
5892
5893
5894
5895
5896
5897
5898
5899
5900
5901
5902
5903
5904
5905
5906
5907
5908
5909
5910
5911
5912
5913
5914
5915
5916
5917
5918
5919
5920
5921
5922
5923
5924
5925
5926
5927
5928
5929
5930
5931
5932
5933
5934
5935
5936
5937
5938
5939
5940
5941
5942
5943
5944
5945
5946
5947
5948
5949
5950
5951
5952
5953
5954
5955
5956
5957
5958
5959
5960
5961
5962
5963
5964
5965
5966
5967
5968
5969
5970
5971
5972
5973
5974
5975
5976
5977
5978
5979
5980
5981
5982
5983
5984
5985
5986
5987
5988
5989
5990
5991
5992
5993
5994
5995
5996
5997
5998
5999
6000
6001
6002
6003
6004
6005
6006
6007
6008
6009
6010
6011
6012
6013
6014
6015
6016
6017
6018
6019
6020
6021
6022
6023
6024
6025
6026
6027
6028
6029
6030
6031
6032
6033
6034
6035
6036
6037
6038
6039
6040
6041
6042
6043
6044
6045
6046
6047
6048
6049
6050
6051
6052
6053
6054
6055
6056
6057
6058
6059
6060
6061
6062
6063
6064
6065
6066
6067
6068
6069
6070
6071
6072
6073
6074
6075
6076
6077
6078
6079
6080
6081
6082
6083
6084
6085
6086
6087
6088
6089
6090
6091
6092
6093
6094
6095
6096
6097
6098
6099
6100
6101
6102
6103
6104
6105
6106
6107
6108
6109
6110
6111
6112
6113
6114
6115
6116
6117
6118
6119
6120
6121
6122
6123
6124
6125
6126
6127
6128
6129
6130
6131
6132
6133
6134
6135
6136
6137
6138
6139
6140
6141
6142
6143
6144
6145
6146
6147
6148
6149
6150
6151
6152
6153
6154
6155
6156
6157
6158
6159
6160
6161
6162
6163
6164
6165
6166
6167
6168
6169
6170
6171
6172
6173
6174
6175
6176
6177
6178
6179
6180
6181
6182
6183
6184
6185
6186
6187
6188
6189
6190
6191
6192
6193
6194
6195
6196
6197
6198
6199
6200
6201
6202
6203
6204
6205
6206
6207
6208
6209
6210
6211
6212
6213
6214
6215
6216
6217
6218
6219
6220
6221
6222
6223
6224
6225
6226
6227
6228
6229
6230
6231
6232
6233
6234
6235
6236
6237
6238
6239
6240
6241
6242
6243
6244
6245
6246
6247
6248
6249
6250
6251
6252
6253
6254
6255
6256
6257
6258
6259
6260
6261
6262
6263
6264
6265
6266
6267
6268
6269
6270
6271
6272
6273
6274
6275
6276
6277
6278
6279
6280
6281
6282
6283
6284
6285
6286
6287
6288
6289
6290
6291
6292
6293
6294
6295
6296
6297
6298
6299
6300
6301
6302
6303
6304
6305
6306
6307
6308
6309
6310
6311
6312
6313
6314
6315
6316
6317
6318
6319
6320
6321
6322
6323
6324
6325
6326
6327
6328
6329
6330
6331
6332
6333
6334
6335
6336
6337
6338
6339
6340
6341
6342
6343
6344
6345
6346
6347
6348
6349
6350
6351
6352
6353
6354
6355
6356
6357
6358
6359
6360
6361
6362
6363
6364
6365
6366
6367
/* tc-alpha.c - Processor-specific code for the DEC Alpha AXP CPU.
   Copyright (C) 1989-2022 Free Software Foundation, Inc.
   Contributed by Carnegie Mellon University, 1993.
   Written by Alessandro Forin, based on earlier gas-1.38 target CPU files.
   Modified by Ken Raeburn for gas-2.x and ECOFF support.
   Modified by Richard Henderson for ELF support.
   Modified by Klaus K"ampf for EVAX (OpenVMS/Alpha) support.

   This file is part of GAS, the GNU Assembler.

   GAS is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3, or (at your option)
   any later version.

   GAS is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with GAS; see the file COPYING.  If not, write to the Free
   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
   02110-1301, USA.  */

/* Mach Operating System
   Copyright (c) 1993 Carnegie Mellon University
   All Rights Reserved.

   Permission to use, copy, modify and distribute this software and its
   documentation is hereby granted, provided that both the copyright
   notice and this permission notice appear in all copies of the
   software, derivative works or modified versions, and any portions
   thereof, and that both notices appear in supporting documentation.

   CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS
   CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
   ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.

   Carnegie Mellon requests users of this software to return to

    Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
    School of Computer Science
    Carnegie Mellon University
    Pittsburgh PA 15213-3890

   any improvements or extensions that they make and grant Carnegie the
   rights to redistribute these changes.  */

#include "as.h"
#include "subsegs.h"
#include "ecoff.h"

#include "opcode/alpha.h"

#ifdef OBJ_ELF
#include "elf/alpha.h"
#endif

#ifdef OBJ_EVAX
#include "vms.h"
#include "vms/egps.h"
#endif

#include "dwarf2dbg.h"
#include "dw2gencfi.h"
#include "safe-ctype.h"

/* Local types.  */

#define TOKENIZE_ERROR 		-1
#define TOKENIZE_ERROR_REPORT	-2
#define MAX_INSN_FIXUPS		 2
#define MAX_INSN_ARGS		 5

/* Used since new relocation types are introduced in this
   file (DUMMY_RELOC_LITUSE_*) */
typedef int extended_bfd_reloc_code_real_type;

struct alpha_fixup
{
  expressionS exp;
  /* bfd_reloc_code_real_type reloc; */
  extended_bfd_reloc_code_real_type reloc;
#ifdef OBJ_EVAX
  /* The symbol of the item in the linkage section.  */
  symbolS *xtrasym;

  /* The symbol of the procedure descriptor.  */
  symbolS *procsym;
#endif
};

struct alpha_insn
{
  unsigned insn;
  int nfixups;
  struct alpha_fixup fixups[MAX_INSN_FIXUPS];
  long sequence;
};

enum alpha_macro_arg
  {
    MACRO_EOA = 1,
    MACRO_IR,
    MACRO_PIR,
    MACRO_OPIR,
    MACRO_CPIR,
    MACRO_FPR,
    MACRO_EXP
  };

struct alpha_macro
{
  const char *name;
  void (*emit) (const expressionS *, int, const void *);
  const void * arg;
  enum alpha_macro_arg argsets[16];
};

/* Extra expression types.  */

#define O_pregister	O_md1	/* O_register, in parentheses.  */
#define O_cpregister	O_md2	/* + a leading comma.  */

/* The alpha_reloc_op table below depends on the ordering of these.  */
#define O_literal	O_md3		/* !literal relocation.  */
#define O_lituse_addr	O_md4		/* !lituse_addr relocation.  */
#define O_lituse_base	O_md5		/* !lituse_base relocation.  */
#define O_lituse_bytoff	O_md6		/* !lituse_bytoff relocation.  */
#define O_lituse_jsr	O_md7		/* !lituse_jsr relocation.  */
#define O_lituse_tlsgd	O_md8		/* !lituse_tlsgd relocation.  */
#define O_lituse_tlsldm	O_md9		/* !lituse_tlsldm relocation.  */
#define O_lituse_jsrdirect O_md10	/* !lituse_jsrdirect relocation.  */
#define O_gpdisp	O_md11		/* !gpdisp relocation.  */
#define O_gprelhigh	O_md12		/* !gprelhigh relocation.  */
#define O_gprellow	O_md13		/* !gprellow relocation.  */
#define O_gprel		O_md14		/* !gprel relocation.  */
#define O_samegp	O_md15		/* !samegp relocation.  */
#define O_tlsgd		O_md16		/* !tlsgd relocation.  */
#define O_tlsldm	O_md17		/* !tlsldm relocation.  */
#define O_gotdtprel	O_md18		/* !gotdtprel relocation.  */
#define O_dtprelhi	O_md19		/* !dtprelhi relocation.  */
#define O_dtprello	O_md20		/* !dtprello relocation.  */
#define O_dtprel	O_md21		/* !dtprel relocation.  */
#define O_gottprel	O_md22		/* !gottprel relocation.  */
#define O_tprelhi	O_md23		/* !tprelhi relocation.  */
#define O_tprello	O_md24		/* !tprello relocation.  */
#define O_tprel		O_md25		/* !tprel relocation.  */

#define DUMMY_RELOC_LITUSE_ADDR		(BFD_RELOC_UNUSED + 1)
#define DUMMY_RELOC_LITUSE_BASE		(BFD_RELOC_UNUSED + 2)
#define DUMMY_RELOC_LITUSE_BYTOFF	(BFD_RELOC_UNUSED + 3)
#define DUMMY_RELOC_LITUSE_JSR		(BFD_RELOC_UNUSED + 4)
#define DUMMY_RELOC_LITUSE_TLSGD	(BFD_RELOC_UNUSED + 5)
#define DUMMY_RELOC_LITUSE_TLSLDM	(BFD_RELOC_UNUSED + 6)
#define DUMMY_RELOC_LITUSE_JSRDIRECT	(BFD_RELOC_UNUSED + 7)

#define USER_RELOC_P(R) ((R) >= O_literal && (R) <= O_tprel)

/* Macros for extracting the type and number of encoded register tokens.  */

#define is_ir_num(x)		(((x) & 32) == 0)
#define is_fpr_num(x)		(((x) & 32) != 0)
#define regno(x)		((x) & 31)

/* Something odd inherited from the old assembler.  */

#define note_gpreg(R)		(alpha_gprmask |= (1 << (R)))
#define note_fpreg(R)		(alpha_fprmask |= (1 << (R)))

/* Predicates for 16- and 32-bit ranges */
/* XXX: The non-shift version appears to trigger a compiler bug when
   cross-assembling from x86 w/ gcc 2.7.2.  */

#if 1
#define range_signed_16(x) \
	(((offsetT) (x) >> 15) == 0 || ((offsetT) (x) >> 15) == -1)
#define range_signed_32(x) \
	(((offsetT) (x) >> 31) == 0 || ((offsetT) (x) >> 31) == -1)
#else
#define range_signed_16(x)	((offsetT) (x) >= -(offsetT) 0x8000 &&	\
				 (offsetT) (x) <=  (offsetT) 0x7FFF)
#define range_signed_32(x)	((offsetT) (x) >= -(offsetT) 0x80000000 && \
				 (offsetT) (x) <=  (offsetT) 0x7FFFFFFF)
#endif

/* Macros for sign extending from 16- and 32-bits.  */
/* XXX: The cast macros will work on all the systems that I care about,
   but really a predicate should be found to use the non-cast forms.  */

#if 1
#define sign_extend_16(x)	((short) (x))
#define sign_extend_32(x)	((int) (x))
#else
#define sign_extend_16(x)	((offsetT) (((x) & 0xFFFF) ^ 0x8000) - 0x8000)
#define sign_extend_32(x)	((offsetT) (((x) & 0xFFFFFFFF) \
					   ^ 0x80000000) - 0x80000000)
#endif

/* Macros to build tokens.  */

#define set_tok_reg(t, r)	(memset (&(t), 0, sizeof (t)),		\
				 (t).X_op = O_register,			\
				 (t).X_add_number = (r))
#define set_tok_preg(t, r)	(memset (&(t), 0, sizeof (t)),		\
				 (t).X_op = O_pregister,		\
				 (t).X_add_number = (r))
#define set_tok_cpreg(t, r)	(memset (&(t), 0, sizeof (t)),		\
				 (t).X_op = O_cpregister,		\
				 (t).X_add_number = (r))
#define set_tok_freg(t, r)	(memset (&(t), 0, sizeof (t)),		\
				 (t).X_op = O_register,			\
				 (t).X_add_number = (r) + 32)
#define set_tok_sym(t, s, a)	(memset (&(t), 0, sizeof (t)),		\
				 (t).X_op = O_symbol,			\
				 (t).X_add_symbol = (s),		\
				 (t).X_add_number = (a))
#define set_tok_const(t, n)	(memset (&(t), 0, sizeof (t)),		\
				 (t).X_op = O_constant,			\
				 (t).X_add_number = (n))

/* Generic assembler global variables which must be defined by all
   targets.  */

/* Characters which always start a comment.  */
const char comment_chars[] = "#";

/* Characters which start a comment at the beginning of a line.  */
const char line_comment_chars[] = "#";

/* Characters which may be used to separate multiple commands on a
   single line.  */
const char line_separator_chars[] = ";";

/* Characters which are used to indicate an exponent in a floating
   point number.  */
const char EXP_CHARS[] = "eE";

/* Characters which mean that a number is a floating point constant,
   as in 0d1.0.  */
/* XXX: Do all of these really get used on the alpha??  */
const char FLT_CHARS[] = "rRsSfFdDxXpP";

#ifdef OBJ_EVAX
const char *md_shortopts = "Fm:g+1h:HG:";
#else
const char *md_shortopts = "Fm:gG:";
#endif

struct option md_longopts[] =
  {
#define OPTION_32ADDR (OPTION_MD_BASE)
    { "32addr", no_argument, NULL, OPTION_32ADDR },
#define OPTION_RELAX (OPTION_32ADDR + 1)
    { "relax", no_argument, NULL, OPTION_RELAX },
#ifdef OBJ_ELF
#define OPTION_MDEBUG (OPTION_RELAX + 1)
#define OPTION_NO_MDEBUG (OPTION_MDEBUG + 1)
    { "mdebug", no_argument, NULL, OPTION_MDEBUG },
    { "no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG },
#endif
#ifdef OBJ_EVAX
#define OPTION_REPLACE (OPTION_RELAX + 1)
#define OPTION_NOREPLACE (OPTION_REPLACE+1)
    { "replace", no_argument, NULL, OPTION_REPLACE },
    { "noreplace", no_argument, NULL, OPTION_NOREPLACE },
#endif
    { NULL, no_argument, NULL, 0 }
  };

size_t md_longopts_size = sizeof (md_longopts);

#ifdef OBJ_EVAX
#define AXP_REG_R0     0
#define AXP_REG_R16    16
#define AXP_REG_R17    17
#undef AXP_REG_T9
#define AXP_REG_T9     22
#undef AXP_REG_T10
#define AXP_REG_T10    23
#undef AXP_REG_T11
#define AXP_REG_T11    24
#undef AXP_REG_T12
#define AXP_REG_T12    25
#define AXP_REG_AI     25
#undef AXP_REG_FP
#define AXP_REG_FP     29

#undef AXP_REG_GP
#define AXP_REG_GP AXP_REG_PV

#endif /* OBJ_EVAX  */

/* The cpu for which we are generating code.  */
static unsigned alpha_target = AXP_OPCODE_BASE;
static const char *alpha_target_name = "<all>";

/* The hash table of instruction opcodes.  */
static htab_t alpha_opcode_hash;

/* The hash table of macro opcodes.  */
static htab_t alpha_macro_hash;

#ifdef OBJ_ECOFF
/* The $gp relocation symbol.  */
static symbolS *alpha_gp_symbol;

/* XXX: what is this, and why is it exported? */
valueT alpha_gp_value;
#endif

/* The current $gp register.  */
static int alpha_gp_register = AXP_REG_GP;

/* A table of the register symbols.  */
static symbolS *alpha_register_table[64];

/* Constant sections, or sections of constants.  */
#ifdef OBJ_ECOFF
static segT alpha_lita_section;
#endif
#ifdef OBJ_EVAX
segT alpha_link_section;
#endif
#ifndef OBJ_EVAX
static segT alpha_lit8_section;
#endif

/* Symbols referring to said sections.  */
#ifdef OBJ_ECOFF
static symbolS *alpha_lita_symbol;
#endif
#ifdef OBJ_EVAX
static symbolS *alpha_link_symbol;
#endif
#ifndef OBJ_EVAX
static symbolS *alpha_lit8_symbol;
#endif

/* Literal for .litX+0x8000 within .lita.  */
#ifdef OBJ_ECOFF
static offsetT alpha_lit8_literal;
#endif

/* Is the assembler not allowed to use $at?  */
static int alpha_noat_on = 0;

/* Are macros enabled?  */
static int alpha_macros_on = 1;

/* Are floats disabled?  */
static int alpha_nofloats_on = 0;

/* Are addresses 32 bit?  */
static int alpha_addr32_on = 0;

/* Symbol labelling the current insn.  When the Alpha gas sees
     foo:
       .quad 0
   and the section happens to not be on an eight byte boundary, it
   will align both the symbol and the .quad to an eight byte boundary.  */
static symbolS *alpha_insn_label;
#if defined(OBJ_ELF) || defined (OBJ_EVAX)
static symbolS *alpha_prologue_label;
#endif

#ifdef OBJ_EVAX
/* Symbol associate with the current jsr instruction.  */
static symbolS *alpha_linkage_symbol;
#endif

/* Whether we should automatically align data generation pseudo-ops.
   .align 0 will turn this off.  */
static int alpha_auto_align_on = 1;

/* The known current alignment of the current section.  */
static int alpha_current_align;

/* These are exported to ECOFF code.  */
unsigned long alpha_gprmask, alpha_fprmask;

/* Whether the debugging option was seen.  */
static int alpha_debug;

#ifdef OBJ_ELF
/* Whether we are emitting an mdebug section.  */
int alpha_flag_mdebug = -1;
#endif

#ifdef OBJ_EVAX
/* Whether to perform the VMS procedure call optimization.  */
int alpha_flag_replace = 1;
#endif

/* Don't fully resolve relocations, allowing code movement in the linker.  */
static int alpha_flag_relax;

/* What value to give to bfd_set_gp_size.  */
static int g_switch_value = 8;

#ifdef OBJ_EVAX
/* Collect information about current procedure here.  */
struct alpha_evax_procs
{
  symbolS *symbol;	/* Proc pdesc symbol.  */
  int pdsckind;
  int framereg;		/* Register for frame pointer.  */
  int framesize;	/* Size of frame.  */
  int rsa_offset;
  int ra_save;
  int fp_save;
  long imask;
  long fmask;
  int type;
  int prologue;
  symbolS *handler;
  int handler_data;
};

/* Linked list of .linkage fixups.  */
struct alpha_linkage_fixups *alpha_linkage_fixup_root;
static struct alpha_linkage_fixups *alpha_linkage_fixup_tail;

/* Current procedure descriptor.  */
static struct alpha_evax_procs *alpha_evax_proc;
static struct alpha_evax_procs alpha_evax_proc_data;

static int alpha_flag_hash_long_names = 0;		/* -+ */
static int alpha_flag_show_after_trunc = 0;		/* -H */

/* If the -+ switch is given, then a hash is appended to any name that is
   longer than 64 characters, else longer symbol names are truncated.  */

#endif

#ifdef RELOC_OP_P
/* A table to map the spelling of a relocation operand into an appropriate
   bfd_reloc_code_real_type type.  The table is assumed to be ordered such
   that op-O_literal indexes into it.  */

#define ALPHA_RELOC_TABLE(op)						\
(&alpha_reloc_op[ ((!USER_RELOC_P (op))					\
		  ? (abort (), 0)					\
		  : (int) (op) - (int) O_literal) ])

#define DEF(NAME, RELOC, REQ, ALLOW) \
 { #NAME, sizeof(#NAME)-1, O_##NAME, RELOC, REQ, ALLOW}

static const struct alpha_reloc_op_tag
{
  const char *name;				/* String to lookup.  */
  size_t length;				/* Size of the string.  */
  operatorT op;					/* Which operator to use.  */
  extended_bfd_reloc_code_real_type reloc;
  unsigned int require_seq : 1;			/* Require a sequence number.  */
  unsigned int allow_seq : 1;			/* Allow a sequence number.  */
}
alpha_reloc_op[] =
{
  DEF (literal, BFD_RELOC_ALPHA_ELF_LITERAL, 0, 1),
  DEF (lituse_addr, DUMMY_RELOC_LITUSE_ADDR, 1, 1),
  DEF (lituse_base, DUMMY_RELOC_LITUSE_BASE, 1, 1),
  DEF (lituse_bytoff, DUMMY_RELOC_LITUSE_BYTOFF, 1, 1),
  DEF (lituse_jsr, DUMMY_RELOC_LITUSE_JSR, 1, 1),
  DEF (lituse_tlsgd, DUMMY_RELOC_LITUSE_TLSGD, 1, 1),
  DEF (lituse_tlsldm, DUMMY_RELOC_LITUSE_TLSLDM, 1, 1),
  DEF (lituse_jsrdirect, DUMMY_RELOC_LITUSE_JSRDIRECT, 1, 1),
  DEF (gpdisp, BFD_RELOC_ALPHA_GPDISP, 1, 1),
  DEF (gprelhigh, BFD_RELOC_ALPHA_GPREL_HI16, 0, 0),
  DEF (gprellow, BFD_RELOC_ALPHA_GPREL_LO16, 0, 0),
  DEF (gprel, BFD_RELOC_GPREL16, 0, 0),
  DEF (samegp, BFD_RELOC_ALPHA_BRSGP, 0, 0),
  DEF (tlsgd, BFD_RELOC_ALPHA_TLSGD, 0, 1),
  DEF (tlsldm, BFD_RELOC_ALPHA_TLSLDM, 0, 1),
  DEF (gotdtprel, BFD_RELOC_ALPHA_GOTDTPREL16, 0, 0),
  DEF (dtprelhi, BFD_RELOC_ALPHA_DTPREL_HI16, 0, 0),
  DEF (dtprello, BFD_RELOC_ALPHA_DTPREL_LO16, 0, 0),
  DEF (dtprel, BFD_RELOC_ALPHA_DTPREL16, 0, 0),
  DEF (gottprel, BFD_RELOC_ALPHA_GOTTPREL16, 0, 0),
  DEF (tprelhi, BFD_RELOC_ALPHA_TPREL_HI16, 0, 0),
  DEF (tprello, BFD_RELOC_ALPHA_TPREL_LO16, 0, 0),
  DEF (tprel, BFD_RELOC_ALPHA_TPREL16, 0, 0),
};

#undef DEF

static const int alpha_num_reloc_op
  = sizeof (alpha_reloc_op) / sizeof (*alpha_reloc_op);
#endif /* RELOC_OP_P */

/* Maximum # digits needed to hold the largest sequence #.  */
#define ALPHA_RELOC_DIGITS 25

/* Structure to hold explicit sequence information.  */
struct alpha_reloc_tag
{
  fixS *master;			/* The literal reloc.  */
#ifdef OBJ_EVAX
  struct symbol *sym;		/* Linkage section item symbol.  */
  struct symbol *psym;		/* Pdesc symbol.  */
#endif
  fixS *slaves;			/* Head of linked list of lituses.  */
  segT segment;			/* Segment relocs are in or undefined_section.  */
  long sequence;		/* Sequence #.  */
  unsigned n_master;		/* # of literals.  */
  unsigned n_slaves;		/* # of lituses.  */
  unsigned saw_tlsgd : 1;	/* True if ...  */
  unsigned saw_tlsldm : 1;
  unsigned saw_lu_tlsgd : 1;
  unsigned saw_lu_tlsldm : 1;
  unsigned multi_section_p : 1;	/* True if more than one section was used.  */
  char string[1];		/* Printable form of sequence to hash with.  */
};

/* Hash table to link up literals with the appropriate lituse.  */
static htab_t alpha_literal_hash;

/* Sequence numbers for internal use by macros.  */
static long next_sequence_num = -1;

/* A table of CPU names and opcode sets.  */

static const struct cpu_type
{
  const char *name;
  unsigned flags;
}
cpu_types[] =
{
  /* Ad hoc convention: cpu number gets palcode, process code doesn't.
     This supports usage under DU 4.0b that does ".arch ev4", and
     usage in MILO that does -m21064.  Probably something more
     specific like -m21064-pal should be used, but oh well.  */

  { "21064", AXP_OPCODE_BASE|AXP_OPCODE_EV4 },
  { "21064a", AXP_OPCODE_BASE|AXP_OPCODE_EV4 },
  { "21066", AXP_OPCODE_BASE|AXP_OPCODE_EV4 },
  { "21068", AXP_OPCODE_BASE|AXP_OPCODE_EV4 },
  { "21164", AXP_OPCODE_BASE|AXP_OPCODE_EV5 },
  { "21164a", AXP_OPCODE_BASE|AXP_OPCODE_EV5|AXP_OPCODE_BWX },
  { "21164pc", (AXP_OPCODE_BASE|AXP_OPCODE_EV5|AXP_OPCODE_BWX
		|AXP_OPCODE_MAX) },
  { "21264", (AXP_OPCODE_BASE|AXP_OPCODE_EV6|AXP_OPCODE_BWX
	      |AXP_OPCODE_MAX|AXP_OPCODE_CIX) },
  { "21264a", (AXP_OPCODE_BASE|AXP_OPCODE_EV6|AXP_OPCODE_BWX
	      |AXP_OPCODE_MAX|AXP_OPCODE_CIX) },
  { "21264b", (AXP_OPCODE_BASE|AXP_OPCODE_EV6|AXP_OPCODE_BWX
	      |AXP_OPCODE_MAX|AXP_OPCODE_CIX) },

  { "ev4", AXP_OPCODE_BASE },
  { "ev45", AXP_OPCODE_BASE },
  { "lca45", AXP_OPCODE_BASE },
  { "ev5", AXP_OPCODE_BASE },
  { "ev56", AXP_OPCODE_BASE|AXP_OPCODE_BWX },
  { "pca56", AXP_OPCODE_BASE|AXP_OPCODE_BWX|AXP_OPCODE_MAX },
  { "ev6", AXP_OPCODE_BASE|AXP_OPCODE_BWX|AXP_OPCODE_MAX|AXP_OPCODE_CIX },
  { "ev67", AXP_OPCODE_BASE|AXP_OPCODE_BWX|AXP_OPCODE_MAX|AXP_OPCODE_CIX },
  { "ev68", AXP_OPCODE_BASE|AXP_OPCODE_BWX|AXP_OPCODE_MAX|AXP_OPCODE_CIX },

  { "all", AXP_OPCODE_BASE },
  { 0, 0 }
};

/* Some instruction sets indexed by lg(size).  */
static const char * const sextX_op[] = { "sextb", "sextw", "sextl", NULL };
static const char * const insXl_op[] = { "insbl", "inswl", "insll", "insql" };
static const char * const insXh_op[] = { NULL,    "inswh", "inslh", "insqh" };
static const char * const extXl_op[] = { "extbl", "extwl", "extll", "extql" };
static const char * const extXh_op[] = { NULL,    "extwh", "extlh", "extqh" };
static const char * const mskXl_op[] = { "mskbl", "mskwl", "mskll", "mskql" };
static const char * const mskXh_op[] = { NULL,    "mskwh", "msklh", "mskqh" };
static const char * const stX_op[] = { "stb", "stw", "stl", "stq" };
static const char * const ldXu_op[] = { "ldbu", "ldwu", NULL, NULL };

static void assemble_insn (const struct alpha_opcode *, const expressionS *, int, struct alpha_insn *, extended_bfd_reloc_code_real_type);
static void emit_insn (struct alpha_insn *);
static void assemble_tokens (const char *, const expressionS *, int, int);
#ifdef OBJ_EVAX
static const char *s_alpha_section_name (void);
static symbolS *add_to_link_pool (symbolS *, offsetT);
#endif

static struct alpha_reloc_tag *
get_alpha_reloc_tag (long sequence)
{
  char buffer[ALPHA_RELOC_DIGITS];
  struct alpha_reloc_tag *info;

  sprintf (buffer, "!%ld", sequence);

  info = (struct alpha_reloc_tag *) str_hash_find (alpha_literal_hash, buffer);
  if (! info)
    {
      size_t len = strlen (buffer);

      info = (struct alpha_reloc_tag *)
          xcalloc (sizeof (struct alpha_reloc_tag) + len, 1);

      info->segment = now_seg;
      info->sequence = sequence;
      strcpy (info->string, buffer);
      str_hash_insert (alpha_literal_hash, info->string, info, 0);
#ifdef OBJ_EVAX
      info->sym = 0;
      info->psym = 0;
#endif
    }

  return info;
}

#ifndef OBJ_EVAX

static void
alpha_adjust_relocs (bfd *abfd ATTRIBUTE_UNUSED,
		     asection *sec,
		     void * ptr ATTRIBUTE_UNUSED)
{
  segment_info_type *seginfo = seg_info (sec);
  fixS **prevP;
  fixS *fixp;
  fixS *next;
  fixS *slave;

  /* If seginfo is NULL, we did not create this section; don't do
     anything with it.  By using a pointer to a pointer, we can update
     the links in place.  */
  if (seginfo == NULL)
    return;

  /* If there are no relocations, skip the section.  */
  if (! seginfo->fix_root)
    return;

  /* First rebuild the fixup chain without the explicit lituse and
     gpdisp_lo16 relocs.  */
  prevP = &seginfo->fix_root;
  for (fixp = seginfo->fix_root; fixp; fixp = next)
    {
      next = fixp->fx_next;
      fixp->fx_next = (fixS *) 0;

      switch (fixp->fx_r_type)
	{
	case BFD_RELOC_ALPHA_LITUSE:
	  if (fixp->tc_fix_data.info->n_master == 0)
	    as_bad_where (fixp->fx_file, fixp->fx_line,
			  _("No !literal!%ld was found"),
			  fixp->tc_fix_data.info->sequence);
#ifdef RELOC_OP_P
	  if (fixp->fx_offset == LITUSE_ALPHA_TLSGD)
	    {
	      if (! fixp->tc_fix_data.info->saw_tlsgd)
		as_bad_where (fixp->fx_file, fixp->fx_line,
			      _("No !tlsgd!%ld was found"),
			      fixp->tc_fix_data.info->sequence);
	    }
	  else if (fixp->fx_offset == LITUSE_ALPHA_TLSLDM)
	    {
	      if (! fixp->tc_fix_data.info->saw_tlsldm)
		as_bad_where (fixp->fx_file, fixp->fx_line,
			      _("No !tlsldm!%ld was found"),
			      fixp->tc_fix_data.info->sequence);
	    }
#endif
	  break;

	case BFD_RELOC_ALPHA_GPDISP_LO16:
	  if (fixp->tc_fix_data.info->n_master == 0)
	    as_bad_where (fixp->fx_file, fixp->fx_line,
			  _("No ldah !gpdisp!%ld was found"),
			  fixp->tc_fix_data.info->sequence);
	  break;

	case BFD_RELOC_ALPHA_ELF_LITERAL:
	  if (fixp->tc_fix_data.info
	      && (fixp->tc_fix_data.info->saw_tlsgd
	          || fixp->tc_fix_data.info->saw_tlsldm))
	    break;
	  /* FALLTHRU */

	default:
	  *prevP = fixp;
	  prevP = &fixp->fx_next;
	  break;
	}
    }

  /* Go back and re-chain dependent relocations.  They are currently
     linked through the next_reloc field in reverse order, so as we
     go through the next_reloc chain, we effectively reverse the chain
     once again.

     Except if there is more than one !literal for a given sequence
     number.  In that case, the programmer and/or compiler is not sure
     how control flows from literal to lituse, and we can't be sure to
     get the relaxation correct.

     ??? Well, actually we could, if there are enough lituses such that
     we can make each literal have at least one of each lituse type
     present.  Not implemented.

     Also suppress the optimization if the !literals/!lituses are spread
     in different segments.  This can happen with "interesting" uses of
     inline assembly; examples are present in the Linux kernel semaphores.  */

  for (fixp = seginfo->fix_root; fixp; fixp = next)
    {
      next = fixp->fx_next;
      switch (fixp->fx_r_type)
	{
	case BFD_RELOC_ALPHA_TLSGD:
	case BFD_RELOC_ALPHA_TLSLDM:
	  if (!fixp->tc_fix_data.info)
	    break;
	  if (fixp->tc_fix_data.info->n_master == 0)
	    break;
	  else if (fixp->tc_fix_data.info->n_master > 1)
	    {
	      as_bad_where (fixp->fx_file, fixp->fx_line,
			    _("too many !literal!%ld for %s"),
			    fixp->tc_fix_data.info->sequence,
			    (fixp->fx_r_type == BFD_RELOC_ALPHA_TLSGD
			     ? "!tlsgd" : "!tlsldm"));
	      break;
	    }

	  fixp->tc_fix_data.info->master->fx_next = fixp->fx_next;
	  fixp->fx_next = fixp->tc_fix_data.info->master;
	  fixp = fixp->fx_next;
	  /* Fall through.  */

	case BFD_RELOC_ALPHA_ELF_LITERAL:
	  if (fixp->tc_fix_data.info
	      && fixp->tc_fix_data.info->n_master == 1
	      && ! fixp->tc_fix_data.info->multi_section_p)
	    {
	      for (slave = fixp->tc_fix_data.info->slaves;
		   slave != (fixS *) 0;
		   slave = slave->tc_fix_data.next_reloc)
		{
		  slave->fx_next = fixp->fx_next;
		  fixp->fx_next = slave;
		}
	    }
	  break;

	case BFD_RELOC_ALPHA_GPDISP_HI16:
	  if (fixp->tc_fix_data.info->n_slaves == 0)
	    as_bad_where (fixp->fx_file, fixp->fx_line,
			  _("No lda !gpdisp!%ld was found"),
			  fixp->tc_fix_data.info->sequence);
	  else
	    {
	      slave = fixp->tc_fix_data.info->slaves;
	      slave->fx_next = next;
	      fixp->fx_next = slave;
	    }
	  break;

	default:
	  break;
	}
    }
}

/* Before the relocations are written, reorder them, so that user
   supplied !lituse relocations follow the appropriate !literal
   relocations, and similarly for !gpdisp relocations.  */

void
alpha_before_fix (void)
{
  if (alpha_literal_hash)
    bfd_map_over_sections (stdoutput, alpha_adjust_relocs, NULL);
}

#endif

#ifdef DEBUG_ALPHA
static void
debug_exp (expressionS tok[], int ntok)
{
  int i;

  fprintf (stderr, "debug_exp: %d tokens", ntok);
  for (i = 0; i < ntok; i++)
    {
      expressionS *t = &tok[i];
      const char *name;

      switch (t->X_op)
	{
	default:			name = "unknown";		break;
	case O_illegal:			name = "O_illegal";		break;
	case O_absent:			name = "O_absent";		break;
	case O_constant:		name = "O_constant";		break;
	case O_symbol:			name = "O_symbol";		break;
	case O_symbol_rva:		name = "O_symbol_rva";		break;
	case O_register:		name = "O_register";		break;
	case O_big:			name = "O_big";			break;
	case O_uminus:			name = "O_uminus";		break;
	case O_bit_not:			name = "O_bit_not";		break;
	case O_logical_not:		name = "O_logical_not";		break;
	case O_multiply:		name = "O_multiply";		break;
	case O_divide:			name = "O_divide";		break;
	case O_modulus:			name = "O_modulus";		break;
	case O_left_shift:		name = "O_left_shift";		break;
	case O_right_shift:		name = "O_right_shift";		break;
	case O_bit_inclusive_or:	name = "O_bit_inclusive_or";	break;
	case O_bit_or_not:		name = "O_bit_or_not";		break;
	case O_bit_exclusive_or:	name = "O_bit_exclusive_or";	break;
	case O_bit_and:			name = "O_bit_and";		break;
	case O_add:			name = "O_add";			break;
	case O_subtract:		name = "O_subtract";		break;
	case O_eq:			name = "O_eq";			break;
	case O_ne:			name = "O_ne";			break;
	case O_lt:			name = "O_lt";			break;
	case O_le:			name = "O_le";			break;
	case O_ge:			name = "O_ge";			break;
	case O_gt:			name = "O_gt";			break;
	case O_logical_and:		name = "O_logical_and";		break;
	case O_logical_or:		name = "O_logical_or";		break;
	case O_index:			name = "O_index";		break;
	case O_pregister:		name = "O_pregister";		break;
	case O_cpregister:		name = "O_cpregister";		break;
	case O_literal:			name = "O_literal";		break;
	case O_lituse_addr:		name = "O_lituse_addr";		break;
	case O_lituse_base:		name = "O_lituse_base";		break;
	case O_lituse_bytoff:		name = "O_lituse_bytoff";	break;
	case O_lituse_jsr:		name = "O_lituse_jsr";		break;
	case O_lituse_tlsgd:		name = "O_lituse_tlsgd";	break;
	case O_lituse_tlsldm:		name = "O_lituse_tlsldm";	break;
	case O_lituse_jsrdirect:	name = "O_lituse_jsrdirect";	break;
	case O_gpdisp:			name = "O_gpdisp";		break;
	case O_gprelhigh:		name = "O_gprelhigh";		break;
	case O_gprellow:		name = "O_gprellow";		break;
	case O_gprel:			name = "O_gprel";		break;
	case O_samegp:			name = "O_samegp";		break;
	case O_tlsgd:			name = "O_tlsgd";		break;
	case O_tlsldm:			name = "O_tlsldm";		break;
	case O_gotdtprel:		name = "O_gotdtprel";		break;
	case O_dtprelhi:		name = "O_dtprelhi";		break;
	case O_dtprello:		name = "O_dtprello";		break;
	case O_dtprel:			name = "O_dtprel";		break;
	case O_gottprel:		name = "O_gottprel";		break;
	case O_tprelhi:			name = "O_tprelhi";		break;
	case O_tprello:			name = "O_tprello";		break;
	case O_tprel:			name = "O_tprel";		break;
	}

      fprintf (stderr, ", %s(%s, %s, %d)", name,
	       (t->X_add_symbol) ? S_GET_NAME (t->X_add_symbol) : "--",
	       (t->X_op_symbol) ? S_GET_NAME (t->X_op_symbol) : "--",
	       (int) t->X_add_number);
    }
  fprintf (stderr, "\n");
  fflush (stderr);
}
#endif

/* Parse the arguments to an opcode.  */

static int
tokenize_arguments (char *str,
		    expressionS tok[],
		    int ntok)
{
  expressionS *end_tok = tok + ntok;
  char *old_input_line_pointer;
  int saw_comma = 0, saw_arg = 0;
#ifdef DEBUG_ALPHA
  expressionS *orig_tok = tok;
#endif
#ifdef RELOC_OP_P
  char *p;
  const struct alpha_reloc_op_tag *r;
  int c, i;
  size_t len;
  int reloc_found_p = 0;
#endif

  memset (tok, 0, sizeof (*tok) * ntok);

  /* Save and restore input_line_pointer around this function.  */
  old_input_line_pointer = input_line_pointer;
  input_line_pointer = str;

#ifdef RELOC_OP_P
  /* ??? Wrest control of ! away from the regular expression parser.  */
  is_end_of_line[(unsigned char) '!'] = 1;
#endif

  while (tok < end_tok && *input_line_pointer)
    {
      SKIP_WHITESPACE ();
      switch (*input_line_pointer)
	{
	case '\0':
	  goto fini;

#ifdef RELOC_OP_P
	case '!':
	  /* A relocation operand can be placed after the normal operand on an
	     assembly language statement, and has the following form:
		!relocation_type!sequence_number.  */
	  if (reloc_found_p)
	    {
	      /* Only support one relocation op per insn.  */
	      as_bad (_("More than one relocation op per insn"));
	      goto err_report;
	    }

	  if (!saw_arg)
	    goto err;

	  ++input_line_pointer;
	  SKIP_WHITESPACE ();
	  c = get_symbol_name (&p);

	  /* Parse !relocation_type.  */
	  len = input_line_pointer - p;
	  if (len == 0)
	    {
	      as_bad (_("No relocation operand"));
	      goto err_report;
	    }

	  r = &alpha_reloc_op[0];
	  for (i = alpha_num_reloc_op - 1; i >= 0; i--, r++)
	    if (len == r->length && memcmp (p, r->name, len) == 0)
	      break;
	  if (i < 0)
	    {
	      as_bad (_("Unknown relocation operand: !%s"), p);
	      goto err_report;
	    }

	  *input_line_pointer = c;
	  SKIP_WHITESPACE_AFTER_NAME ();
	  if (*input_line_pointer != '!')
	    {
	      if (r->require_seq)
		{
		  as_bad (_("no sequence number after !%s"), p);
		  goto err_report;
		}

	      tok->X_add_number = 0;
	    }
	  else
	    {
	      if (! r->allow_seq)
		{
		  as_bad (_("!%s does not use a sequence number"), p);
		  goto err_report;
		}

	      input_line_pointer++;

	      /* Parse !sequence_number.  */
	      expression (tok);
	      if (tok->X_op != O_constant || tok->X_add_number <= 0)
		{
		  as_bad (_("Bad sequence number: !%s!%s"),
			  r->name, input_line_pointer);
		  goto err_report;
		}
	    }

	  tok->X_op = r->op;
	  reloc_found_p = 1;
	  ++tok;
	  break;
#endif /* RELOC_OP_P */

	case ',':
	  ++input_line_pointer;
	  if (saw_comma || !saw_arg)
	    goto err;
	  saw_comma = 1;
	  break;

	case '(':
	  {
	    char *hold = input_line_pointer++;

	    /* First try for parenthesized register ...  */
	    expression (tok);
	    if (*input_line_pointer == ')' && tok->X_op == O_register)
	      {
		tok->X_op = (saw_comma ? O_cpregister : O_pregister);
		saw_comma = 0;
		saw_arg = 1;
		++input_line_pointer;
		++tok;
		break;
	      }

	    /* ... then fall through to plain expression.  */
	    input_line_pointer = hold;
	  }
	  /* Fall through.  */

	default:
	  if (saw_arg && !saw_comma)
	    goto err;

	  expression (tok);
	  if (tok->X_op == O_illegal || tok->X_op == O_absent)
	    goto err;

	  saw_comma = 0;
	  saw_arg = 1;
	  ++tok;
	  break;
	}
    }

 fini:
  if (saw_comma)
    goto err;
  input_line_pointer = old_input_line_pointer;

#ifdef DEBUG_ALPHA
  debug_exp (orig_tok, ntok - (end_tok - tok));
#endif
#ifdef RELOC_OP_P
  is_end_of_line[(unsigned char) '!'] = 0;
#endif

  return ntok - (end_tok - tok);

 err:
#ifdef RELOC_OP_P
  is_end_of_line[(unsigned char) '!'] = 0;
#endif
  input_line_pointer = old_input_line_pointer;
  return TOKENIZE_ERROR;

#ifdef RELOC_OP_P
 err_report:
  is_end_of_line[(unsigned char) '!'] = 0;
#endif
  input_line_pointer = old_input_line_pointer;
  return TOKENIZE_ERROR_REPORT;
}

/* Search forward through all variants of an opcode looking for a
   syntax match.  */

static const struct alpha_opcode *
find_opcode_match (const struct alpha_opcode *first_opcode,
		   const expressionS *tok,
		   int *pntok,
		   int *pcpumatch)
{
  const struct alpha_opcode *opcode = first_opcode;
  int ntok = *pntok;
  int got_cpu_match = 0;

  do
    {
      const unsigned char *opidx;
      int tokidx = 0;

      /* Don't match opcodes that don't exist on this architecture.  */
      if (!(opcode->flags & alpha_target))
	goto match_failed;

      got_cpu_match = 1;

      for (opidx = opcode->operands; *opidx; ++opidx)
	{
	  const struct alpha_operand *operand = &alpha_operands[*opidx];

	  /* Only take input from real operands.  */
	  if (operand->flags & AXP_OPERAND_FAKE)
	    continue;

	  /* When we expect input, make sure we have it.  */
	  if (tokidx >= ntok)
	    {
	      if ((operand->flags & AXP_OPERAND_OPTIONAL_MASK) == 0)
		goto match_failed;
	      continue;
	    }

	  /* Match operand type with expression type.  */
	  switch (operand->flags & AXP_OPERAND_TYPECHECK_MASK)
	    {
	    case AXP_OPERAND_IR:
	      if (tok[tokidx].X_op != O_register
		  || !is_ir_num (tok[tokidx].X_add_number))
		goto match_failed;
	      break;
	    case AXP_OPERAND_FPR:
	      if (tok[tokidx].X_op != O_register
		  || !is_fpr_num (tok[tokidx].X_add_number))
		goto match_failed;
	      break;
	    case AXP_OPERAND_IR | AXP_OPERAND_PARENS:
	      if (tok[tokidx].X_op != O_pregister
		  || !is_ir_num (tok[tokidx].X_add_number))
		goto match_failed;
	      break;
	    case AXP_OPERAND_IR | AXP_OPERAND_PARENS | AXP_OPERAND_COMMA:
	      if (tok[tokidx].X_op != O_cpregister
		  || !is_ir_num (tok[tokidx].X_add_number))
		goto match_failed;
	      break;

	    case AXP_OPERAND_RELATIVE:
	    case AXP_OPERAND_SIGNED:
	    case AXP_OPERAND_UNSIGNED:
	      switch (tok[tokidx].X_op)
		{
		case O_illegal:
		case O_absent:
		case O_register:
		case O_pregister:
		case O_cpregister:
		  goto match_failed;

		default:
		  break;
		}
	      break;

	    default:
	      /* Everything else should have been fake.  */
	      abort ();
	    }
	  ++tokidx;
	}

      /* Possible match -- did we use all of our input?  */
      if (tokidx == ntok)
	{
	  *pntok = ntok;
	  return opcode;
	}

    match_failed:;
    }
  while (++opcode - alpha_opcodes < (int) alpha_num_opcodes
	 && !strcmp (opcode->name, first_opcode->name));

  if (*pcpumatch)
    *pcpumatch = got_cpu_match;

  return NULL;
}

/* Given an opcode name and a pre-tokenized set of arguments, assemble
   the insn, but do not emit it.

   Note that this implies no macros allowed, since we can't store more
   than one insn in an insn structure.  */

static void
assemble_tokens_to_insn (const char *opname,
			 const expressionS *tok,
			 int ntok,
			 struct alpha_insn *insn)
{
  const struct alpha_opcode *opcode;

  /* Search opcodes.  */
  opcode = (const struct alpha_opcode *) str_hash_find (alpha_opcode_hash,
							opname);
  if (opcode)
    {
      int cpumatch;
      opcode = find_opcode_match (opcode, tok, &ntok, &cpumatch);
      if (opcode)
	{
	  assemble_insn (opcode, tok, ntok, insn, BFD_RELOC_UNUSED);
	  return;
	}
      else if (cpumatch)
	as_bad (_("inappropriate arguments for opcode `%s'"), opname);
      else
	as_bad (_("opcode `%s' not supported for target %s"), opname,
		alpha_target_name);
    }
  else
    as_bad (_("unknown opcode `%s'"), opname);
}

/* Build a BFD section with its flags set appropriately for the .lita,
   .lit8, or .lit4 sections.  */

static void
create_literal_section (const char *name,
			segT *secp,
			symbolS **symp)
{
  segT current_section = now_seg;
  int current_subsec = now_subseg;
  segT new_sec;

  *secp = new_sec = subseg_new (name, 0);
  subseg_set (current_section, current_subsec);
  bfd_set_section_alignment (new_sec, 4);
  bfd_set_section_flags (new_sec, (SEC_RELOC | SEC_ALLOC | SEC_LOAD
				   | SEC_READONLY | SEC_DATA));

  S_CLEAR_EXTERNAL (*symp = section_symbol (new_sec));
}

/* Load a (partial) expression into a target register.

   If poffset is not null, after the call it will either contain
   O_constant 0, or a 16-bit offset appropriate for any MEM format
   instruction.  In addition, pbasereg will be modified to point to
   the base register to use in that MEM format instruction.

   In any case, *pbasereg should contain a base register to add to the
   expression.  This will normally be either AXP_REG_ZERO or
   alpha_gp_register.  Symbol addresses will always be loaded via $gp,
   so "foo($0)" is interpreted as adding the address of foo to $0;
   i.e. "ldq $targ, LIT($gp); addq $targ, $0, $targ".  Odd, perhaps,
   but this is what OSF/1 does.

   If explicit relocations of the form !literal!<number> are allowed,
   and used, then explicit_reloc with be an expression pointer.

   Finally, the return value is nonzero if the calling macro may emit
   a LITUSE reloc if otherwise appropriate; the return value is the
   sequence number to use.  */

static long
load_expression (int targreg,
		 const expressionS *exp,
		 int *pbasereg,
		 expressionS *poffset,
		 const char *opname)
{
  long emit_lituse = 0;
  offsetT addend = exp->X_add_number;
  int basereg = *pbasereg;
  struct alpha_insn insn;
  expressionS newtok[3];

  switch (exp->X_op)
    {
    case O_symbol:
      {
#ifdef OBJ_ECOFF
	offsetT lit;

	/* Attempt to reduce .lit load by splitting the offset from
	   its symbol when possible, but don't create a situation in
	   which we'd fail.  */
	if (!range_signed_32 (addend) &&
	    (alpha_noat_on || targreg == AXP_REG_AT))
	  {
	    lit = add_to_literal_pool (exp->X_add_symbol, addend,
				       alpha_lita_section, 8);
	    addend = 0;
	  }
	else
	  lit = add_to_literal_pool (exp->X_add_symbol, 0,
				     alpha_lita_section, 8);

	if (lit >= 0x8000)
	  as_fatal (_("overflow in literal (.lita) table"));

	/* Emit "ldq r, lit(gp)".  */

	if (basereg != alpha_gp_register && targreg == basereg)
	  {
	    if (alpha_noat_on)
	      as_bad (_("macro requires $at register while noat in effect"));
	    if (targreg == AXP_REG_AT)
	      as_bad (_("macro requires $at while $at in use"));

	    set_tok_reg (newtok[0], AXP_REG_AT);
	  }
	else
	  set_tok_reg (newtok[0], targreg);

	set_tok_sym (newtok[1], alpha_lita_symbol, lit);
	set_tok_preg (newtok[2], alpha_gp_register);

	assemble_tokens_to_insn ("ldq", newtok, 3, &insn);

	gas_assert (insn.nfixups == 1);
	insn.fixups[0].reloc = BFD_RELOC_ALPHA_LITERAL;
	insn.sequence = emit_lituse = next_sequence_num--;
#endif /* OBJ_ECOFF */
#ifdef OBJ_ELF
	/* Emit "ldq r, gotoff(gp)".  */

	if (basereg != alpha_gp_register && targreg == basereg)
	  {
	    if (alpha_noat_on)
	      as_bad (_("macro requires $at register while noat in effect"));
	    if (targreg == AXP_REG_AT)
	      as_bad (_("macro requires $at while $at in use"));

	    set_tok_reg (newtok[0], AXP_REG_AT);
	  }
	else
	  set_tok_reg (newtok[0], targreg);

	/* XXX: Disable this .got minimizing optimization so that we can get
	   better instruction offset knowledge in the compiler.  This happens
	   very infrequently anyway.  */
	if (1
	    || (!range_signed_32 (addend)
		&& (alpha_noat_on || targreg == AXP_REG_AT)))
	  {
	    newtok[1] = *exp;
	    addend = 0;
	  }
	else
	  set_tok_sym (newtok[1], exp->X_add_symbol, 0);

	set_tok_preg (newtok[2], alpha_gp_register);

	assemble_tokens_to_insn ("ldq", newtok, 3, &insn);

	gas_assert (insn.nfixups == 1);
	insn.fixups[0].reloc = BFD_RELOC_ALPHA_ELF_LITERAL;
	insn.sequence = emit_lituse = next_sequence_num--;
#endif /* OBJ_ELF */
#ifdef OBJ_EVAX
	/* Find symbol or symbol pointer in link section.  */

	if (exp->X_add_symbol == alpha_evax_proc->symbol)
	  {
            /* Linkage-relative expression.  */
            set_tok_reg (newtok[0], targreg);

	    if (range_signed_16 (addend))
	      {
		set_tok_const (newtok[1], addend);
		addend = 0;
	      }
	    else
	      {
		set_tok_const (newtok[1], 0);
	      }
            set_tok_preg (newtok[2], basereg);
            assemble_tokens_to_insn ("lda", newtok, 3, &insn);
	  }
	else
	  {
	    const char *symname = S_GET_NAME (exp->X_add_symbol);
	    const char *ptr1, *ptr2;
	    int symlen = strlen (symname);

	    if ((symlen > 4 &&
		 strcmp (ptr2 = &symname [symlen - 4], "..lk") == 0))
	      {
                /* Access to an item whose address is stored in the linkage
                   section.  Just read the address.  */
		set_tok_reg (newtok[0], targreg);

		newtok[1] = *exp;
		newtok[1].X_op = O_subtract;
		newtok[1].X_op_symbol = alpha_evax_proc->symbol;

		set_tok_preg (newtok[2], basereg);
		assemble_tokens_to_insn ("ldq", newtok, 3, &insn);
		alpha_linkage_symbol = exp->X_add_symbol;

		if (poffset)
		  set_tok_const (*poffset, 0);

		if (alpha_flag_replace && targreg == 26)
		  {
                    /* Add a NOP fixup for 'ldX $26,YYY..NAME..lk'.  */
		    char *ensymname;
		    symbolS *ensym;

                    /* Build the entry name as 'NAME..en'.  */
		    ptr1 = strstr (symname, "..") + 2;
		    if (ptr1 > ptr2)
		      ptr1 = symname;
		    ensymname = XNEWVEC (char, ptr2 - ptr1 + 5);
		    memcpy (ensymname, ptr1, ptr2 - ptr1);
		    memcpy (ensymname + (ptr2 - ptr1), "..en", 5);

		    gas_assert (insn.nfixups + 1 <= MAX_INSN_FIXUPS);
		    insn.fixups[insn.nfixups].reloc = BFD_RELOC_ALPHA_NOP;
		    ensym = symbol_find_or_make (ensymname);
		    free (ensymname);
		    symbol_mark_used (ensym);
		    /* The fixup must be the same as the BFD_RELOC_ALPHA_BOH
		       case in emit_jsrjmp.  See B.4.5.2 of the OpenVMS Linker
		       Utility Manual.  */
		    insn.fixups[insn.nfixups].exp.X_op = O_symbol;
		    insn.fixups[insn.nfixups].exp.X_add_symbol = ensym;
		    insn.fixups[insn.nfixups].exp.X_add_number = 0;
		    insn.fixups[insn.nfixups].xtrasym = alpha_linkage_symbol;
		    insn.fixups[insn.nfixups].procsym = alpha_evax_proc->symbol;
		    insn.nfixups++;

		    /* ??? Force bsym to be instantiated now, as it will be
		       too late to do so in tc_gen_reloc.  */
		    symbol_get_bfdsym (exp->X_add_symbol);
		  }
		else if (alpha_flag_replace && targreg == 27)
		  {
                    /* Add a lda fixup for 'ldX $27,YYY.NAME..lk+8'.  */
		    char *psymname;
		    symbolS *psym;

                    /* Extract NAME.  */
		    ptr1 = strstr (symname, "..") + 2;
		    if (ptr1 > ptr2)
		      ptr1 = symname;
		    psymname = xmemdup0 (ptr1, ptr2 - ptr1);

		    gas_assert (insn.nfixups + 1 <= MAX_INSN_FIXUPS);
		    insn.fixups[insn.nfixups].reloc = BFD_RELOC_ALPHA_LDA;
		    psym = symbol_find_or_make (psymname);
		    free (psymname);
		    symbol_mark_used (psym);
		    insn.fixups[insn.nfixups].exp.X_op = O_subtract;
		    insn.fixups[insn.nfixups].exp.X_add_symbol = psym;
		    insn.fixups[insn.nfixups].exp.X_op_symbol = alpha_evax_proc->symbol;
		    insn.fixups[insn.nfixups].exp.X_add_number = 0;
		    insn.fixups[insn.nfixups].xtrasym = alpha_linkage_symbol;
		    insn.fixups[insn.nfixups].procsym = alpha_evax_proc->symbol;
		    insn.nfixups++;
		  }

		emit_insn (&insn);
		return 0;
	      }
	    else
	      {
                /* Not in the linkage section.  Put the value into the linkage
                   section.  */
		symbolS *linkexp;

		if (!range_signed_32 (addend))
		  addend = sign_extend_32 (addend);
		linkexp = add_to_link_pool (exp->X_add_symbol, 0);
		set_tok_reg (newtok[0], targreg);
		set_tok_sym (newtok[1], linkexp, 0);
		set_tok_preg (newtok[2], basereg);
		assemble_tokens_to_insn ("ldq", newtok, 3, &insn);
	      }
	  }
#endif /* OBJ_EVAX */

	emit_insn (&insn);

#ifndef OBJ_EVAX
	if (basereg != alpha_gp_register && basereg != AXP_REG_ZERO)
	  {
	    /* Emit "addq r, base, r".  */

	    set_tok_reg (newtok[1], basereg);
	    set_tok_reg (newtok[2], targreg);
	    assemble_tokens ("addq", newtok, 3, 0);
	  }
#endif
	basereg = targreg;
      }
      break;

    case O_constant:
      break;

    case O_subtract:
      /* Assume that this difference expression will be resolved to an
	 absolute value and that that value will fit in 16 bits.  */

      set_tok_reg (newtok[0], targreg);
      newtok[1] = *exp;
      set_tok_preg (newtok[2], basereg);
      assemble_tokens (opname, newtok, 3, 0);

      if (poffset)
	set_tok_const (*poffset, 0);
      return 0;

    case O_big:
      if (exp->X_add_number > 0)
	as_bad (_("bignum invalid; zero assumed"));
      else
	as_bad (_("floating point number invalid; zero assumed"));
      addend = 0;
      break;

    default:
      as_bad (_("can't handle expression"));
      addend = 0;
      break;
    }

  if (!range_signed_32 (addend))
    {
#ifdef OBJ_EVAX
      symbolS *litexp;
#else
      offsetT lit;
      long seq_num = next_sequence_num--;
#endif

      /* For 64-bit addends, just put it in the literal pool.  */
#ifdef OBJ_EVAX
      /* Emit "ldq targreg, lit(basereg)".  */
      litexp = add_to_link_pool (section_symbol (absolute_section), addend);
      set_tok_reg (newtok[0], targreg);
      set_tok_sym (newtok[1], litexp, 0);
      set_tok_preg (newtok[2], alpha_gp_register);
      assemble_tokens ("ldq", newtok, 3, 0);
#else

      if (alpha_lit8_section == NULL)
	{
	  create_literal_section (".lit8",
				  &alpha_lit8_section,
				  &alpha_lit8_symbol);

#ifdef OBJ_ECOFF
	  alpha_lit8_literal = add_to_literal_pool (alpha_lit8_symbol, 0x8000,
						    alpha_lita_section, 8);
	  if (alpha_lit8_literal >= 0x8000)
	    as_fatal (_("overflow in literal (.lita) table"));
#endif
	}

      lit = add_to_literal_pool (NULL, addend, alpha_lit8_section, 8) - 0x8000;
      if (lit >= 0x8000)
	as_fatal (_("overflow in literal (.lit8) table"));

      /* Emit "lda litreg, .lit8+0x8000".  */

      if (targreg == basereg)
	{
	  if (alpha_noat_on)
	    as_bad (_("macro requires $at register while noat in effect"));
	  if (targreg == AXP_REG_AT)
	    as_bad (_("macro requires $at while $at in use"));

	  set_tok_reg (newtok[0], AXP_REG_AT);
	}
      else
	set_tok_reg (newtok[0], targreg);
#ifdef OBJ_ECOFF
      set_tok_sym (newtok[1], alpha_lita_symbol, alpha_lit8_literal);
#endif
#ifdef OBJ_ELF
      set_tok_sym (newtok[1], alpha_lit8_symbol, 0x8000);
#endif
      set_tok_preg (newtok[2], alpha_gp_register);

      assemble_tokens_to_insn ("ldq", newtok, 3, &insn);

      gas_assert (insn.nfixups == 1);
#ifdef OBJ_ECOFF
      insn.fixups[0].reloc = BFD_RELOC_ALPHA_LITERAL;
#endif
#ifdef OBJ_ELF
      insn.fixups[0].reloc = BFD_RELOC_ALPHA_ELF_LITERAL;
#endif
      insn.sequence = seq_num;

      emit_insn (&insn);

      /* Emit "ldq litreg, lit(litreg)".  */

      set_tok_const (newtok[1], lit);
      set_tok_preg (newtok[2], newtok[0].X_add_number);

      assemble_tokens_to_insn ("ldq", newtok, 3, &insn);

      gas_assert (insn.nfixups < MAX_INSN_FIXUPS);
      insn.fixups[insn.nfixups].reloc = DUMMY_RELOC_LITUSE_BASE;
      insn.fixups[insn.nfixups].exp.X_op = O_absent;
      insn.nfixups++;
      insn.sequence = seq_num;
      emit_lituse = 0;

      emit_insn (&insn);

      /* Emit "addq litreg, base, target".  */

      if (basereg != AXP_REG_ZERO)
	{
	  set_tok_reg (newtok[1], basereg);
	  set_tok_reg (newtok[2], targreg);
	  assemble_tokens ("addq", newtok, 3, 0);
	}
#endif /* !OBJ_EVAX */

      if (poffset)
	set_tok_const (*poffset, 0);
      *pbasereg = targreg;
    }
  else
    {
      offsetT low, high, extra, tmp;

      /* For 32-bit operands, break up the addend.  */

      low = sign_extend_16 (addend);
      tmp = addend - low;
      high = sign_extend_16 (tmp >> 16);

      if (tmp - (high << 16))
	{
	  extra = 0x4000;
	  tmp -= 0x40000000;
	  high = sign_extend_16 (tmp >> 16);
	}
      else
	extra = 0;

      set_tok_reg (newtok[0], targreg);
      set_tok_preg (newtok[2], basereg);

      if (extra)
	{
	  /* Emit "ldah r, extra(r).  */
	  set_tok_const (newtok[1], extra);
	  assemble_tokens ("ldah", newtok, 3, 0);
	  set_tok_preg (newtok[2], basereg = targreg);
	}

      if (high)
	{
	  /* Emit "ldah r, high(r).  */
	  set_tok_const (newtok[1], high);
	  assemble_tokens ("ldah", newtok, 3, 0);
	  basereg = targreg;
	  set_tok_preg (newtok[2], basereg);
	}

      if ((low && !poffset) || (!poffset && basereg != targreg))
	{
	  /* Emit "lda r, low(base)".  */
	  set_tok_const (newtok[1], low);
	  assemble_tokens ("lda", newtok, 3, 0);
	  basereg = targreg;
	  low = 0;
	}

      if (poffset)
	set_tok_const (*poffset, low);
      *pbasereg = basereg;
    }

  return emit_lituse;
}

/* The lda macro differs from the lda instruction in that it handles
   most simple expressions, particularly symbol address loads and
   large constants.  */

static void
emit_lda (const expressionS *tok,
	  int ntok,
	  const void * unused ATTRIBUTE_UNUSED)
{
  int basereg;

  if (ntok == 2)
    basereg = (tok[1].X_op == O_constant ? AXP_REG_ZERO : alpha_gp_register);
  else
    basereg = tok[2].X_add_number;

  (void) load_expression (tok[0].X_add_number, &tok[1], &basereg, NULL, "lda");
}

/* The ldah macro differs from the ldah instruction in that it has $31
   as an implied base register.  */

static void
emit_ldah (const expressionS *tok,
	   int ntok ATTRIBUTE_UNUSED,
	   const void * unused ATTRIBUTE_UNUSED)
{
  expressionS newtok[3];

  newtok[0] = tok[0];
  newtok[1] = tok[1];
  set_tok_preg (newtok[2], AXP_REG_ZERO);

  assemble_tokens ("ldah", newtok, 3, 0);
}

/* Called internally to handle all alignment needs.  This takes care
   of eliding calls to frag_align if'n the cached current alignment
   says we've already got it, as well as taking care of the auto-align
   feature wrt labels.  */

static void
alpha_align (int n,
	     char *pfill,
	     symbolS *label,
	     int force ATTRIBUTE_UNUSED)
{
  if (alpha_current_align >= n)
    return;

  if (pfill == NULL)
    {
      if (subseg_text_p (now_seg))
	frag_align_code (n, 0);
      else
	frag_align (n, 0, 0);
    }
  else
    frag_align (n, *pfill, 0);

  alpha_current_align = n;

  if (label != NULL && S_GET_SEGMENT (label) == now_seg)
    {
      symbol_set_frag (label, frag_now);
      S_SET_VALUE (label, (valueT) frag_now_fix ());
    }

  record_alignment (now_seg, n);

  /* ??? If alpha_flag_relax && force && elf, record the requested alignment
     in a reloc for the linker to see.  */
}

/* Actually output an instruction with its fixup.  */

static void
emit_insn (struct alpha_insn *insn)
{
  char *f;
  int i;

  /* Take care of alignment duties.  */
  if (alpha_auto_align_on && alpha_current_align < 2)
    alpha_align (2, (char *) NULL, alpha_insn_label, 0);
  if (alpha_current_align > 2)
    alpha_current_align = 2;
  alpha_insn_label = NULL;

  /* Write out the instruction.  */
  f = frag_more (4);
  md_number_to_chars (f, insn->insn, 4);

#ifdef OBJ_ELF
  dwarf2_emit_insn (4);
#endif

  /* Apply the fixups in order.  */
  for (i = 0; i < insn->nfixups; ++i)
    {
      const struct alpha_operand *operand = (const struct alpha_operand *) 0;
      struct alpha_fixup *fixup = &insn->fixups[i];
      struct alpha_reloc_tag *info = NULL;
      int size, pcrel;
      fixS *fixP;

      /* Some fixups are only used internally and so have no howto.  */
      if ((int) fixup->reloc < 0)
	{
	  operand = &alpha_operands[-(int) fixup->reloc];
	  size = 4;
	  pcrel = ((operand->flags & AXP_OPERAND_RELATIVE) != 0);
	}
      else if (fixup->reloc > BFD_RELOC_UNUSED
	       || fixup->reloc == BFD_RELOC_ALPHA_GPDISP_HI16
	       || fixup->reloc == BFD_RELOC_ALPHA_GPDISP_LO16)
	{
	  size = 2;
	  pcrel = 0;
	}
      else
	{
	  reloc_howto_type *reloc_howto =
              bfd_reloc_type_lookup (stdoutput,
                                     (bfd_reloc_code_real_type) fixup->reloc);
	  gas_assert (reloc_howto);

	  size = bfd_get_reloc_size (reloc_howto);

	  switch (fixup->reloc)
	    {
#ifdef OBJ_EVAX
	    case BFD_RELOC_ALPHA_NOP:
	    case BFD_RELOC_ALPHA_BSR:
	    case BFD_RELOC_ALPHA_LDA:
	    case BFD_RELOC_ALPHA_BOH:
	      break;
#endif
	    default:
	      gas_assert (size >= 1 && size <= 4);
	    }

	  pcrel = reloc_howto->pc_relative;
	}

      fixP = fix_new_exp (frag_now, f - frag_now->fr_literal, size,
			  &fixup->exp, pcrel, (bfd_reloc_code_real_type) fixup->reloc);

      /* Turn off complaints that the addend is too large for some fixups,
         and copy in the sequence number for the explicit relocations.  */
      switch (fixup->reloc)
	{
	case BFD_RELOC_ALPHA_HINT:
	case BFD_RELOC_GPREL32:
	case BFD_RELOC_GPREL16:
	case BFD_RELOC_ALPHA_GPREL_HI16:
	case BFD_RELOC_ALPHA_GPREL_LO16:
	case BFD_RELOC_ALPHA_GOTDTPREL16:
	case BFD_RELOC_ALPHA_DTPREL_HI16:
	case BFD_RELOC_ALPHA_DTPREL_LO16:
	case BFD_RELOC_ALPHA_DTPREL16:
	case BFD_RELOC_ALPHA_GOTTPREL16:
	case BFD_RELOC_ALPHA_TPREL_HI16:
	case BFD_RELOC_ALPHA_TPREL_LO16:
	case BFD_RELOC_ALPHA_TPREL16:
	  fixP->fx_no_overflow = 1;
	  break;

	case BFD_RELOC_ALPHA_GPDISP_HI16:
	  fixP->fx_no_overflow = 1;
	  fixP->fx_addsy = section_symbol (now_seg);
	  fixP->fx_offset = 0;

	  info = get_alpha_reloc_tag (insn->sequence);
	  if (++info->n_master > 1)
	    as_bad (_("too many ldah insns for !gpdisp!%ld"), insn->sequence);
	  if (info->segment != now_seg)
	    as_bad (_("both insns for !gpdisp!%ld must be in the same section"),
		    insn->sequence);
	  fixP->tc_fix_data.info = info;
	  break;

	case BFD_RELOC_ALPHA_GPDISP_LO16:
	  fixP->fx_no_overflow = 1;

	  info = get_alpha_reloc_tag (insn->sequence);
	  if (++info->n_slaves > 1)
	    as_bad (_("too many lda insns for !gpdisp!%ld"), insn->sequence);
	  if (info->segment != now_seg)
	    as_bad (_("both insns for !gpdisp!%ld must be in the same section"),
		    insn->sequence);
	  fixP->tc_fix_data.info = info;
	  info->slaves = fixP;
	  break;

	case BFD_RELOC_ALPHA_LITERAL:
	case BFD_RELOC_ALPHA_ELF_LITERAL:
	  fixP->fx_no_overflow = 1;

	  if (insn->sequence == 0)
	    break;
	  info = get_alpha_reloc_tag (insn->sequence);
	  info->master = fixP;
	  info->n_master++;
	  if (info->segment != now_seg)
	    info->multi_section_p = 1;
	  fixP->tc_fix_data.info = info;
	  break;

#ifdef RELOC_OP_P
	case DUMMY_RELOC_LITUSE_ADDR:
	  fixP->fx_offset = LITUSE_ALPHA_ADDR;
	  goto do_lituse;
	case DUMMY_RELOC_LITUSE_BASE:
	  fixP->fx_offset = LITUSE_ALPHA_BASE;
	  goto do_lituse;
	case DUMMY_RELOC_LITUSE_BYTOFF:
	  fixP->fx_offset = LITUSE_ALPHA_BYTOFF;
	  goto do_lituse;
	case DUMMY_RELOC_LITUSE_JSR:
	  fixP->fx_offset = LITUSE_ALPHA_JSR;
	  goto do_lituse;
	case DUMMY_RELOC_LITUSE_TLSGD:
	  fixP->fx_offset = LITUSE_ALPHA_TLSGD;
	  goto do_lituse;
	case DUMMY_RELOC_LITUSE_TLSLDM:
	  fixP->fx_offset = LITUSE_ALPHA_TLSLDM;
	  goto do_lituse;
	case DUMMY_RELOC_LITUSE_JSRDIRECT:
	  fixP->fx_offset = LITUSE_ALPHA_JSRDIRECT;
	  goto do_lituse;
	do_lituse:
	  fixP->fx_addsy = section_symbol (now_seg);
	  fixP->fx_r_type = BFD_RELOC_ALPHA_LITUSE;

	  info = get_alpha_reloc_tag (insn->sequence);
	  if (fixup->reloc == DUMMY_RELOC_LITUSE_TLSGD)
	    info->saw_lu_tlsgd = 1;
	  else if (fixup->reloc == DUMMY_RELOC_LITUSE_TLSLDM)
	    info->saw_lu_tlsldm = 1;
	  if (++info->n_slaves > 1)
	    {
	      if (info->saw_lu_tlsgd)
		as_bad (_("too many lituse insns for !lituse_tlsgd!%ld"),
		        insn->sequence);
	      else if (info->saw_lu_tlsldm)
		as_bad (_("too many lituse insns for !lituse_tlsldm!%ld"),
		        insn->sequence);
	    }
	  fixP->tc_fix_data.info = info;
	  fixP->tc_fix_data.next_reloc = info->slaves;
	  info->slaves = fixP;
	  if (info->segment != now_seg)
	    info->multi_section_p = 1;
	  break;

	case BFD_RELOC_ALPHA_TLSGD:
	  fixP->fx_no_overflow = 1;

	  if (insn->sequence == 0)
	    break;
	  info = get_alpha_reloc_tag (insn->sequence);
	  if (info->saw_tlsgd)
	    as_bad (_("duplicate !tlsgd!%ld"), insn->sequence);
	  else if (info->saw_tlsldm)
	    as_bad (_("sequence number in use for !tlsldm!%ld"),
		    insn->sequence);
	  else
	    info->saw_tlsgd = 1;
	  fixP->tc_fix_data.info = info;
	  break;

	case BFD_RELOC_ALPHA_TLSLDM:
	  fixP->fx_no_overflow = 1;

	  if (insn->sequence == 0)
	    break;
	  info = get_alpha_reloc_tag (insn->sequence);
	  if (info->saw_tlsldm)
	    as_bad (_("duplicate !tlsldm!%ld"), insn->sequence);
	  else if (info->saw_tlsgd)
	    as_bad (_("sequence number in use for !tlsgd!%ld"),
		    insn->sequence);
	  else
	    info->saw_tlsldm = 1;
	  fixP->tc_fix_data.info = info;
	  break;
#endif
#ifdef OBJ_EVAX
	case BFD_RELOC_ALPHA_NOP:
	case BFD_RELOC_ALPHA_LDA:
	case BFD_RELOC_ALPHA_BSR:
	case BFD_RELOC_ALPHA_BOH:
	  info = get_alpha_reloc_tag (next_sequence_num--);
	  fixP->tc_fix_data.info = info;
	  fixP->tc_fix_data.info->sym = fixup->xtrasym;
	  fixP->tc_fix_data.info->psym = fixup->procsym;
	  break;
#endif

	default:
	  if ((int) fixup->reloc < 0)
	    {
	      if (operand->flags & AXP_OPERAND_NOOVERFLOW)
		fixP->fx_no_overflow = 1;
	    }
	  break;
	}
    }
}

/* Insert an operand value into an instruction.  */

static unsigned
insert_operand (unsigned insn,
		const struct alpha_operand *operand,
		offsetT val,
		const char *file,
		unsigned line)
{
  if (!(operand->flags & AXP_OPERAND_NOOVERFLOW))
    {
      offsetT min, max;

      if (operand->flags & AXP_OPERAND_SIGNED)
	{
	  max = (1 << (operand->bits - 1)) - 1;
	  min = -(1 << (operand->bits - 1));
	}
      else
	{
	  max = (1 << operand->bits) - 1;
	  min = 0;
	}

      if (val < min || val > max)
	as_bad_value_out_of_range (_("operand"), val, min, max, file, line);
    }

  if (operand->insert)
    {
      const char *errmsg = NULL;

      insn = (*operand->insert) (insn, val, &errmsg);
      if (errmsg)
	as_warn ("%s", errmsg);
    }
  else
    insn |= ((val & ((1 << operand->bits) - 1)) << operand->shift);

  return insn;
}

/* Turn an opcode description and a set of arguments into
   an instruction and a fixup.  */

static void
assemble_insn (const struct alpha_opcode *opcode,
	       const expressionS *tok,
	       int ntok,
	       struct alpha_insn *insn,
	       extended_bfd_reloc_code_real_type reloc)
{
  const struct alpha_operand *reloc_operand = NULL;
  const expressionS *reloc_exp = NULL;
  const unsigned char *argidx;
  unsigned image;
  int tokidx = 0;

  memset (insn, 0, sizeof (*insn));
  image = opcode->opcode;

  for (argidx = opcode->operands; *argidx; ++argidx)
    {
      const struct alpha_operand *operand = &alpha_operands[*argidx];
      const expressionS *t = (const expressionS *) 0;

      if (operand->flags & AXP_OPERAND_FAKE)
	{
	  /* Fake operands take no value and generate no fixup.  */
	  image = insert_operand (image, operand, 0, NULL, 0);
	  continue;
	}

      if (tokidx >= ntok)
	{
	  switch (operand->flags & AXP_OPERAND_OPTIONAL_MASK)
	    {
	    case AXP_OPERAND_DEFAULT_FIRST:
	      t = &tok[0];
	      break;
	    case AXP_OPERAND_DEFAULT_SECOND:
	      t = &tok[1];
	      break;
	    case AXP_OPERAND_DEFAULT_ZERO:
	      {
		static expressionS zero_exp;
		t = &zero_exp;
		zero_exp.X_op = O_constant;
		zero_exp.X_unsigned = 1;
	      }
	      break;
	    default:
	      abort ();
	    }
	}
      else
	t = &tok[tokidx++];

      switch (t->X_op)
	{
	case O_register:
	case O_pregister:
	case O_cpregister:
	  image = insert_operand (image, operand, regno (t->X_add_number),
				  NULL, 0);
	  break;

	case O_constant:
	  image = insert_operand (image, operand, t->X_add_number, NULL, 0);
	  gas_assert (reloc_operand == NULL);
	  reloc_operand = operand;
	  reloc_exp = t;
	  break;

	default:
	  /* This is only 0 for fields that should contain registers,
	     which means this pattern shouldn't have matched.  */
	  if (operand->default_reloc == 0)
	    abort ();

	  /* There is one special case for which an insn receives two
	     relocations, and thus the user-supplied reloc does not
	     override the operand reloc.  */
	  if (operand->default_reloc == BFD_RELOC_ALPHA_HINT)
	    {
	      struct alpha_fixup *fixup;

	      if (insn->nfixups >= MAX_INSN_FIXUPS)
		as_fatal (_("too many fixups"));

	      fixup = &insn->fixups[insn->nfixups++];
	      fixup->exp = *t;
	      fixup->reloc = BFD_RELOC_ALPHA_HINT;
	    }
	  else
	    {
	      if (reloc == BFD_RELOC_UNUSED)
		reloc = operand->default_reloc;

	      gas_assert (reloc_operand == NULL);
	      reloc_operand = operand;
	      reloc_exp = t;
	    }
	  break;
	}
    }

  if (reloc != BFD_RELOC_UNUSED)
    {
      struct alpha_fixup *fixup;

      if (insn->nfixups >= MAX_INSN_FIXUPS)
	as_fatal (_("too many fixups"));

      /* ??? My but this is hacky.  But the OSF/1 assembler uses the same
	 relocation tag for both ldah and lda with gpdisp.  Choose the
	 correct internal relocation based on the opcode.  */
      if (reloc == BFD_RELOC_ALPHA_GPDISP)
	{
	  if (strcmp (opcode->name, "ldah") == 0)
	    reloc = BFD_RELOC_ALPHA_GPDISP_HI16;
	  else if (strcmp (opcode->name, "lda") == 0)
	    reloc = BFD_RELOC_ALPHA_GPDISP_LO16;
	  else
	    as_bad (_("invalid relocation for instruction"));
	}

      /* If this is a real relocation (as opposed to a lituse hint), then
	 the relocation width should match the operand width.
	 Take care of -MDISP in operand table.  */
      else if (reloc < BFD_RELOC_UNUSED && reloc > 0)
	{
	  reloc_howto_type *reloc_howto
              = bfd_reloc_type_lookup (stdoutput,
                                       (bfd_reloc_code_real_type) reloc);
	  if (reloc_operand == NULL
	      || reloc_howto->bitsize != reloc_operand->bits)
	    {
	      as_bad (_("invalid relocation for field"));
	      return;
	    }
	}

      fixup = &insn->fixups[insn->nfixups++];
      if (reloc_exp)
	fixup->exp = *reloc_exp;
      else
	fixup->exp.X_op = O_absent;
      fixup->reloc = reloc;
    }

  insn->insn = image;
}

/* Handle all "simple" integer register loads -- ldq, ldq_l, ldq_u,
   etc.  They differ from the real instructions in that they do simple
   expressions like the lda macro.  */

static void
emit_ir_load (const expressionS *tok,
	      int ntok,
	      const void * opname)
{
  int basereg;
  long lituse;
  expressionS newtok[3];
  struct alpha_insn insn;
  const char *symname
    = tok[1].X_add_symbol ? S_GET_NAME (tok[1].X_add_symbol): "";
  int symlen = strlen (symname);

  if (ntok == 2)
    basereg = (tok[1].X_op == O_constant ? AXP_REG_ZERO : alpha_gp_register);
  else
    basereg = tok[2].X_add_number;

  lituse = load_expression (tok[0].X_add_number, &tok[1],
			    &basereg, &newtok[1], (const char *) opname);

  if (basereg == alpha_gp_register &&
      (symlen > 4 && strcmp (&symname [symlen - 4], "..lk") == 0))
    return;

  newtok[0] = tok[0];
  set_tok_preg (newtok[2], basereg);

  assemble_tokens_to_insn ((const char *) opname, newtok, 3, &insn);

  if (lituse)
    {
      gas_assert (insn.nfixups < MAX_INSN_FIXUPS);
      insn.fixups[insn.nfixups].reloc = DUMMY_RELOC_LITUSE_BASE;
      insn.fixups[insn.nfixups].exp.X_op = O_absent;
      insn.nfixups++;
      insn.sequence = lituse;
    }

  emit_insn (&insn);
}

/* Handle fp register loads, and both integer and fp register stores.
   Again, we handle simple expressions.  */

static void
emit_loadstore (const expressionS *tok,
		int ntok,
		const void * opname)
{
  int basereg;
  long lituse;
  expressionS newtok[3];
  struct alpha_insn insn;

  if (ntok == 2)
    basereg = (tok[1].X_op == O_constant ? AXP_REG_ZERO : alpha_gp_register);
  else
    basereg = tok[2].X_add_number;

  if (tok[1].X_op != O_constant || !range_signed_16 (tok[1].X_add_number))
    {
      if (alpha_noat_on)
	as_bad (_("macro requires $at register while noat in effect"));

      lituse = load_expression (AXP_REG_AT, &tok[1],
				&basereg, &newtok[1], (const char *) opname);
    }
  else
    {
      newtok[1] = tok[1];
      lituse = 0;
    }

  newtok[0] = tok[0];
  set_tok_preg (newtok[2], basereg);

  assemble_tokens_to_insn ((const char *) opname, newtok, 3, &insn);

  if (lituse)
    {
      gas_assert (insn.nfixups < MAX_INSN_FIXUPS);
      insn.fixups[insn.nfixups].reloc = DUMMY_RELOC_LITUSE_BASE;
      insn.fixups[insn.nfixups].exp.X_op = O_absent;
      insn.nfixups++;
      insn.sequence = lituse;
    }

  emit_insn (&insn);
}

/* Load a half-word or byte as an unsigned value.  */

static void
emit_ldXu (const expressionS *tok,
	   int ntok,
	   const void * vlgsize)
{
  if (alpha_target & AXP_OPCODE_BWX)
    emit_ir_load (tok, ntok, ldXu_op[(long) vlgsize]);
  else
    {
      expressionS newtok[3];
      struct alpha_insn insn;
      int basereg;
      long lituse;

      if (alpha_noat_on)
	as_bad (_("macro requires $at register while noat in effect"));

      if (ntok == 2)
	basereg = (tok[1].X_op == O_constant
		   ? AXP_REG_ZERO : alpha_gp_register);
      else
	basereg = tok[2].X_add_number;

      /* Emit "lda $at, exp".  */
      lituse = load_expression (AXP_REG_AT, &tok[1], &basereg, NULL, "lda");

      /* Emit "ldq_u targ, 0($at)".  */
      newtok[0] = tok[0];
      set_tok_const (newtok[1], 0);
      set_tok_preg (newtok[2], basereg);
      assemble_tokens_to_insn ("ldq_u", newtok, 3, &insn);

      if (lituse)
	{
	  gas_assert (insn.nfixups < MAX_INSN_FIXUPS);
	  insn.fixups[insn.nfixups].reloc = DUMMY_RELOC_LITUSE_BASE;
	  insn.fixups[insn.nfixups].exp.X_op = O_absent;
	  insn.nfixups++;
	  insn.sequence = lituse;
	}

      emit_insn (&insn);

      /* Emit "extXl targ, $at, targ".  */
      set_tok_reg (newtok[1], basereg);
      newtok[2] = newtok[0];
      assemble_tokens_to_insn (extXl_op[(long) vlgsize], newtok, 3, &insn);

      if (lituse)
	{
	  gas_assert (insn.nfixups < MAX_INSN_FIXUPS);
	  insn.fixups[insn.nfixups].reloc = DUMMY_RELOC_LITUSE_BYTOFF;
	  insn.fixups[insn.nfixups].exp.X_op = O_absent;
	  insn.nfixups++;
	  insn.sequence = lituse;
	}

      emit_insn (&insn);
    }
}

/* Load a half-word or byte as a signed value.  */

static void
emit_ldX (const expressionS *tok,
	  int ntok,
	  const void * vlgsize)
{
  emit_ldXu (tok, ntok, vlgsize);
  assemble_tokens (sextX_op[(long) vlgsize], tok, 1, 1);
}

/* Load an integral value from an unaligned address as an unsigned
   value.  */

static void
emit_uldXu (const expressionS *tok,
	    int ntok,
	    const void * vlgsize)
{
  long lgsize = (long) vlgsize;
  expressionS newtok[3];

  if (alpha_noat_on)
    as_bad (_("macro requires $at register while noat in effect"));

  /* Emit "lda $at, exp".  */
  memcpy (newtok, tok, sizeof (expressionS) * ntok);
  newtok[0].X_add_number = AXP_REG_AT;
  assemble_tokens ("lda", newtok, ntok, 1);

  /* Emit "ldq_u $t9, 0($at)".  */
  set_tok_reg (newtok[0], AXP_REG_T9);
  set_tok_const (newtok[1], 0);
  set_tok_preg (newtok[2], AXP_REG_AT);
  assemble_tokens ("ldq_u", newtok, 3, 1);

  /* Emit "ldq_u $t10, size-1($at)".  */
  set_tok_reg (newtok[0], AXP_REG_T10);
  set_tok_const (newtok[1], (1 << lgsize) - 1);
  assemble_tokens ("ldq_u", newtok, 3, 1);

  /* Emit "extXl $t9, $at, $t9".  */
  set_tok_reg (newtok[0], AXP_REG_T9);
  set_tok_reg (newtok[1], AXP_REG_AT);
  set_tok_reg (newtok[2], AXP_REG_T9);
  assemble_tokens (extXl_op[lgsize], newtok, 3, 1);

  /* Emit "extXh $t10, $at, $t10".  */
  set_tok_reg (newtok[0], AXP_REG_T10);
  set_tok_reg (newtok[2], AXP_REG_T10);
  assemble_tokens (extXh_op[lgsize], newtok, 3, 1);

  /* Emit "or $t9, $t10, targ".  */
  set_tok_reg (newtok[0], AXP_REG_T9);
  set_tok_reg (newtok[1], AXP_REG_T10);
  newtok[2] = tok[0];
  assemble_tokens ("or", newtok, 3, 1);
}

/* Load an integral value from an unaligned address as a signed value.
   Note that quads should get funneled to the unsigned load since we
   don't have to do the sign extension.  */

static void
emit_uldX (const expressionS *tok,
	   int ntok,
	   const void * vlgsize)
{
  emit_uldXu (tok, ntok, vlgsize);
  assemble_tokens (sextX_op[(long) vlgsize], tok, 1, 1);
}

/* Implement the ldil macro.  */

static void
emit_ldil (const expressionS *tok,
	   int ntok,
	   const void * unused ATTRIBUTE_UNUSED)
{
  expressionS newtok[2];

  memcpy (newtok, tok, sizeof (newtok));
  newtok[1].X_add_number = sign_extend_32 (tok[1].X_add_number);

  assemble_tokens ("lda", newtok, ntok, 1);
}

/* Store a half-word or byte.  */

static void
emit_stX (const expressionS *tok,
	  int ntok,
	  const void * vlgsize)
{
  int lgsize = (int) (long) vlgsize;

  if (alpha_target & AXP_OPCODE_BWX)
    emit_loadstore (tok, ntok, stX_op[lgsize]);
  else
    {
      expressionS newtok[3];
      struct alpha_insn insn;
      int basereg;
      long lituse;

      if (alpha_noat_on)
	as_bad (_("macro requires $at register while noat in effect"));

      if (ntok == 2)
	basereg = (tok[1].X_op == O_constant
		   ? AXP_REG_ZERO : alpha_gp_register);
      else
	basereg = tok[2].X_add_number;

      /* Emit "lda $at, exp".  */
      lituse = load_expression (AXP_REG_AT, &tok[1], &basereg, NULL, "lda");

      /* Emit "ldq_u $t9, 0($at)".  */
      set_tok_reg (newtok[0], AXP_REG_T9);
      set_tok_const (newtok[1], 0);
      set_tok_preg (newtok[2], basereg);
      assemble_tokens_to_insn ("ldq_u", newtok, 3, &insn);

      if (lituse)
	{
	  gas_assert (insn.nfixups < MAX_INSN_FIXUPS);
	  insn.fixups[insn.nfixups].reloc = DUMMY_RELOC_LITUSE_BASE;
	  insn.fixups[insn.nfixups].exp.X_op = O_absent;
	  insn.nfixups++;
	  insn.sequence = lituse;
	}

      emit_insn (&insn);

      /* Emit "insXl src, $at, $t10".  */
      newtok[0] = tok[0];
      set_tok_reg (newtok[1], basereg);
      set_tok_reg (newtok[2], AXP_REG_T10);
      assemble_tokens_to_insn (insXl_op[lgsize], newtok, 3, &insn);

      if (lituse)
	{
	  gas_assert (insn.nfixups < MAX_INSN_FIXUPS);
	  insn.fixups[insn.nfixups].reloc = DUMMY_RELOC_LITUSE_BYTOFF;
	  insn.fixups[insn.nfixups].exp.X_op = O_absent;
	  insn.nfixups++;
	  insn.sequence = lituse;
	}

      emit_insn (&insn);

      /* Emit "mskXl $t9, $at, $t9".  */
      set_tok_reg (newtok[0], AXP_REG_T9);
      newtok[2] = newtok[0];
      assemble_tokens_to_insn (mskXl_op[lgsize], newtok, 3, &insn);

      if (lituse)
	{
	  gas_assert (insn.nfixups < MAX_INSN_FIXUPS);
	  insn.fixups[insn.nfixups].reloc = DUMMY_RELOC_LITUSE_BYTOFF;
	  insn.fixups[insn.nfixups].exp.X_op = O_absent;
	  insn.nfixups++;
	  insn.sequence = lituse;
	}

      emit_insn (&insn);

      /* Emit "or $t9, $t10, $t9".  */
      set_tok_reg (newtok[1], AXP_REG_T10);
      assemble_tokens ("or", newtok, 3, 1);

      /* Emit "stq_u $t9, 0($at).  */
      set_tok_const(newtok[1], 0);
      set_tok_preg (newtok[2], AXP_REG_AT);
      assemble_tokens_to_insn ("stq_u", newtok, 3, &insn);

      if (lituse)
	{
	  gas_assert (insn.nfixups < MAX_INSN_FIXUPS);
	  insn.fixups[insn.nfixups].reloc = DUMMY_RELOC_LITUSE_BASE;
	  insn.fixups[insn.nfixups].exp.X_op = O_absent;
	  insn.nfixups++;
	  insn.sequence = lituse;
	}

      emit_insn (&insn);
    }
}

/* Store an integer to an unaligned address.  */

static void
emit_ustX (const expressionS *tok,
	   int ntok,
	   const void * vlgsize)
{
  int lgsize = (int) (long) vlgsize;
  expressionS newtok[3];

  /* Emit "lda $at, exp".  */
  memcpy (newtok, tok, sizeof (expressionS) * ntok);
  newtok[0].X_add_number = AXP_REG_AT;
  assemble_tokens ("lda", newtok, ntok, 1);

  /* Emit "ldq_u $9, 0($at)".  */
  set_tok_reg (newtok[0], AXP_REG_T9);
  set_tok_const (newtok[1], 0);
  set_tok_preg (newtok[2], AXP_REG_AT);
  assemble_tokens ("ldq_u", newtok, 3, 1);

  /* Emit "ldq_u $10, size-1($at)".  */
  set_tok_reg (newtok[0], AXP_REG_T10);
  set_tok_const (newtok[1], (1 << lgsize) - 1);
  assemble_tokens ("ldq_u", newtok, 3, 1);

  /* Emit "insXl src, $at, $t11".  */
  newtok[0] = tok[0];
  set_tok_reg (newtok[1], AXP_REG_AT);
  set_tok_reg (newtok[2], AXP_REG_T11);
  assemble_tokens (insXl_op[lgsize], newtok, 3, 1);

  /* Emit "insXh src, $at, $t12".  */
  set_tok_reg (newtok[2], AXP_REG_T12);
  assemble_tokens (insXh_op[lgsize], newtok, 3, 1);

  /* Emit "mskXl $t9, $at, $t9".  */
  set_tok_reg (newtok[0], AXP_REG_T9);
  newtok[2] = newtok[0];
  assemble_tokens (mskXl_op[lgsize], newtok, 3, 1);

  /* Emit "mskXh $t10, $at, $t10".  */
  set_tok_reg (newtok[0], AXP_REG_T10);
  newtok[2] = newtok[0];
  assemble_tokens (mskXh_op[lgsize], newtok, 3, 1);

  /* Emit "or $t9, $t11, $t9".  */
  set_tok_reg (newtok[0], AXP_REG_T9);
  set_tok_reg (newtok[1], AXP_REG_T11);
  newtok[2] = newtok[0];
  assemble_tokens ("or", newtok, 3, 1);

  /* Emit "or $t10, $t12, $t10".  */
  set_tok_reg (newtok[0], AXP_REG_T10);
  set_tok_reg (newtok[1], AXP_REG_T12);
  newtok[2] = newtok[0];
  assemble_tokens ("or", newtok, 3, 1);

  /* Emit "stq_u $t10, size-1($at)".  */
  set_tok_reg (newtok[0], AXP_REG_T10);
  set_tok_const (newtok[1], (1 << lgsize) - 1);
  set_tok_preg (newtok[2], AXP_REG_AT);
  assemble_tokens ("stq_u", newtok, 3, 1);

  /* Emit "stq_u $t9, 0($at)".  */
  set_tok_reg (newtok[0], AXP_REG_T9);
  set_tok_const (newtok[1], 0);
  assemble_tokens ("stq_u", newtok, 3, 1);
}

/* Sign extend a half-word or byte.  The 32-bit sign extend is
   implemented as "addl $31, $r, $t" in the opcode table.  */

static void
emit_sextX (const expressionS *tok,
	    int ntok,
	    const void * vlgsize)
{
  long lgsize = (long) vlgsize;

  if (alpha_target & AXP_OPCODE_BWX)
    assemble_tokens (sextX_op[lgsize], tok, ntok, 0);
  else
    {
      int bitshift = 64 - 8 * (1 << lgsize);
      expressionS newtok[3];

      /* Emit "sll src,bits,dst".  */
      newtok[0] = tok[0];
      set_tok_const (newtok[1], bitshift);
      newtok[2] = tok[ntok - 1];
      assemble_tokens ("sll", newtok, 3, 1);

      /* Emit "sra dst,bits,dst".  */
      newtok[0] = newtok[2];
      assemble_tokens ("sra", newtok, 3, 1);
    }
}

/* Implement the division and modulus macros.  */

#ifdef OBJ_EVAX

/* Make register usage like in normal procedure call.
   Don't clobber PV and RA.  */

static void
emit_division (const expressionS *tok,
	       int ntok,
	       const void * symname)
{
  /* DIVISION and MODULUS. Yech.

     Convert
        OP x,y,result
     to
        mov x,R16	# if x != R16
        mov y,R17	# if y != R17
        lda AT,__OP
        jsr AT,(AT),0
        mov R0,result

     with appropriate optimizations if R0,R16,R17 are the registers
     specified by the compiler.  */

  int xr, yr, rr;
  symbolS *sym;
  expressionS newtok[3];

  xr = regno (tok[0].X_add_number);
  yr = regno (tok[1].X_add_number);

  if (ntok < 3)
    rr = xr;
  else
    rr = regno (tok[2].X_add_number);

  /* Move the operands into the right place.  */
  if (yr == AXP_REG_R16 && xr == AXP_REG_R17)
    {
      /* They are in exactly the wrong order -- swap through AT.  */
      if (alpha_noat_on)
	as_bad (_("macro requires $at register while noat in effect"));

      set_tok_reg (newtok[0], AXP_REG_R16);
      set_tok_reg (newtok[1], AXP_REG_AT);
      assemble_tokens ("mov", newtok, 2, 1);

      set_tok_reg (newtok[0], AXP_REG_R17);
      set_tok_reg (newtok[1], AXP_REG_R16);
      assemble_tokens ("mov", newtok, 2, 1);

      set_tok_reg (newtok[0], AXP_REG_AT);
      set_tok_reg (newtok[1], AXP_REG_R17);
      assemble_tokens ("mov", newtok, 2, 1);
    }
  else
    {
      if (yr == AXP_REG_R16)
	{
	  set_tok_reg (newtok[0], AXP_REG_R16);
	  set_tok_reg (newtok[1], AXP_REG_R17);
	  assemble_tokens ("mov", newtok, 2, 1);
	}

      if (xr != AXP_REG_R16)
	{
	  set_tok_reg (newtok[0], xr);
	  set_tok_reg (newtok[1], AXP_REG_R16);
	  assemble_tokens ("mov", newtok, 2, 1);
	}

      if (yr != AXP_REG_R16 && yr != AXP_REG_R17)
	{
	  set_tok_reg (newtok[0], yr);
	  set_tok_reg (newtok[1], AXP_REG_R17);
	  assemble_tokens ("mov", newtok, 2, 1);
	}
    }

  sym = symbol_find_or_make ((const char *) symname);

  set_tok_reg (newtok[0], AXP_REG_AT);
  set_tok_sym (newtok[1], sym, 0);
  assemble_tokens ("lda", newtok, 2, 1);

  /* Call the division routine.  */
  set_tok_reg (newtok[0], AXP_REG_AT);
  set_tok_cpreg (newtok[1], AXP_REG_AT);
  set_tok_const (newtok[2], 0);
  assemble_tokens ("jsr", newtok, 3, 1);

  /* Move the result to the right place.  */
  if (rr != AXP_REG_R0)
    {
      set_tok_reg (newtok[0], AXP_REG_R0);
      set_tok_reg (newtok[1], rr);
      assemble_tokens ("mov", newtok, 2, 1);
    }
}

#else /* !OBJ_EVAX */

static void
emit_division (const expressionS *tok,
	       int ntok,
	       const void * symname)
{
  /* DIVISION and MODULUS. Yech.
     Convert
        OP x,y,result
     to
        lda pv,__OP
        mov x,t10
        mov y,t11
        jsr t9,(pv),__OP
        mov t12,result

     with appropriate optimizations if t10,t11,t12 are the registers
     specified by the compiler.  */

  int xr, yr, rr;
  symbolS *sym;
  expressionS newtok[3];

  xr = regno (tok[0].X_add_number);
  yr = regno (tok[1].X_add_number);

  if (ntok < 3)
    rr = xr;
  else
    rr = regno (tok[2].X_add_number);

  sym = symbol_find_or_make ((const char *) symname);

  /* Move the operands into the right place.  */
  if (yr == AXP_REG_T10 && xr == AXP_REG_T11)
    {
      /* They are in exactly the wrong order -- swap through AT.  */
      if (alpha_noat_on)
	as_bad (_("macro requires $at register while noat in effect"));

      set_tok_reg (newtok[0], AXP_REG_T10);
      set_tok_reg (newtok[1], AXP_REG_AT);
      assemble_tokens ("mov", newtok, 2, 1);

      set_tok_reg (newtok[0], AXP_REG_T11);
      set_tok_reg (newtok[1], AXP_REG_T10);
      assemble_tokens ("mov", newtok, 2, 1);

      set_tok_reg (newtok[0], AXP_REG_AT);
      set_tok_reg (newtok[1], AXP_REG_T11);
      assemble_tokens ("mov", newtok, 2, 1);
    }
  else
    {
      if (yr == AXP_REG_T10)
	{
	  set_tok_reg (newtok[0], AXP_REG_T10);
	  set_tok_reg (newtok[1], AXP_REG_T11);
	  assemble_tokens ("mov", newtok, 2, 1);
	}

      if (xr != AXP_REG_T10)
	{
	  set_tok_reg (newtok[0], xr);
	  set_tok_reg (newtok[1], AXP_REG_T10);
	  assemble_tokens ("mov", newtok, 2, 1);
	}

      if (yr != AXP_REG_T10 && yr != AXP_REG_T11)
	{
	  set_tok_reg (newtok[0], yr);
	  set_tok_reg (newtok[1], AXP_REG_T11);
	  assemble_tokens ("mov", newtok, 2, 1);
	}
    }

  /* Call the division routine.  */
  set_tok_reg (newtok[0], AXP_REG_T9);
  set_tok_sym (newtok[1], sym, 0);
  assemble_tokens ("jsr", newtok, 2, 1);

  /* Reload the GP register.  */
#ifdef OBJ_AOUT
FIXME
#endif
#if defined(OBJ_ECOFF) || defined(OBJ_ELF)
  set_tok_reg (newtok[0], alpha_gp_register);
  set_tok_const (newtok[1], 0);
  set_tok_preg (newtok[2], AXP_REG_T9);
  assemble_tokens ("ldgp", newtok, 3, 1);
#endif

  /* Move the result to the right place.  */
  if (rr != AXP_REG_T12)
    {
      set_tok_reg (newtok[0], AXP_REG_T12);
      set_tok_reg (newtok[1], rr);
      assemble_tokens ("mov", newtok, 2, 1);
    }
}

#endif /* !OBJ_EVAX */

/* The jsr and jmp macros differ from their instruction counterparts
   in that they can load the target address and default most
   everything.  */

static void
emit_jsrjmp (const expressionS *tok,
	     int ntok,
	     const void * vopname)
{
  const char *opname = (const char *) vopname;
  struct alpha_insn insn;
  expressionS newtok[3];
  int r, tokidx = 0;
  long lituse = 0;

  if (tokidx < ntok && tok[tokidx].X_op == O_register)
    r = regno (tok[tokidx++].X_add_number);
  else
    r = strcmp (opname, "jmp") == 0 ? AXP_REG_ZERO : AXP_REG_RA;

  set_tok_reg (newtok[0], r);

  if (tokidx < ntok &&
      (tok[tokidx].X_op == O_pregister || tok[tokidx].X_op == O_cpregister))
    r = regno (tok[tokidx++].X_add_number);
#ifdef OBJ_EVAX
  /* Keep register if jsr $n.<sym>.  */
#else
  else
    {
      int basereg = alpha_gp_register;
      lituse = load_expression (r = AXP_REG_PV, &tok[tokidx],
				&basereg, NULL, opname);
    }
#endif

  set_tok_cpreg (newtok[1], r);

#ifndef OBJ_EVAX
  if (tokidx < ntok)
    newtok[2] = tok[tokidx];
  else
#endif
    set_tok_const (newtok[2], 0);

  assemble_tokens_to_insn (opname, newtok, 3, &insn);

  if (lituse)
    {
      gas_assert (insn.nfixups < MAX_INSN_FIXUPS);
      insn.fixups[insn.nfixups].reloc = DUMMY_RELOC_LITUSE_JSR;
      insn.fixups[insn.nfixups].exp.X_op = O_absent;
      insn.nfixups++;
      insn.sequence = lituse;
    }

#ifdef OBJ_EVAX
  if (alpha_flag_replace
      && r == AXP_REG_RA
      && tok[tokidx].X_add_symbol
      && alpha_linkage_symbol)
    {
      /* Create a BOH reloc for 'jsr $27,NAME'.  */
      const char *symname = S_GET_NAME (tok[tokidx].X_add_symbol);
      int symlen = strlen (symname);
      char *ensymname;

      /* Build the entry name as 'NAME..en'.  */
      ensymname = XNEWVEC (char, symlen + 5);
      memcpy (ensymname, symname, symlen);
      memcpy (ensymname + symlen, "..en", 5);

      gas_assert (insn.nfixups < MAX_INSN_FIXUPS);
      if (insn.nfixups > 0)
	{
	  memmove (&insn.fixups[1], &insn.fixups[0],
		   sizeof(struct alpha_fixup) * insn.nfixups);
	}

      /* The fixup must be the same as the BFD_RELOC_ALPHA_NOP
	 case in load_expression.  See B.4.5.2 of the OpenVMS
	 Linker Utility Manual.  */
      insn.fixups[0].reloc = BFD_RELOC_ALPHA_BOH;
      insn.fixups[0].exp.X_op = O_symbol;
      insn.fixups[0].exp.X_add_symbol = symbol_find_or_make (ensymname);
      insn.fixups[0].exp.X_add_number = 0;
      insn.fixups[0].xtrasym = alpha_linkage_symbol;
      insn.fixups[0].procsym = alpha_evax_proc->symbol;
      insn.nfixups++;
      alpha_linkage_symbol = 0;
      free (ensymname);
    }
#endif

  emit_insn (&insn);
}

/* The ret and jcr instructions differ from their instruction
   counterparts in that everything can be defaulted.  */

static void
emit_retjcr (const expressionS *tok,
	     int ntok,
	     const void * vopname)
{
  const char *opname = (const char *) vopname;
  expressionS newtok[3];
  int r, tokidx = 0;

  if (tokidx < ntok && tok[tokidx].X_op == O_register)
    r = regno (tok[tokidx++].X_add_number);
  else
    r = AXP_REG_ZERO;

  set_tok_reg (newtok[0], r);

  if (tokidx < ntok &&
      (tok[tokidx].X_op == O_pregister || tok[tokidx].X_op == O_cpregister))
    r = regno (tok[tokidx++].X_add_number);
  else
    r = AXP_REG_RA;

  set_tok_cpreg (newtok[1], r);

  if (tokidx < ntok)
    newtok[2] = tok[tokidx];
  else
    set_tok_const (newtok[2], strcmp (opname, "ret") == 0);

  assemble_tokens (opname, newtok, 3, 0);
}

/* Implement the ldgp macro.  */

static void
emit_ldgp (const expressionS *tok ATTRIBUTE_UNUSED,
	   int ntok ATTRIBUTE_UNUSED,
	   const void * unused ATTRIBUTE_UNUSED)
{
#ifdef OBJ_AOUT
FIXME
#endif
#if defined(OBJ_ECOFF) || defined(OBJ_ELF)
  /* from "ldgp r1,n(r2)", generate "ldah r1,X(R2); lda r1,Y(r1)"
     with appropriate constants and relocations.  */
  struct alpha_insn insn;
  expressionS newtok[3];
  expressionS addend;

#ifdef OBJ_ECOFF
  if (regno (tok[2].X_add_number) == AXP_REG_PV)
    ecoff_set_gp_prolog_size (0);
#endif

  newtok[0] = tok[0];
  set_tok_const (newtok[1], 0);
  newtok[2] = tok[2];

  assemble_tokens_to_insn ("ldah", newtok, 3, &insn);

  addend = tok[1];

#ifdef OBJ_ECOFF
  if (addend.X_op != O_constant)
    as_bad (_("can not resolve expression"));
  addend.X_op = O_symbol;
  addend.X_add_symbol = alpha_gp_symbol;
#endif

  insn.nfixups = 1;
  insn.fixups[0].exp = addend;
  insn.fixups[0].reloc = BFD_RELOC_ALPHA_GPDISP_HI16;
  insn.sequence = next_sequence_num;

  emit_insn (&insn);

  set_tok_preg (newtok[2], tok[0].X_add_number);

  assemble_tokens_to_insn ("lda", newtok, 3, &insn);

#ifdef OBJ_ECOFF
  addend.X_add_number += 4;
#endif

  insn.nfixups = 1;
  insn.fixups[0].exp = addend;
  insn.fixups[0].reloc = BFD_RELOC_ALPHA_GPDISP_LO16;
  insn.sequence = next_sequence_num--;

  emit_insn (&insn);
#endif /* OBJ_ECOFF || OBJ_ELF */
}

/* The macro table.  */

static const struct alpha_macro alpha_macros[] =
{
/* Load/Store macros.  */
  { "lda",	emit_lda, NULL,
    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
  { "ldah",	emit_ldah, NULL,
    { MACRO_IR, MACRO_EXP, MACRO_EOA } },

  { "ldl",	emit_ir_load, "ldl",
    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
  { "ldl_l",	emit_ir_load, "ldl_l",
    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
  { "ldq",	emit_ir_load, "ldq",
    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
  { "ldq_l",	emit_ir_load, "ldq_l",
    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
  { "ldq_u",	emit_ir_load, "ldq_u",
    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
  { "ldf",	emit_loadstore, "ldf",
    { MACRO_FPR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
  { "ldg",	emit_loadstore, "ldg",
    { MACRO_FPR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
  { "lds",	emit_loadstore, "lds",
    { MACRO_FPR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
  { "ldt",	emit_loadstore, "ldt",
    { MACRO_FPR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },

  { "ldb",	emit_ldX, (void *) 0,
    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
  { "ldbu",	emit_ldXu, (void *) 0,
    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
  { "ldw",	emit_ldX, (void *) 1,
    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
  { "ldwu",	emit_ldXu, (void *) 1,
    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },

  { "uldw",	emit_uldX, (void *) 1,
    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
  { "uldwu",	emit_uldXu, (void *) 1,
    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
  { "uldl",	emit_uldX, (void *) 2,
    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
  { "uldlu",	emit_uldXu, (void *) 2,
    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
  { "uldq",	emit_uldXu, (void *) 3,
    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },

  { "ldgp",	emit_ldgp, NULL,
    { MACRO_IR, MACRO_EXP, MACRO_PIR, MACRO_EOA } },

  { "ldi",	emit_lda, NULL,
    { MACRO_IR, MACRO_EXP, MACRO_EOA } },
  { "ldil",	emit_ldil, NULL,
    { MACRO_IR, MACRO_EXP, MACRO_EOA } },
  { "ldiq",	emit_lda, NULL,
    { MACRO_IR, MACRO_EXP, MACRO_EOA } },

  { "stl",	emit_loadstore, "stl",
    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
  { "stl_c",	emit_loadstore, "stl_c",
    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
  { "stq",	emit_loadstore, "stq",
    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
  { "stq_c",	emit_loadstore, "stq_c",
    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
  { "stq_u",	emit_loadstore, "stq_u",
    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
  { "stf",	emit_loadstore, "stf",
    { MACRO_FPR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
  { "stg",	emit_loadstore, "stg",
    { MACRO_FPR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
  { "sts",	emit_loadstore, "sts",
    { MACRO_FPR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
  { "stt",	emit_loadstore, "stt",
    { MACRO_FPR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },

  { "stb",	emit_stX, (void *) 0,
    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
  { "stw",	emit_stX, (void *) 1,
    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
  { "ustw",	emit_ustX, (void *) 1,
    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
  { "ustl",	emit_ustX, (void *) 2,
    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
  { "ustq",	emit_ustX, (void *) 3,
    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },

/* Arithmetic macros.  */

  { "sextb",	emit_sextX, (void *) 0,
    { MACRO_IR, MACRO_IR, MACRO_EOA,
      MACRO_IR, MACRO_EOA,
      /* MACRO_EXP, MACRO_IR, MACRO_EOA */ } },
  { "sextw",	emit_sextX, (void *) 1,
    { MACRO_IR, MACRO_IR, MACRO_EOA,
      MACRO_IR, MACRO_EOA,
      /* MACRO_EXP, MACRO_IR, MACRO_EOA */ } },

  { "divl",	emit_division, "__divl",
    { MACRO_IR, MACRO_IR, MACRO_IR, MACRO_EOA,
      MACRO_IR, MACRO_IR, MACRO_EOA,
      /* MACRO_IR, MACRO_EXP, MACRO_IR, MACRO_EOA,
      MACRO_IR, MACRO_EXP, MACRO_EOA */ } },
  { "divlu",	emit_division, "__divlu",
    { MACRO_IR, MACRO_IR, MACRO_IR, MACRO_EOA,
      MACRO_IR, MACRO_IR, MACRO_EOA,
      /* MACRO_IR, MACRO_EXP, MACRO_IR, MACRO_EOA,
      MACRO_IR, MACRO_EXP, MACRO_EOA */ } },
  { "divq",	emit_division, "__divq",
    { MACRO_IR, MACRO_IR, MACRO_IR, MACRO_EOA,
      MACRO_IR, MACRO_IR, MACRO_EOA,
      /* MACRO_IR, MACRO_EXP, MACRO_IR, MACRO_EOA,
      MACRO_IR, MACRO_EXP, MACRO_EOA */ } },
  { "divqu",	emit_division, "__divqu",
    { MACRO_IR, MACRO_IR, MACRO_IR, MACRO_EOA,
      MACRO_IR, MACRO_IR, MACRO_EOA,
      /* MACRO_IR, MACRO_EXP, MACRO_IR, MACRO_EOA,
      MACRO_IR, MACRO_EXP, MACRO_EOA */ } },
  { "reml",	emit_division, "__reml",
    { MACRO_IR, MACRO_IR, MACRO_IR, MACRO_EOA,
      MACRO_IR, MACRO_IR, MACRO_EOA,
      /* MACRO_IR, MACRO_EXP, MACRO_IR, MACRO_EOA,
      MACRO_IR, MACRO_EXP, MACRO_EOA */ } },
  { "remlu",	emit_division, "__remlu",
    { MACRO_IR, MACRO_IR, MACRO_IR, MACRO_EOA,
      MACRO_IR, MACRO_IR, MACRO_EOA,
      /* MACRO_IR, MACRO_EXP, MACRO_IR, MACRO_EOA,
      MACRO_IR, MACRO_EXP, MACRO_EOA */ } },
  { "remq",	emit_division, "__remq",
    { MACRO_IR, MACRO_IR, MACRO_IR, MACRO_EOA,
      MACRO_IR, MACRO_IR, MACRO_EOA,
      /* MACRO_IR, MACRO_EXP, MACRO_IR, MACRO_EOA,
      MACRO_IR, MACRO_EXP, MACRO_EOA */ } },
  { "remqu",	emit_division, "__remqu",
    { MACRO_IR, MACRO_IR, MACRO_IR, MACRO_EOA,
      MACRO_IR, MACRO_IR, MACRO_EOA,
      /* MACRO_IR, MACRO_EXP, MACRO_IR, MACRO_EOA,
      MACRO_IR, MACRO_EXP, MACRO_EOA */ } },

  { "jsr",	emit_jsrjmp, "jsr",
    { MACRO_PIR, MACRO_EXP, MACRO_EOA,
      MACRO_PIR, MACRO_EOA,
      MACRO_IR,  MACRO_EXP, MACRO_EOA,
      MACRO_EXP, MACRO_EOA } },
  { "jmp",	emit_jsrjmp, "jmp",
    { MACRO_PIR, MACRO_EXP, MACRO_EOA,
      MACRO_PIR, MACRO_EOA,
      MACRO_IR,  MACRO_EXP, MACRO_EOA,
      MACRO_EXP, MACRO_EOA } },
  { "ret",	emit_retjcr, "ret",
    { MACRO_IR, MACRO_EXP, MACRO_EOA,
      MACRO_IR, MACRO_EOA,
      MACRO_PIR, MACRO_EXP, MACRO_EOA,
      MACRO_PIR, MACRO_EOA,
      MACRO_EXP, MACRO_EOA,
      MACRO_EOA } },
  { "jcr",	emit_retjcr, "jcr",
    { MACRO_IR,  MACRO_EXP, MACRO_EOA,
      MACRO_IR,  MACRO_EOA,
      MACRO_PIR, MACRO_EXP, MACRO_EOA,
      MACRO_PIR, MACRO_EOA,
      MACRO_EXP, MACRO_EOA,
      MACRO_EOA } },
  { "jsr_coroutine",	emit_retjcr, "jcr",
    { MACRO_IR,  MACRO_EXP, MACRO_EOA,
      MACRO_IR,  MACRO_EOA,
      MACRO_PIR, MACRO_EXP, MACRO_EOA,
      MACRO_PIR, MACRO_EOA,
      MACRO_EXP, MACRO_EOA,
      MACRO_EOA } },
};

static const unsigned int alpha_num_macros
  = sizeof (alpha_macros) / sizeof (*alpha_macros);

/* Search forward through all variants of a macro looking for a syntax
   match.  */

static const struct alpha_macro *
find_macro_match (const struct alpha_macro *first_macro,
		  const expressionS *tok,
		  int *pntok)

{
  const struct alpha_macro *macro = first_macro;
  int ntok = *pntok;

  do
    {
      const enum alpha_macro_arg *arg = macro->argsets;
      int tokidx = 0;

      while (*arg)
	{
	  switch (*arg)
	    {
	    case MACRO_EOA:
	      if (tokidx == ntok)
		return macro;
	      else
		tokidx = 0;
	      break;

	      /* Index register.  */
	    case MACRO_IR:
	      if (tokidx >= ntok || tok[tokidx].X_op != O_register
		  || !is_ir_num (tok[tokidx].X_add_number))
		goto match_failed;
	      ++tokidx;
	      break;

	      /* Parenthesized index register.  */
	    case MACRO_PIR:
	      if (tokidx >= ntok || tok[tokidx].X_op != O_pregister
		  || !is_ir_num (tok[tokidx].X_add_number))
		goto match_failed;
	      ++tokidx;
	      break;

	      /* Optional parenthesized index register.  */
	    case MACRO_OPIR:
	      if (tokidx < ntok && tok[tokidx].X_op == O_pregister
		  && is_ir_num (tok[tokidx].X_add_number))
		++tokidx;
	      break;

	      /* Leading comma with a parenthesized index register.  */
	    case MACRO_CPIR:
	      if (tokidx >= ntok || tok[tokidx].X_op != O_cpregister
		  || !is_ir_num (tok[tokidx].X_add_number))
		goto match_failed;
	      ++tokidx;
	      break;

	      /* Floating point register.  */
	    case MACRO_FPR:
	      if (tokidx >= ntok || tok[tokidx].X_op != O_register
		  || !is_fpr_num (tok[tokidx].X_add_number))
		goto match_failed;
	      ++tokidx;
	      break;

	      /* Normal expression.  */
	    case MACRO_EXP:
	      if (tokidx >= ntok)
		goto match_failed;
	      switch (tok[tokidx].X_op)
		{
		case O_illegal:
		case O_absent:
		case O_register:
		case O_pregister:
		case O_cpregister:
		case O_literal:
		case O_lituse_base:
		case O_lituse_bytoff:
		case O_lituse_jsr:
		case O_gpdisp:
		case O_gprelhigh:
		case O_gprellow:
		case O_gprel:
		case O_samegp:
		  goto match_failed;

		default:
		  break;
		}
	      ++tokidx;
	      break;

	    match_failed:
	      while (*arg != MACRO_EOA)
		++arg;
	      tokidx = 0;
	      break;
	    }
	  ++arg;
	}
    }
  while (++macro - alpha_macros < (int) alpha_num_macros
	 && !strcmp (macro->name, first_macro->name));

  return NULL;
}

/* Given an opcode name and a pre-tokenized set of arguments, take the
   opcode all the way through emission.  */

static void
assemble_tokens (const char *opname,
		 const expressionS *tok,
		 int ntok,
		 int local_macros_on)
{
  int found_something = 0;
  const struct alpha_opcode *opcode;
  const struct alpha_macro *macro;
  int cpumatch = 1;
  extended_bfd_reloc_code_real_type reloc = BFD_RELOC_UNUSED;

#ifdef RELOC_OP_P
  /* If a user-specified relocation is present, this is not a macro.  */
  if (ntok && USER_RELOC_P (tok[ntok - 1].X_op))
    {
      reloc = ALPHA_RELOC_TABLE (tok[ntok - 1].X_op)->reloc;
      ntok--;
    }
  else
#endif
  if (local_macros_on)
    {
      macro = (const struct alpha_macro *) str_hash_find (alpha_macro_hash,
							  opname);
      if (macro)
	{
	  found_something = 1;
	  macro = find_macro_match (macro, tok, &ntok);
	  if (macro)
	    {
	      (*macro->emit) (tok, ntok, macro->arg);
	      return;
	    }
	}
    }

  /* Search opcodes.  */
  opcode = (const struct alpha_opcode *) str_hash_find (alpha_opcode_hash,
							opname);
  if (opcode)
    {
      found_something = 1;
      opcode = find_opcode_match (opcode, tok, &ntok, &cpumatch);
      if (opcode)
	{
	  struct alpha_insn insn;
	  assemble_insn (opcode, tok, ntok, &insn, reloc);

	  /* Copy the sequence number for the reloc from the reloc token.  */
	  if (reloc != BFD_RELOC_UNUSED)
	    insn.sequence = tok[ntok].X_add_number;

	  emit_insn (&insn);
	  return;
	}
    }

  if (found_something)
    {
      if (cpumatch)
	as_bad (_("inappropriate arguments for opcode `%s'"), opname);
      else
	as_bad (_("opcode `%s' not supported for target %s"), opname,
		alpha_target_name);
    }
  else
    as_bad (_("unknown opcode `%s'"), opname);
}

#ifdef OBJ_EVAX

/* Add sym+addend to link pool.
   Return offset from current procedure value (pv) to entry in link pool.

   Add new fixup only if offset isn't 16bit.  */

static symbolS *
add_to_link_pool (symbolS *sym, offsetT addend)
{
  symbolS *basesym;
  segT current_section = now_seg;
  int current_subsec = now_subseg;
  char *p;
  segment_info_type *seginfo = seg_info (alpha_link_section);
  fixS *fixp;
  symbolS *linksym, *expsym;
  expressionS e;

  basesym = alpha_evax_proc->symbol;

  /* @@ This assumes all entries in a given section will be of the same
     size...  Probably correct, but unwise to rely on.  */
  /* This must always be called with the same subsegment.  */

  if (seginfo->frchainP)
    for (fixp = seginfo->frchainP->fix_root;
	 fixp != (fixS *) NULL;
	 fixp = fixp->fx_next)
      {
	if (fixp->fx_addsy == sym
	    && fixp->fx_offset == (valueT)addend
	    && fixp->tc_fix_data.info
	    && fixp->tc_fix_data.info->sym
	    && symbol_symbolS (fixp->tc_fix_data.info->sym)
	    && (symbol_get_value_expression (fixp->tc_fix_data.info->sym)
		->X_op_symbol == basesym))
	  return fixp->tc_fix_data.info->sym;
      }

  /* Not found, add a new entry.  */
  subseg_set (alpha_link_section, 0);
  linksym = symbol_new (FAKE_LABEL_NAME, now_seg, frag_now, frag_now_fix ());
  p = frag_more (8);
  memset (p, 0, 8);

  /* Create a symbol for 'basesym - linksym' (offset of the added entry).  */
  e.X_op = O_subtract;
  e.X_add_symbol = linksym;
  e.X_op_symbol = basesym;
  e.X_add_number = 0;
  expsym = make_expr_symbol (&e);

  /* Create a fixup for the entry.  */
  fixp = fix_new
    (frag_now, p - frag_now->fr_literal, 8, sym, addend, 0, BFD_RELOC_64);
  fixp->tc_fix_data.info = get_alpha_reloc_tag (next_sequence_num--);
  fixp->tc_fix_data.info->sym = expsym;

  subseg_set (current_section, current_subsec);

  /* Return the symbol.  */
  return expsym;
}
#endif /* OBJ_EVAX */

/* Assembler directives.  */

/* Handle the .text pseudo-op.  This is like the usual one, but it
   clears alpha_insn_label and restores auto alignment.  */

static void
s_alpha_text (int i)
{
#ifdef OBJ_ELF
  obj_elf_text (i);
#else
  s_text (i);
#endif
#ifdef OBJ_EVAX
  {
    symbolS * symbolP;

    symbolP = symbol_find (".text");
    if (symbolP == NULL)
      {
	symbolP = symbol_make (".text");
	S_SET_SEGMENT (symbolP, text_section);
	symbol_table_insert (symbolP);
      }
  }
#endif
  alpha_insn_label = NULL;
  alpha_auto_align_on = 1;
  alpha_current_align = 0;
}

/* Handle the .data pseudo-op.  This is like the usual one, but it
   clears alpha_insn_label and restores auto alignment.  */

static void
s_alpha_data (int i)
{
#ifdef OBJ_ELF
  obj_elf_data (i);
#else
  s_data (i);
#endif
  alpha_insn_label = NULL;
  alpha_auto_align_on = 1;
  alpha_current_align = 0;
}

#if defined (OBJ_ECOFF) || defined (OBJ_EVAX)

/* Handle the OSF/1 and openVMS .comm pseudo quirks.  */

static void
s_alpha_comm (int ignore ATTRIBUTE_UNUSED)
{
  char *name;
  char c;
  char *p;
  offsetT size;
  symbolS *symbolP;
#ifdef OBJ_EVAX
  offsetT temp;
  int log_align = 0;
#endif

  c = get_symbol_name (&name);

  /* Just after name is now '\0'.  */
  p = input_line_pointer;
  *p = c;

  SKIP_WHITESPACE_AFTER_NAME ();

  /* Alpha OSF/1 compiler doesn't provide the comma, gcc does.  */
  if (*input_line_pointer == ',')
    {
      input_line_pointer++;
      SKIP_WHITESPACE ();
    }
  if ((size = get_absolute_expression ()) < 0)
    {
      as_warn (_(".COMMon length (%ld.) <0! Ignored."), (long) size);
      ignore_rest_of_line ();
      return;
    }

  *p = 0;
  symbolP = symbol_find_or_make (name);
  *p = c;

  if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP))
    {
      as_bad (_("Ignoring attempt to re-define symbol"));
      ignore_rest_of_line ();
      return;
    }

#ifdef OBJ_EVAX
  if (*input_line_pointer != ',')
    temp = 8; /* Default alignment.  */
  else
    {
      input_line_pointer++;
      SKIP_WHITESPACE ();
      temp = get_absolute_expression ();
    }

  /* ??? Unlike on OSF/1, the alignment factor is not in log units.  */
  while ((temp >>= 1) != 0)
    ++log_align;

  if (*input_line_pointer == ',')
    {
      /* Extended form of the directive

	   .comm symbol, size, alignment, section

         where the "common" semantics is transferred to the section.
         The symbol is effectively an alias for the section name.  */

      segT sec;
      const char *sec_name;
      symbolS *sec_symbol;
      segT current_seg = now_seg;
      subsegT current_subseg = now_subseg;
      int cur_size;

      input_line_pointer++;
      SKIP_WHITESPACE ();
      sec_name = s_alpha_section_name ();
      sec_symbol = symbol_find_or_make (sec_name);
      sec = subseg_new (sec_name, 0);
      S_SET_SEGMENT (sec_symbol, sec);
      symbol_get_bfdsym (sec_symbol)->flags |= BSF_SECTION_SYM;
      bfd_vms_set_section_flags (stdoutput, sec, 0,
				 EGPS__V_OVR | EGPS__V_GBL | EGPS__V_NOMOD);
      record_alignment (sec, log_align);

      /* Reuse stab_string_size to store the size of the section.  */
      cur_size = seg_info (sec)->stabu.stab_string_size;
      if ((int) size > cur_size)
	{
	  char *pfrag
	    = frag_var (rs_fill, 1, 1, (relax_substateT)0, NULL,
			(valueT)size - (valueT)cur_size, NULL);
	  *pfrag = 0;
	  seg_info (sec)->stabu.stab_string_size = (int)size;
	}

      S_SET_SEGMENT (symbolP, sec);

      subseg_set (current_seg, current_subseg);
    }
  else
    {
      /* Regular form of the directive

	   .comm symbol, size, alignment

	 where the "common" semantics in on the symbol.
	 These symbols are assembled in the .bss section.  */

      char *pfrag;
      segT current_seg = now_seg;
      subsegT current_subseg = now_subseg;

      subseg_set (bss_section, 1);
      frag_align (log_align, 0, 0);
      record_alignment (bss_section, log_align);

      symbol_set_frag (symbolP, frag_now);
      pfrag = frag_var (rs_org, 1, 1, (relax_substateT)0, symbolP,
                        size, NULL);
      *pfrag = 0;

      S_SET_SEGMENT (symbolP, bss_section);

      subseg_set (current_seg, current_subseg);
    }
#endif

  if (S_GET_VALUE (symbolP))
    {
      if (S_GET_VALUE (symbolP) != (valueT) size)
        as_bad (_("Length of .comm \"%s\" is already %ld. Not changed to %ld."),
                S_GET_NAME (symbolP),
                (long) S_GET_VALUE (symbolP),
                (long) size);
    }
  else
    {
#ifndef OBJ_EVAX
      S_SET_VALUE (symbolP, (valueT) size);
#endif
      S_SET_EXTERNAL (symbolP);
    }

#ifndef OBJ_EVAX
  know (symbol_get_frag (symbolP) == &zero_address_frag);
#endif
  demand_empty_rest_of_line ();
}

#endif /* ! OBJ_ELF */

#ifdef OBJ_ECOFF

/* Handle the .rdata pseudo-op.  This is like the usual one, but it
   clears alpha_insn_label and restores auto alignment.  */

static void
s_alpha_rdata (int ignore ATTRIBUTE_UNUSED)
{
  get_absolute_expression ();
  subseg_new (".rdata", 0);
  demand_empty_rest_of_line ();
  alpha_insn_label = NULL;
  alpha_auto_align_on = 1;
  alpha_current_align = 0;
}

#endif

#ifdef OBJ_ECOFF

/* Handle the .sdata pseudo-op.  This is like the usual one, but it
   clears alpha_insn_label and restores auto alignment.  */

static void
s_alpha_sdata (int ignore ATTRIBUTE_UNUSED)
{
  get_absolute_expression ();
  subseg_new (".sdata", 0);
  demand_empty_rest_of_line ();
  alpha_insn_label = NULL;
  alpha_auto_align_on = 1;
  alpha_current_align = 0;
}
#endif

#ifdef OBJ_ELF
struct alpha_elf_frame_data
{
  symbolS *func_sym;
  symbolS *func_end_sym;
  symbolS *prologue_sym;
  unsigned int mask;
  unsigned int fmask;
  int fp_regno;
  int ra_regno;
  offsetT frame_size;
  offsetT mask_offset;
  offsetT fmask_offset;

  struct alpha_elf_frame_data *next;
};

static struct alpha_elf_frame_data *all_frame_data;
static struct alpha_elf_frame_data **plast_frame_data = &all_frame_data;
static struct alpha_elf_frame_data *cur_frame_data;

extern int all_cfi_sections;

/* Handle the .section pseudo-op.  This is like the usual one, but it
   clears alpha_insn_label and restores auto alignment.  */

static void
s_alpha_section (int ignore ATTRIBUTE_UNUSED)
{
  obj_elf_section (ignore);

  alpha_insn_label = NULL;
  alpha_auto_align_on = 1;
  alpha_current_align = 0;
}

static void
s_alpha_ent (int dummy ATTRIBUTE_UNUSED)
{
  if (ECOFF_DEBUGGING)
    ecoff_directive_ent (0);
  else
    {
      char *name, name_end;

      name_end = get_symbol_name (&name);
      /* CFI_EMIT_eh_frame is the default.  */
      all_cfi_sections = CFI_EMIT_eh_frame;

      if (! is_name_beginner (*name))
	{
	  as_warn (_(".ent directive has no name"));
	  (void) restore_line_pointer (name_end);
	}
      else
	{
	  symbolS *sym;

	  if (cur_frame_data)
	    as_warn (_("nested .ent directives"));

	  sym = symbol_find_or_make (name);
	  symbol_get_bfdsym (sym)->flags |= BSF_FUNCTION;

	  cur_frame_data = XCNEW (struct alpha_elf_frame_data);
	  cur_frame_data->func_sym = sym;

	  /* Provide sensible defaults.  */
	  cur_frame_data->fp_regno = 30;	/* sp */
	  cur_frame_data->ra_regno = 26;	/* ra */

	  *plast_frame_data = cur_frame_data;
	  plast_frame_data = &cur_frame_data->next;

	  /* The .ent directive is sometimes followed by a number.  Not sure
	     what it really means, but ignore it.  */
	  *input_line_pointer = name_end;
	  SKIP_WHITESPACE_AFTER_NAME ();
	  if (*input_line_pointer == ',')
	    {
	      input_line_pointer++;
	      SKIP_WHITESPACE ();
	    }
	  if (ISDIGIT (*input_line_pointer) || *input_line_pointer == '-')
	    (void) get_absolute_expression ();
	}
      demand_empty_rest_of_line ();
    }
}

static void
s_alpha_end (int dummy ATTRIBUTE_UNUSED)
{
  if (ECOFF_DEBUGGING)
    ecoff_directive_end (0);
  else
    {
      char *name, name_end;

      name_end = get_symbol_name (&name);

      if (! is_name_beginner (*name))
	{
	  as_warn (_(".end directive has no name"));
	}
      else
	{
	  symbolS *sym;

	  sym = symbol_find (name);
	  if (!cur_frame_data)
	    as_warn (_(".end directive without matching .ent"));
	  else if (sym != cur_frame_data->func_sym)
	    as_warn (_(".end directive names different symbol than .ent"));

	  /* Create an expression to calculate the size of the function.  */
	  if (sym && cur_frame_data)
	    {
	      OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (sym);
	      expressionS *exp = XNEW (expressionS);

	      obj->size = exp;
	      exp->X_op = O_subtract;
	      exp->X_add_symbol = symbol_temp_new_now ();
	      exp->X_op_symbol = sym;
	      exp->X_add_number = 0;

	      cur_frame_data->func_end_sym = exp->X_add_symbol;
	    }

	  cur_frame_data = NULL;
	}

      (void) restore_line_pointer (name_end);
      demand_empty_rest_of_line ();
    }
}

static void
s_alpha_mask (int fp)
{
  if (ECOFF_DEBUGGING)
    {
      if (fp)
	ecoff_directive_fmask (0);
      else
	ecoff_directive_mask (0);
    }
  else
    {
      long val;
      offsetT offset;

      if (!cur_frame_data)
	{
	  if (fp)
	    as_warn (_(".fmask outside of .ent"));
	  else
	    as_warn (_(".mask outside of .ent"));
	  discard_rest_of_line ();
	  return;
	}

      if (get_absolute_expression_and_terminator (&val) != ',')
	{
	  if (fp)
	    as_warn (_("bad .fmask directive"));
	  else
	    as_warn (_("bad .mask directive"));
	  --input_line_pointer;
	  discard_rest_of_line ();
	  return;
	}

      offset = get_absolute_expression ();
      demand_empty_rest_of_line ();

      if (fp)
	{
	  cur_frame_data->fmask = val;
          cur_frame_data->fmask_offset = offset;
	}
      else
	{
	  cur_frame_data->mask = val;
	  cur_frame_data->mask_offset = offset;
	}
    }
}

static void
s_alpha_frame (int dummy ATTRIBUTE_UNUSED)
{
  if (ECOFF_DEBUGGING)
    ecoff_directive_frame (0);
  else
    {
      long val;

      if (!cur_frame_data)
	{
	  as_warn (_(".frame outside of .ent"));
	  discard_rest_of_line ();
	  return;
	}

      cur_frame_data->fp_regno = tc_get_register (1);

      SKIP_WHITESPACE ();
      if (*input_line_pointer++ != ','
	  || get_absolute_expression_and_terminator (&val) != ',')
	{
	  as_warn (_("bad .frame directive"));
	  --input_line_pointer;
	  discard_rest_of_line ();
	  return;
	}
      cur_frame_data->frame_size = val;

      cur_frame_data->ra_regno = tc_get_register (0);

      /* Next comes the "offset of saved $a0 from $sp".  In gcc terms
	 this is current_function_pretend_args_size.  There's no place
	 to put this value, so ignore it.  */
      s_ignore (42);
    }
}

static void
s_alpha_prologue (int ignore ATTRIBUTE_UNUSED)
{
  symbolS *sym;
  int arg;

  arg = get_absolute_expression ();
  demand_empty_rest_of_line ();
  alpha_prologue_label = symbol_new (FAKE_LABEL_NAME, now_seg, frag_now,
				     frag_now_fix ());

  if (ECOFF_DEBUGGING)
    sym = ecoff_get_cur_proc_sym ();
  else
    sym = cur_frame_data ? cur_frame_data->func_sym : NULL;

  if (sym == NULL)
    {
      as_bad (_(".prologue directive without a preceding .ent directive"));
      return;
    }

  switch (arg)
    {
    case 0: /* No PV required.  */
      S_SET_OTHER (sym, STO_ALPHA_NOPV
		   | (S_GET_OTHER (sym) & ~STO_ALPHA_STD_GPLOAD));
      break;
    case 1: /* Std GP load.  */
      S_SET_OTHER (sym, STO_ALPHA_STD_GPLOAD
		   | (S_GET_OTHER (sym) & ~STO_ALPHA_STD_GPLOAD));
      break;
    case 2: /* Non-std use of PV.  */
      break;

    default:
      as_bad (_("Invalid argument %d to .prologue."), arg);
      break;
    }

  if (cur_frame_data)
    cur_frame_data->prologue_sym = symbol_temp_new_now ();
}

static char *first_file_directive;

static void
s_alpha_file (int ignore ATTRIBUTE_UNUSED)
{
  /* Save the first .file directive we see, so that we can change our
     minds about whether ecoff debugging should or shouldn't be enabled.  */
  if (alpha_flag_mdebug < 0 && ! first_file_directive)
    {
      char *start = input_line_pointer;
      size_t len;

      discard_rest_of_line ();

      len = input_line_pointer - start;
      first_file_directive = xmemdup0 (start, len);

      input_line_pointer = start;
    }

  if (ECOFF_DEBUGGING)
    ecoff_directive_file (0);
  else
    dwarf2_directive_file (0);
}

static void
s_alpha_loc (int ignore ATTRIBUTE_UNUSED)
{
  if (ECOFF_DEBUGGING)
    ecoff_directive_loc (0);
  else
    dwarf2_directive_loc (0);
}

static void
s_alpha_stab (int n)
{
  /* If we've been undecided about mdebug, make up our minds in favour.  */
  if (alpha_flag_mdebug < 0)
    {
      segT sec = subseg_new (".mdebug", 0);
      bfd_set_section_flags (sec, SEC_HAS_CONTENTS | SEC_READONLY);
      bfd_set_section_alignment (sec, 3);

      ecoff_read_begin_hook ();

      if (first_file_directive)
	{
	  char *save_ilp = input_line_pointer;
	  input_line_pointer = first_file_directive;
	  ecoff_directive_file (0);
	  input_line_pointer = save_ilp;
	  free (first_file_directive);
	}

      alpha_flag_mdebug = 1;
    }
  s_stab (n);
}

static void
s_alpha_coff_wrapper (int which)
{
  static void (* const fns[]) (int) = {
    ecoff_directive_begin,
    ecoff_directive_bend,
    ecoff_directive_def,
    ecoff_directive_dim,
    ecoff_directive_endef,
    ecoff_directive_scl,
    ecoff_directive_tag,
    ecoff_directive_val,
  };

  gas_assert (which >= 0 && which < (int) (sizeof (fns)/sizeof (*fns)));

  if (ECOFF_DEBUGGING)
    (*fns[which]) (0);
  else
    {
      as_bad (_("ECOFF debugging is disabled."));
      ignore_rest_of_line ();
    }
}

/* Called at the end of assembly.  Here we emit unwind info for frames
   unless the compiler has done it for us.  */

void
alpha_elf_md_finish (void)
{
  struct alpha_elf_frame_data *p;

  if (cur_frame_data)
    as_warn (_(".ent directive without matching .end"));

  /* If someone has generated the unwind info themselves, great.  */
  if (bfd_get_section_by_name (stdoutput, ".eh_frame") != NULL)
    return;

  /* ??? In theory we could look for functions for which we have
     generated unwind info via CFI directives, and those we have not.
     Those we have not could still get their unwind info from here.
     For now, do nothing if we've seen any CFI directives.  Note that
     the above test will not trigger, as we've not emitted data yet.  */
  if (all_fde_data != NULL)
    return;

  /* Generate .eh_frame data for the unwind directives specified.  */
  for (p = all_frame_data; p ; p = p->next)
    if (p->prologue_sym)
      {
	/* Create a temporary symbol at the same location as our
	   function symbol.  This prevents problems with globals.  */
	cfi_new_fde (symbol_temp_new (S_GET_SEGMENT (p->func_sym),
				      symbol_get_frag (p->func_sym),
				      S_GET_VALUE (p->func_sym)));

	cfi_set_sections ();
	cfi_set_return_column (p->ra_regno);
	cfi_add_CFA_def_cfa_register (30);
	if (p->fp_regno != 30 || p->mask || p->fmask || p->frame_size)
	  {
	    unsigned int mask;
	    offsetT offset;

	    cfi_add_advance_loc (p->prologue_sym);

	    if (p->fp_regno != 30)
	      if (p->frame_size != 0)
		cfi_add_CFA_def_cfa (p->fp_regno, p->frame_size);
	      else
		cfi_add_CFA_def_cfa_register (p->fp_regno);
	    else if (p->frame_size != 0)
	      cfi_add_CFA_def_cfa_offset (p->frame_size);

	    mask = p->mask;
	    offset = p->mask_offset;

	    /* Recall that $26 is special-cased and stored first.  */
	    if ((mask >> 26) & 1)
	      {
	        cfi_add_CFA_offset (26, offset);
		offset += 8;
		mask &= ~(1 << 26);
	      }
	    while (mask)
	      {
		unsigned int i;
		i = mask & -mask;
		mask ^= i;
		i = ffs (i) - 1;

		cfi_add_CFA_offset (i, offset);
		offset += 8;
	      }

	    mask = p->fmask;
	    offset = p->fmask_offset;
	    while (mask)
	      {
		unsigned int i;
		i = mask & -mask;
		mask ^= i;
		i = ffs (i) - 1;

		cfi_add_CFA_offset (i + 32, offset);
		offset += 8;
	      }
	  }

	cfi_end_fde (p->func_end_sym);
      }
}

static void
s_alpha_usepv (int unused ATTRIBUTE_UNUSED)
{
  char *name, name_end;
  char *which, which_end;
  symbolS *sym;
  int other;

  name_end = get_symbol_name (&name);

  if (! is_name_beginner (*name))
    {
      as_bad (_(".usepv directive has no name"));
      (void) restore_line_pointer (name_end);
      ignore_rest_of_line ();
      return;
    }

  sym = symbol_find_or_make (name);
  name_end = restore_line_pointer (name_end);
  if (! is_end_of_line[(unsigned char) name_end])
    input_line_pointer++;

  if (name_end != ',')
    {
      as_bad (_(".usepv directive has no type"));
      ignore_rest_of_line ();
      return;
    }

  SKIP_WHITESPACE ();

  which_end = get_symbol_name (&which);

  if (strcmp (which, "no") == 0)
    other = STO_ALPHA_NOPV;
  else if (strcmp (which, "std") == 0)
    other = STO_ALPHA_STD_GPLOAD;
  else
    {
      as_bad (_("unknown argument for .usepv"));
      other = 0;
    }

  (void) restore_line_pointer (which_end);
  demand_empty_rest_of_line ();

  S_SET_OTHER (sym, other | (S_GET_OTHER (sym) & ~STO_ALPHA_STD_GPLOAD));
}
#endif /* OBJ_ELF */

/* Standard calling conventions leaves the CFA at $30 on entry.  */

void
alpha_cfi_frame_initial_instructions (void)
{
  cfi_add_CFA_def_cfa_register (30);
}

#ifdef OBJ_EVAX

/* Get name of section.  */
static const char *
s_alpha_section_name (void)
{
  char *name;

  SKIP_WHITESPACE ();
  if (*input_line_pointer == '"')
    {
      int dummy;

      name = demand_copy_C_string (&dummy);
      if (name == NULL)
	{
	  ignore_rest_of_line ();
	  return NULL;
	}
    }
  else
    {
      char *end = input_line_pointer;

      while (0 == strchr ("\n\t,; ", *end))
	end++;
      if (end == input_line_pointer)
	{
	  as_warn (_("missing name"));
	  ignore_rest_of_line ();
	  return NULL;
	}

      name = xmemdup0 (input_line_pointer, end - input_line_pointer);
      input_line_pointer = end;
    }
  SKIP_WHITESPACE ();
  return name;
}

/* Put clear/set flags in one flagword.  The LSBs are flags to be set,
   the MSBs are the flags to be cleared.  */

#define EGPS__V_NO_SHIFT 16
#define EGPS__V_MASK	 0xffff

/* Parse one VMS section flag.  */

static flagword
s_alpha_section_word (char *str, size_t len)
{
  int no = 0;
  flagword flag = 0;

  if (len == 5 && startswith (str, "NO"))
    {
      no = 1;
      str += 2;
      len -= 2;
    }

  if (len == 3)
    {
      if (startswith (str, "PIC"))
	flag = EGPS__V_PIC;
      else if (startswith (str, "LIB"))
	flag = EGPS__V_LIB;
      else if (startswith (str, "OVR"))
	flag = EGPS__V_OVR;
      else if (startswith (str, "REL"))
	flag = EGPS__V_REL;
      else if (startswith (str, "GBL"))
	flag = EGPS__V_GBL;
      else if (startswith (str, "SHR"))
	flag = EGPS__V_SHR;
      else if (startswith (str, "EXE"))
	flag = EGPS__V_EXE;
      else if (startswith (str, "WRT"))
	flag = EGPS__V_WRT;
      else if (startswith (str, "VEC"))
	flag = EGPS__V_VEC;
      else if (startswith (str, "MOD"))
	{
	  flag = no ? EGPS__V_NOMOD : EGPS__V_NOMOD << EGPS__V_NO_SHIFT;
	  no = 0;
	}
      else if (startswith (str, "COM"))
	flag = EGPS__V_COM;
    }

  if (flag == 0)
    {
      char c = str[len];
      str[len] = 0;
      as_warn (_("unknown section attribute %s"), str);
      str[len] = c;
      return 0;
    }

  if (no)
    return flag << EGPS__V_NO_SHIFT;
  else
    return flag;
}

/* Handle the section specific pseudo-op.  */

#define EVAX_SECTION_COUNT 5

static const char *section_name[EVAX_SECTION_COUNT + 1] =
  { "NULL", ".rdata", ".comm", ".link", ".ctors", ".dtors" };

static void
s_alpha_section (int secid)
{
  const char *name;
  char *beg;
  segT sec;
  flagword vms_flags = 0;
  symbolS *symbol;

  if (secid == 0)
    {
      name = s_alpha_section_name ();
      if (name == NULL)
        return;
      sec = subseg_new (name, 0);
      if (*input_line_pointer == ',')
        {
          /* Skip the comma.  */
          ++input_line_pointer;
          SKIP_WHITESPACE ();

     	  do
     	    {
     	      char c;

     	      SKIP_WHITESPACE ();
     	      c = get_symbol_name (&beg);
     	      *input_line_pointer = c;

     	      vms_flags |= s_alpha_section_word (beg, input_line_pointer - beg);

     	      SKIP_WHITESPACE_AFTER_NAME ();
     	    }
     	  while (*input_line_pointer++ == ',');

     	  --input_line_pointer;
        }

	symbol = symbol_find_or_make (name);
	S_SET_SEGMENT (symbol, sec);
	symbol_get_bfdsym (symbol)->flags |= BSF_SECTION_SYM;
        bfd_vms_set_section_flags
          (stdoutput, sec,
           (vms_flags >> EGPS__V_NO_SHIFT) & EGPS__V_MASK,
           vms_flags & EGPS__V_MASK);
    }
  else
    {
      get_absolute_expression ();
      subseg_new (section_name[secid], 0);
    }

  demand_empty_rest_of_line ();
  alpha_insn_label = NULL;
  alpha_auto_align_on = 1;
  alpha_current_align = 0;
}

static void
s_alpha_literals (int ignore ATTRIBUTE_UNUSED)
{
  subseg_new (".literals", 0);
  demand_empty_rest_of_line ();
  alpha_insn_label = NULL;
  alpha_auto_align_on = 1;
  alpha_current_align = 0;
}

/* Parse .ent directives.  */

static void
s_alpha_ent (int ignore ATTRIBUTE_UNUSED)
{
  symbolS *symbol;
  expressionS symexpr;

  if (alpha_evax_proc != NULL)
    as_bad (_("previous .ent not closed by a .end"));

  alpha_evax_proc = &alpha_evax_proc_data;

  alpha_evax_proc->pdsckind = 0;
  alpha_evax_proc->framereg = -1;
  alpha_evax_proc->framesize = 0;
  alpha_evax_proc->rsa_offset = 0;
  alpha_evax_proc->ra_save = AXP_REG_RA;
  alpha_evax_proc->fp_save = -1;
  alpha_evax_proc->imask = 0;
  alpha_evax_proc->fmask = 0;
  alpha_evax_proc->prologue = 0;
  alpha_evax_proc->type = 0;
  alpha_evax_proc->handler = 0;
  alpha_evax_proc->handler_data = 0;

  expression (&symexpr);

  if (symexpr.X_op != O_symbol)
    {
      as_fatal (_(".ent directive has no symbol"));
      demand_empty_rest_of_line ();
      return;
    }

  symbol = make_expr_symbol (&symexpr);
  symbol_get_bfdsym (symbol)->flags |= BSF_FUNCTION;
  alpha_evax_proc->symbol = symbol;

  demand_empty_rest_of_line ();
}

static void
s_alpha_handler (int is_data)
{
  if (is_data)
    alpha_evax_proc->handler_data = get_absolute_expression ();
  else
    {
      char *name, name_end;

      name_end = get_symbol_name (&name);

      if (! is_name_beginner (*name))
	{
	  as_warn (_(".handler directive has no name"));
	}
      else
	{
	  symbolS *sym;

	  sym = symbol_find_or_make (name);
	  symbol_get_bfdsym (sym)->flags |= BSF_FUNCTION;
	  alpha_evax_proc->handler = sym;
	}

      (void) restore_line_pointer (name_end);
    }

  demand_empty_rest_of_line ();
}

/* Parse .frame <framreg>,<framesize>,RA,<rsa_offset> directives.  */

static void
s_alpha_frame (int ignore ATTRIBUTE_UNUSED)
{
  long val;
  int ra;

  alpha_evax_proc->framereg = tc_get_register (1);

  SKIP_WHITESPACE ();
  if (*input_line_pointer++ != ','
      || get_absolute_expression_and_terminator (&val) != ',')
    {
      as_warn (_("Bad .frame directive 1./2. param"));
      --input_line_pointer;
      demand_empty_rest_of_line ();
      return;
    }

  alpha_evax_proc->framesize = val;

  ra = tc_get_register (1);
  if (ra != AXP_REG_RA)
    as_warn (_("Bad RA (%d) register for .frame"), ra);

  SKIP_WHITESPACE ();
  if (*input_line_pointer++ != ',')
    {
      as_warn (_("Bad .frame directive 3./4. param"));
      --input_line_pointer;
      demand_empty_rest_of_line ();
      return;
    }
  alpha_evax_proc->rsa_offset = get_absolute_expression ();
}

/* Parse .prologue.  */

static void
s_alpha_prologue (int ignore ATTRIBUTE_UNUSED)
{
  demand_empty_rest_of_line ();
  alpha_prologue_label = symbol_new (FAKE_LABEL_NAME, now_seg, frag_now,
				     frag_now_fix ());
}

/* Parse .pdesc <entry_name>,{null|stack|reg}
   Insert a procedure descriptor.  */

static void
s_alpha_pdesc (int ignore ATTRIBUTE_UNUSED)
{
  char *name;
  char name_end;
  char *p;
  expressionS exp;
  symbolS *entry_sym;
  const char *entry_sym_name;
  const char *pdesc_sym_name;
  fixS *fixp;
  size_t len;

  if (now_seg != alpha_link_section)
    {
      as_bad (_(".pdesc directive not in link (.link) section"));
      return;
    }

  expression (&exp);
  if (exp.X_op != O_symbol)
    {
      as_bad (_(".pdesc directive has no entry symbol"));
      return;
    }

  entry_sym = make_expr_symbol (&exp);
  entry_sym_name = S_GET_NAME (entry_sym);

  /* Strip "..en".  */
  len = strlen (entry_sym_name);
  if (len < 4 || strcmp (entry_sym_name + len - 4, "..en") != 0)
    {
      as_bad (_(".pdesc has a bad entry symbol"));
      return;
    }
  len -= 4;
  pdesc_sym_name = S_GET_NAME (alpha_evax_proc->symbol);

  if (!alpha_evax_proc
      || !S_IS_DEFINED (alpha_evax_proc->symbol)
      || strlen (pdesc_sym_name) != len
      || memcmp (entry_sym_name, pdesc_sym_name, len) != 0)
    {
      as_fatal (_(".pdesc doesn't match with last .ent"));
      return;
    }

  /* Define pdesc symbol.  */
  symbol_set_value_now (alpha_evax_proc->symbol);

  /* Save bfd symbol of proc entry in function symbol.  */
  ((struct evax_private_udata_struct *)
     symbol_get_bfdsym (alpha_evax_proc->symbol)->udata.p)->enbsym
       = symbol_get_bfdsym (entry_sym);

  SKIP_WHITESPACE ();
  if (*input_line_pointer++ != ',')
    {
      as_warn (_("No comma after .pdesc <entryname>"));
      demand_empty_rest_of_line ();
      return;
    }

  SKIP_WHITESPACE ();
  name_end = get_symbol_name (&name);

  if (startswith (name, "stack"))
    alpha_evax_proc->pdsckind = PDSC_S_K_KIND_FP_STACK;

  else if (startswith (name, "reg"))
    alpha_evax_proc->pdsckind = PDSC_S_K_KIND_FP_REGISTER;

  else if (startswith (name, "null"))
    alpha_evax_proc->pdsckind = PDSC_S_K_KIND_NULL;

  else
    {
      (void) restore_line_pointer (name_end);
      as_fatal (_("unknown procedure kind"));
      demand_empty_rest_of_line ();
      return;
    }

  (void) restore_line_pointer (name_end);
  demand_empty_rest_of_line ();

#ifdef md_flush_pending_output
  md_flush_pending_output ();
#endif

  frag_align (3, 0, 0);
  p = frag_more (16);
  fixp = fix_new (frag_now, p - frag_now->fr_literal, 8, 0, 0, 0, 0);
  fixp->fx_done = 1;

  *p = alpha_evax_proc->pdsckind
    | ((alpha_evax_proc->framereg == 29) ? PDSC_S_M_BASE_REG_IS_FP : 0)
    | ((alpha_evax_proc->handler) ? PDSC_S_M_HANDLER_VALID : 0)
    | ((alpha_evax_proc->handler_data) ? PDSC_S_M_HANDLER_DATA_VALID : 0);
  *(p + 1) = PDSC_S_M_NATIVE | PDSC_S_M_NO_JACKET;

  switch (alpha_evax_proc->pdsckind)
    {
    case PDSC_S_K_KIND_NULL:
      *(p + 2) = 0;
      *(p + 3) = 0;
      break;
    case PDSC_S_K_KIND_FP_REGISTER:
      *(p + 2) = alpha_evax_proc->fp_save;
      *(p + 3) = alpha_evax_proc->ra_save;
      break;
    case PDSC_S_K_KIND_FP_STACK:
      md_number_to_chars (p + 2, (valueT) alpha_evax_proc->rsa_offset, 2);
      break;
    default:		/* impossible */
      break;
    }

  *(p + 4) = 0;
  *(p + 5) = alpha_evax_proc->type & 0x0f;

  /* Signature offset.  */
  md_number_to_chars (p + 6, (valueT) 0, 2);

  fix_new_exp (frag_now, p - frag_now->fr_literal + 8,
               8, &exp, 0, BFD_RELOC_64);

  if (alpha_evax_proc->pdsckind == PDSC_S_K_KIND_NULL)
    return;

  /* pdesc+16: Size.  */
  p = frag_more (6);
  md_number_to_chars (p, (valueT) alpha_evax_proc->framesize, 4);
  md_number_to_chars (p + 4, (valueT) 0, 2);

  /* Entry length.  */
  exp.X_op = O_subtract;
  exp.X_add_symbol = alpha_prologue_label;
  exp.X_op_symbol = entry_sym;
  emit_expr (&exp, 2);

  if (alpha_evax_proc->pdsckind == PDSC_S_K_KIND_FP_REGISTER)
    return;

  /* pdesc+24: register masks.  */
  p = frag_more (8);
  md_number_to_chars (p, alpha_evax_proc->imask, 4);
  md_number_to_chars (p + 4, alpha_evax_proc->fmask, 4);

  if (alpha_evax_proc->handler)
    {
      p = frag_more (8);
      fixp = fix_new (frag_now, p - frag_now->fr_literal, 8,
	              alpha_evax_proc->handler, 0, 0, BFD_RELOC_64);
    }

  if (alpha_evax_proc->handler_data)
    {
      p = frag_more (8);
      md_number_to_chars (p, alpha_evax_proc->handler_data, 8);
    }
}

/* Support for crash debug on vms.  */

static void
s_alpha_name (int ignore ATTRIBUTE_UNUSED)
{
  char *p;
  expressionS exp;

  if (now_seg != alpha_link_section)
    {
      as_bad (_(".name directive not in link (.link) section"));
      demand_empty_rest_of_line ();
      return;
    }

  expression (&exp);
  if (exp.X_op != O_symbol)
    {
      as_warn (_(".name directive has no symbol"));
      demand_empty_rest_of_line ();
      return;
    }

  demand_empty_rest_of_line ();

#ifdef md_flush_pending_output
  md_flush_pending_output ();
#endif

  frag_align (3, 0, 0);
  p = frag_more (8);

  fix_new_exp (frag_now, p - frag_now->fr_literal, 8, &exp, 0, BFD_RELOC_64);
}

/* Parse .linkage <symbol>.
   Create a linkage pair relocation.  */

static void
s_alpha_linkage (int ignore ATTRIBUTE_UNUSED)
{
  expressionS exp;
  char *p;
  fixS *fixp;

#ifdef md_flush_pending_output
  md_flush_pending_output ();
#endif

  expression (&exp);
  if (exp.X_op != O_symbol)
    {
      as_fatal (_("No symbol after .linkage"));
    }
  else
    {
      struct alpha_linkage_fixups *linkage_fixup;

      p = frag_more (LKP_S_K_SIZE);
      memset (p, 0, LKP_S_K_SIZE);
      fixp = fix_new_exp
	(frag_now, p - frag_now->fr_literal, LKP_S_K_SIZE, &exp, 0,
	 BFD_RELOC_ALPHA_LINKAGE);

      if (alpha_insn_label == NULL)
	alpha_insn_label = symbol_new (FAKE_LABEL_NAME, now_seg, frag_now,
				       frag_now_fix ());

      /* Create a linkage element.  */
      linkage_fixup = XNEW (struct alpha_linkage_fixups);
      linkage_fixup->fixp = fixp;
      linkage_fixup->next = NULL;
      linkage_fixup->label = alpha_insn_label;

      /* Append it to the list.  */
      if (alpha_linkage_fixup_root == NULL)
        alpha_linkage_fixup_root = linkage_fixup;
      else
        alpha_linkage_fixup_tail->next = linkage_fixup;
      alpha_linkage_fixup_tail = linkage_fixup;
    }
  demand_empty_rest_of_line ();
}

/* Parse .code_address <symbol>.
   Create a code address relocation.  */

static void
s_alpha_code_address (int ignore ATTRIBUTE_UNUSED)
{
  expressionS exp;
  char *p;

#ifdef md_flush_pending_output
  md_flush_pending_output ();
#endif

  expression (&exp);
  if (exp.X_op != O_symbol)
    as_fatal (_("No symbol after .code_address"));
  else
    {
      p = frag_more (8);
      memset (p, 0, 8);
      fix_new_exp (frag_now, p - frag_now->fr_literal, 8, &exp, 0,\
		   BFD_RELOC_ALPHA_CODEADDR);
    }
  demand_empty_rest_of_line ();
}

static void
s_alpha_fp_save (int ignore ATTRIBUTE_UNUSED)
{
  alpha_evax_proc->fp_save = tc_get_register (1);

  demand_empty_rest_of_line ();
}

static void
s_alpha_mask (int ignore ATTRIBUTE_UNUSED)
{
  long val;

  if (get_absolute_expression_and_terminator (&val) != ',')
    {
      as_warn (_("Bad .mask directive"));
      --input_line_pointer;
    }
  else
    {
      alpha_evax_proc->imask = val;
      (void) get_absolute_expression ();
    }
  demand_empty_rest_of_line ();
}

static void
s_alpha_fmask (int ignore ATTRIBUTE_UNUSED)
{
  long val;

  if (get_absolute_expression_and_terminator (&val) != ',')
    {
      as_warn (_("Bad .fmask directive"));
      --input_line_pointer;
    }
  else
    {
      alpha_evax_proc->fmask = val;
      (void) get_absolute_expression ();
    }
  demand_empty_rest_of_line ();
}

static void
s_alpha_end (int ignore ATTRIBUTE_UNUSED)
{
  char *name;
  char c;

  c = get_symbol_name (&name);
  (void) restore_line_pointer (c);
  demand_empty_rest_of_line ();
  alpha_evax_proc = NULL;
}

static void
s_alpha_file (int ignore ATTRIBUTE_UNUSED)
{
  symbolS *s;
  int length;
  static char case_hack[32];

  sprintf (case_hack, "<CASE:%01d%01d>",
	   alpha_flag_hash_long_names, alpha_flag_show_after_trunc);

  s = symbol_find_or_make (case_hack);
  symbol_get_bfdsym (s)->flags |= BSF_FILE;

  get_absolute_expression ();
  s = symbol_find_or_make (demand_copy_string (&length));
  symbol_get_bfdsym (s)->flags |= BSF_FILE;
  demand_empty_rest_of_line ();
}
#endif /* OBJ_EVAX  */

/* Handle the .gprel32 pseudo op.  */

static void
s_alpha_gprel32 (int ignore ATTRIBUTE_UNUSED)
{
  expressionS e;
  char *p;

  SKIP_WHITESPACE ();
  expression (&e);

#ifdef OBJ_ELF
  switch (e.X_op)
    {
    case O_constant:
      e.X_add_symbol = section_symbol (absolute_section);
      e.X_op = O_symbol;
      /* FALLTHRU */
    case O_symbol:
      break;
    default:
      abort ();
    }
#else
#ifdef OBJ_ECOFF
  switch (e.X_op)
    {
    case O_constant:
      e.X_add_symbol = section_symbol (absolute_section);
      /* fall through */
    case O_symbol:
      e.X_op = O_subtract;
      e.X_op_symbol = alpha_gp_symbol;
      break;
    default:
      abort ();
    }
#endif
#endif

  if (alpha_auto_align_on && alpha_current_align < 2)
    alpha_align (2, (char *) NULL, alpha_insn_label, 0);
  if (alpha_current_align > 2)
    alpha_current_align = 2;
  alpha_insn_label = NULL;

  p = frag_more (4);
  memset (p, 0, 4);
  fix_new_exp (frag_now, p - frag_now->fr_literal, 4,
	       &e, 0, BFD_RELOC_GPREL32);
}

/* Handle floating point allocation pseudo-ops.  This is like the
   generic version, but it makes sure the current label, if any, is
   correctly aligned.  */

static void
s_alpha_float_cons (int type)
{
  int log_size;

  switch (type)
    {
    default:
    case 'f':
    case 'F':
      log_size = 2;
      break;

    case 'd':
    case 'D':
    case 'G':
      log_size = 3;
      break;

    case 'x':
    case 'X':
    case 'p':
    case 'P':
      log_size = 4;
      break;
    }

  if (alpha_auto_align_on && alpha_current_align < log_size)
    alpha_align (log_size, (char *) NULL, alpha_insn_label, 0);
  if (alpha_current_align > log_size)
    alpha_current_align = log_size;
  alpha_insn_label = NULL;

  float_cons (type);
}

/* Handle the .proc pseudo op.  We don't really do much with it except
   parse it.  */

static void
s_alpha_proc (int is_static ATTRIBUTE_UNUSED)
{
  char *name;
  char c;
  char *p;
  symbolS *symbolP;
  int temp;

  /* Takes ".proc name,nargs".  */
  SKIP_WHITESPACE ();
  c = get_symbol_name (&name);
  p = input_line_pointer;
  symbolP = symbol_find_or_make (name);
  *p = c;
  SKIP_WHITESPACE_AFTER_NAME ();
  if (*input_line_pointer != ',')
    {
      *p = 0;
      as_warn (_("Expected comma after name \"%s\""), name);
      *p = c;
      temp = 0;
      ignore_rest_of_line ();
    }
  else
    {
      input_line_pointer++;
      temp = get_absolute_expression ();
    }
  /*  *symbol_get_obj (symbolP) = (signed char) temp; */
  (void) symbolP;
  as_warn (_("unhandled: .proc %s,%d"), name, temp);
  demand_empty_rest_of_line ();
}

/* Handle the .set pseudo op.  This is used to turn on and off most of
   the assembler features.  */

static void
s_alpha_set (int x ATTRIBUTE_UNUSED)
{
  char *name, ch, *s;
  int yesno = 1;

  SKIP_WHITESPACE ();

  ch = get_symbol_name (&name);
  s = name;
  if (s[0] == 'n' && s[1] == 'o')
    {
      yesno = 0;
      s += 2;
    }
  if (!strcmp ("reorder", s))
    /* ignore */ ;
  else if (!strcmp ("at", s))
    alpha_noat_on = !yesno;
  else if (!strcmp ("macro", s))
    alpha_macros_on = yesno;
  else if (!strcmp ("move", s))
    /* ignore */ ;
  else if (!strcmp ("volatile", s))
    /* ignore */ ;
  else
    as_warn (_("Tried to .set unrecognized mode `%s'"), name);

  (void) restore_line_pointer (ch);
  demand_empty_rest_of_line ();
}

/* Handle the .base pseudo op.  This changes the assembler's notion of
   the $gp register.  */

static void
s_alpha_base (int ignore ATTRIBUTE_UNUSED)
{
  SKIP_WHITESPACE ();

  if (*input_line_pointer == '$')
    {
      /* $rNN form.  */
      input_line_pointer++;
      if (*input_line_pointer == 'r')
	input_line_pointer++;
    }

  alpha_gp_register = get_absolute_expression ();
  if (alpha_gp_register < 0 || alpha_gp_register > 31)
    {
      alpha_gp_register = AXP_REG_GP;
      as_warn (_("Bad base register, using $%d."), alpha_gp_register);
    }

  demand_empty_rest_of_line ();
}

/* Handle the .align pseudo-op.  This aligns to a power of two.  It
   also adjusts any current instruction label.  We treat this the same
   way the MIPS port does: .align 0 turns off auto alignment.  */

static void
s_alpha_align (int ignore ATTRIBUTE_UNUSED)
{
  int align;
  char fill, *pfill;
  long max_alignment = 16;

  align = get_absolute_expression ();
  if (align > max_alignment)
    {
      align = max_alignment;
      as_bad (_("Alignment too large: %d. assumed"), align);
    }
  else if (align < 0)
    {
      as_warn (_("Alignment negative: 0 assumed"));
      align = 0;
    }

  if (*input_line_pointer == ',')
    {
      input_line_pointer++;
      fill = get_absolute_expression ();
      pfill = &fill;
    }
  else
    pfill = NULL;

  if (align != 0)
    {
      alpha_auto_align_on = 1;
      alpha_align (align, pfill, NULL, 1);
    }
  else
    {
      alpha_auto_align_on = 0;
    }
  alpha_insn_label = NULL;

  demand_empty_rest_of_line ();
}

/* Hook the normal string processor to reset known alignment.  */

static void
s_alpha_stringer (int terminate)
{
  alpha_current_align = 0;
  alpha_insn_label = NULL;
  stringer (8 + terminate);
}

/* Hook the normal space processing to reset known alignment.  */

static void
s_alpha_space (int ignore)
{
  alpha_current_align = 0;
  alpha_insn_label = NULL;
  s_space (ignore);
}

/* Hook into cons for auto-alignment.  */

void
alpha_cons_align (int size)
{
  int log_size;

  log_size = 0;
  while ((size >>= 1) != 0)
    ++log_size;

  if (alpha_auto_align_on && alpha_current_align < log_size)
    alpha_align (log_size, (char *) NULL, alpha_insn_label, 0);
  if (alpha_current_align > log_size)
    alpha_current_align = log_size;
  alpha_insn_label = NULL;
}

/* Here come the .uword, .ulong, and .uquad explicitly unaligned
   pseudos.  We just turn off auto-alignment and call down to cons.  */

static void
s_alpha_ucons (int bytes)
{
  int hold = alpha_auto_align_on;
  alpha_auto_align_on = 0;
  cons (bytes);
  alpha_auto_align_on = hold;
}

/* Switch the working cpu type.  */

static void
s_alpha_arch (int ignored ATTRIBUTE_UNUSED)
{
  char *name, ch;
  const struct cpu_type *p;

  SKIP_WHITESPACE ();

  ch = get_symbol_name (&name);

  for (p = cpu_types; p->name; ++p)
    if (strcmp (name, p->name) == 0)
      {
	alpha_target_name = p->name, alpha_target = p->flags;
	goto found;
      }
  as_warn (_("Unknown CPU identifier `%s'"), name);

 found:
  (void) restore_line_pointer (ch);
  demand_empty_rest_of_line ();
}

#ifdef DEBUG1
/* print token expression with alpha specific extension.  */

static void
alpha_print_token (FILE *f, const expressionS *exp)
{
  switch (exp->X_op)
    {
    case O_cpregister:
      putc (',', f);
      /* FALLTHRU */
    case O_pregister:
      putc ('(', f);
      {
	expressionS nexp = *exp;
	nexp.X_op = O_register;
	print_expr_1 (f, &nexp);
      }
      putc (')', f);
      break;
    default:
      print_expr_1 (f, exp);
      break;
    }
}
#endif

/* The target specific pseudo-ops which we support.  */

const pseudo_typeS md_pseudo_table[] =
{
#ifdef OBJ_ECOFF
  {"comm", s_alpha_comm, 0},	/* OSF1 compiler does this.  */
  {"rdata", s_alpha_rdata, 0},
#endif
  {"text", s_alpha_text, 0},
  {"data", s_alpha_data, 0},
#ifdef OBJ_ECOFF
  {"sdata", s_alpha_sdata, 0},
#endif
#ifdef OBJ_ELF
  {"section", s_alpha_section, 0},
  {"section.s", s_alpha_section, 0},
  {"sect", s_alpha_section, 0},
  {"sect.s", s_alpha_section, 0},
#endif
#ifdef OBJ_EVAX
  {"section", s_alpha_section, 0},
  {"literals", s_alpha_literals, 0},
  {"pdesc", s_alpha_pdesc, 0},
  {"name", s_alpha_name, 0},
  {"linkage", s_alpha_linkage, 0},
  {"code_address", s_alpha_code_address, 0},
  {"ent", s_alpha_ent, 0},
  {"frame", s_alpha_frame, 0},
  {"fp_save", s_alpha_fp_save, 0},
  {"mask", s_alpha_mask, 0},
  {"fmask", s_alpha_fmask, 0},
  {"end", s_alpha_end, 0},
  {"file", s_alpha_file, 0},
  {"rdata", s_alpha_section, 1},
  {"comm", s_alpha_comm, 0},
  {"link", s_alpha_section, 3},
  {"ctors", s_alpha_section, 4},
  {"dtors", s_alpha_section, 5},
  {"handler", s_alpha_handler, 0},
  {"handler_data", s_alpha_handler, 1},
#endif
#ifdef OBJ_ELF
  /* Frame related pseudos.  */
  {"ent", s_alpha_ent, 0},
  {"end", s_alpha_end, 0},
  {"mask", s_alpha_mask, 0},
  {"fmask", s_alpha_mask, 1},
  {"frame", s_alpha_frame, 0},
  {"prologue", s_alpha_prologue, 0},
  {"file", s_alpha_file, 5},
  {"loc", s_alpha_loc, 9},
  {"stabs", s_alpha_stab, 's'},
  {"stabn", s_alpha_stab, 'n'},
  {"usepv", s_alpha_usepv, 0},
  /* COFF debugging related pseudos.  */
  {"begin", s_alpha_coff_wrapper, 0},
  {"bend", s_alpha_coff_wrapper, 1},
  {"def", s_alpha_coff_wrapper, 2},
  {"dim", s_alpha_coff_wrapper, 3},
  {"endef", s_alpha_coff_wrapper, 4},
  {"scl", s_alpha_coff_wrapper, 5},
  {"tag", s_alpha_coff_wrapper, 6},
  {"val", s_alpha_coff_wrapper, 7},
#else
#ifdef OBJ_EVAX
  {"prologue", s_alpha_prologue, 0},
#else
  {"prologue", s_ignore, 0},
#endif
#endif
  {"gprel32", s_alpha_gprel32, 0},
  {"t_floating", s_alpha_float_cons, 'd'},
  {"s_floating", s_alpha_float_cons, 'f'},
  {"f_floating", s_alpha_float_cons, 'F'},
  {"g_floating", s_alpha_float_cons, 'G'},
  {"d_floating", s_alpha_float_cons, 'D'},

  {"proc", s_alpha_proc, 0},
  {"aproc", s_alpha_proc, 1},
  {"set", s_alpha_set, 0},
  {"reguse", s_ignore, 0},
  {"livereg", s_ignore, 0},
  {"base", s_alpha_base, 0},		/*??*/
  {"option", s_ignore, 0},
  {"aent", s_ignore, 0},
  {"ugen", s_ignore, 0},
  {"eflag", s_ignore, 0},

  {"align", s_alpha_align, 0},
  {"double", s_alpha_float_cons, 'd'},
  {"float", s_alpha_float_cons, 'f'},
  {"single", s_alpha_float_cons, 'f'},
  {"ascii", s_alpha_stringer, 0},
  {"asciz", s_alpha_stringer, 1},
  {"string", s_alpha_stringer, 1},
  {"space", s_alpha_space, 0},
  {"skip", s_alpha_space, 0},
  {"zero", s_alpha_space, 0},

/* Unaligned data pseudos.  */
  {"uword", s_alpha_ucons, 2},
  {"ulong", s_alpha_ucons, 4},
  {"uquad", s_alpha_ucons, 8},

#ifdef OBJ_ELF
/* Dwarf wants these versions of unaligned.  */
  {"2byte", s_alpha_ucons, 2},
  {"4byte", s_alpha_ucons, 4},
  {"8byte", s_alpha_ucons, 8},
#endif

/* We don't do any optimizing, so we can safely ignore these.  */
  {"noalias", s_ignore, 0},
  {"alias", s_ignore, 0},

  {"arch", s_alpha_arch, 0},

  {NULL, 0, 0},
};

#ifdef OBJ_ECOFF

/* @@@ GP selection voodoo.  All of this seems overly complicated and
   unnecessary; which is the primary reason it's for ECOFF only.  */

static inline void
maybe_set_gp (asection *sec)
{
  bfd_vma vma;

  if (!sec)
    return;
  vma = bfd_section_vma (sec);
  if (vma && vma < alpha_gp_value)
    alpha_gp_value = vma;
}

static void
select_gp_value (void)
{
  gas_assert (alpha_gp_value == 0);

  /* Get minus-one in whatever width...  */
  alpha_gp_value = 0;
  alpha_gp_value--;

  /* Select the smallest VMA of these existing sections.  */
  maybe_set_gp (alpha_lita_section);

/* @@ Will a simple 0x8000 work here?  If not, why not?  */
#define GP_ADJUSTMENT	(0x8000 - 0x10)

  alpha_gp_value += GP_ADJUSTMENT;

  S_SET_VALUE (alpha_gp_symbol, alpha_gp_value);

#ifdef DEBUG1
  printf (_("Chose GP value of %lx\n"), alpha_gp_value);
#endif
}
#endif /* OBJ_ECOFF */

#ifdef OBJ_ELF
/* Map 's' to SHF_ALPHA_GPREL.  */

bfd_vma
alpha_elf_section_letter (int letter, const char **ptr_msg)
{
  if (letter == 's')
    return SHF_ALPHA_GPREL;

  *ptr_msg = _("bad .section directive: want a,s,w,x,M,S,G,T in string");
  return -1;
}

/* Map SHF_ALPHA_GPREL to SEC_SMALL_DATA.  */

flagword
alpha_elf_section_flags (flagword flags, bfd_vma attr, int type ATTRIBUTE_UNUSED)
{
  if (attr & SHF_ALPHA_GPREL)
    flags |= SEC_SMALL_DATA;
  return flags;
}
#endif /* OBJ_ELF */

/* This is called from HANDLE_ALIGN in write.c.  Fill in the contents
   of an rs_align_code fragment.  */

void
alpha_handle_align (fragS *fragp)
{
  static unsigned char const unop[4] = { 0x00, 0x00, 0xfe, 0x2f };
  static unsigned char const nopunop[8] =
  {
    0x1f, 0x04, 0xff, 0x47,
    0x00, 0x00, 0xfe, 0x2f
  };

  int bytes, fix;
  char *p;

  if (fragp->fr_type != rs_align_code)
    return;

  bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
  p = fragp->fr_literal + fragp->fr_fix;
  fix = 0;

  if (bytes & 3)
    {
      fix = bytes & 3;
      memset (p, 0, fix);
      p += fix;
      bytes -= fix;
    }

  if (bytes & 4)
    {
      memcpy (p, unop, 4);
      p += 4;
      bytes -= 4;
      fix += 4;
    }

  memcpy (p, nopunop, 8);

  fragp->fr_fix += fix;
  fragp->fr_var = 8;
}

/* Public interface functions.  */

/* This function is called once, at assembler startup time.  It sets
   up all the tables, etc. that the MD part of the assembler will
   need, that can be determined before arguments are parsed.  */

void
md_begin (void)
{
  unsigned int i;

  /* Verify that X_op field is wide enough.  */
  {
    expressionS e;

    e.X_op = O_max;
    gas_assert (e.X_op == O_max);
  }

  /* Create the opcode hash table.  */
  alpha_opcode_hash = str_htab_create ();

  for (i = 0; i < alpha_num_opcodes;)
    {
      const char *name, *slash;

      name = alpha_opcodes[i].name;
      if (str_hash_insert (alpha_opcode_hash, name, &alpha_opcodes[i], 0))
	as_fatal (_("duplicate %s"), name);

      /* Some opcodes include modifiers of various sorts with a "/mod"
	 syntax, like the architecture manual suggests.  However, for
	 use with gcc at least, we also need access to those same opcodes
	 without the "/".  */

      if ((slash = strchr (name, '/')) != NULL)
	{
	  char *p = XNEWVEC (char, strlen (name));

	  memcpy (p, name, slash - name);
	  strcpy (p + (slash - name), slash + 1);

	  (void) str_hash_insert (alpha_opcode_hash, p, &alpha_opcodes[i], 0);
	  /* Ignore failures -- the opcode table does duplicate some
	     variants in different forms, like "hw_stq" and "hw_st/q".  */
	}

      while (++i < alpha_num_opcodes
	     && (alpha_opcodes[i].name == name
		 || !strcmp (alpha_opcodes[i].name, name)))
	continue;
    }

  /* Create the macro hash table.  */
  alpha_macro_hash = str_htab_create ();

  for (i = 0; i < alpha_num_macros;)
    {
      const char *name;

      name = alpha_macros[i].name;
      if (str_hash_insert (alpha_macro_hash, name, &alpha_macros[i], 0))
	as_fatal (_("duplicate %s"), name);

      while (++i < alpha_num_macros
	     && (alpha_macros[i].name == name
		 || !strcmp (alpha_macros[i].name, name)))
	continue;
    }

  /* Construct symbols for each of the registers.  */
  for (i = 0; i < 32; ++i)
    {
      char name[4];

      sprintf (name, "$%d", i);
      alpha_register_table[i] = symbol_create (name, reg_section,
					       &zero_address_frag, i);
    }

  for (; i < 64; ++i)
    {
      char name[5];

      sprintf (name, "$f%d", i - 32);
      alpha_register_table[i] = symbol_create (name, reg_section,
					       &zero_address_frag, i);
    }

  /* Create the special symbols and sections we'll be using.  */

  /* So .sbss will get used for tiny objects.  */
  bfd_set_gp_size (stdoutput, g_switch_value);

#ifdef OBJ_ECOFF
  create_literal_section (".lita", &alpha_lita_section, &alpha_lita_symbol);

  /* For handling the GP, create a symbol that won't be output in the
     symbol table.  We'll edit it out of relocs later.  */
  alpha_gp_symbol = symbol_create ("<GP value>", alpha_lita_section,
				   &zero_address_frag, 0x8000);
#endif

#ifdef OBJ_EVAX
  create_literal_section (".link", &alpha_link_section, &alpha_link_symbol);
#endif

#ifdef OBJ_ELF
  if (ECOFF_DEBUGGING)
    {
      segT sec = subseg_new (".mdebug", (subsegT) 0);
      bfd_set_section_flags (sec, SEC_HAS_CONTENTS | SEC_READONLY);
      bfd_set_section_alignment (sec, 3);
    }
#endif

  /* Create literal lookup hash table.  */
  alpha_literal_hash = str_htab_create ();

  subseg_set (text_section, 0);
}

/* The public interface to the instruction assembler.  */

void
md_assemble (char *str)
{
  /* Current maximum is 13.  */
  char opname[32];
  expressionS tok[MAX_INSN_ARGS];
  int ntok, trunclen;
  size_t opnamelen;

  /* Split off the opcode.  */
  opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_/46819");
  trunclen = (opnamelen < sizeof (opname) - 1
	      ? opnamelen
	      : sizeof (opname) - 1);
  memcpy (opname, str, trunclen);
  opname[trunclen] = '\0';

  /* Tokenize the rest of the line.  */
  if ((ntok = tokenize_arguments (str + opnamelen, tok, MAX_INSN_ARGS)) < 0)
    {
      if (ntok != TOKENIZE_ERROR_REPORT)
	as_bad (_("syntax error"));

      return;
    }

  /* Finish it off.  */
  assemble_tokens (opname, tok, ntok, alpha_macros_on);
}

/* Round up a section's size to the appropriate boundary.  */

valueT
md_section_align (segT seg, valueT size)
{
  int align = bfd_section_alignment (seg);
  valueT mask = ((valueT) 1 << align) - 1;

  return (size + mask) & ~mask;
}

/* Turn a string in input_line_pointer into a floating point constant
   of type TYPE, and store the appropriate bytes in *LITP.  The number
   of LITTLENUMS emitted is stored in *SIZEP.  An error message is
   returned, or NULL on OK.  */

const char *
md_atof (int type, char *litP, int *sizeP)
{
  extern const char *vax_md_atof (int, char *, int *);

  switch (type)
    {
      /* VAX floats.  */
    case 'G':
      /* vax_md_atof() doesn't like "G" for some reason.  */
      type = 'g';
      /* Fall through.  */
    case 'F':
    case 'D':
      return vax_md_atof (type, litP, sizeP);

    default:
      return ieee_md_atof (type, litP, sizeP, false);
    }
}

/* Take care of the target-specific command-line options.  */

int
md_parse_option (int c, const char *arg)
{
  switch (c)
    {
    case 'F':
      alpha_nofloats_on = 1;
      break;

    case OPTION_32ADDR:
      alpha_addr32_on = 1;
      break;

    case 'g':
      alpha_debug = 1;
      break;

    case 'G':
      g_switch_value = atoi (arg);
      break;

    case 'm':
      {
	const struct cpu_type *p;

	for (p = cpu_types; p->name; ++p)
	  if (strcmp (arg, p->name) == 0)
	    {
	      alpha_target_name = p->name, alpha_target = p->flags;
	      goto found;
	    }
	as_warn (_("Unknown CPU identifier `%s'"), arg);
      found:;
      }
      break;

#ifdef OBJ_EVAX
    case '+':			/* For g++.  Hash any name > 63 chars long.  */
      alpha_flag_hash_long_names = 1;
      break;

    case 'H':			/* Show new symbol after hash truncation.  */
      alpha_flag_show_after_trunc = 1;
      break;

    case 'h':			/* For gnu-c/vax compatibility.  */
      break;

    case OPTION_REPLACE:
      alpha_flag_replace = 1;
      break;

    case OPTION_NOREPLACE:
      alpha_flag_replace = 0;
      break;
#endif

    case OPTION_RELAX:
      alpha_flag_relax = 1;
      break;

#ifdef OBJ_ELF
    case OPTION_MDEBUG:
      alpha_flag_mdebug = 1;
      break;
    case OPTION_NO_MDEBUG:
      alpha_flag_mdebug = 0;
      break;
#endif

    default:
      return 0;
    }

  return 1;
}

/* Print a description of the command-line options that we accept.  */

void
md_show_usage (FILE *stream)
{
  fputs (_("\
Alpha options:\n\
-32addr			treat addresses as 32-bit values\n\
-F			lack floating point instructions support\n\
-mev4 | -mev45 | -mev5 | -mev56 | -mpca56 | -mev6 | -mev67 | -mev68 | -mall\n\
			specify variant of Alpha architecture\n\
-m21064 | -m21066 | -m21164 | -m21164a | -m21164pc | -m21264 | -m21264a | -m21264b\n\
			these variants include PALcode opcodes\n"),
	stream);
#ifdef OBJ_EVAX
  fputs (_("\
VMS options:\n\
-+			encode (don't truncate) names longer than 64 characters\n\
-H			show new symbol after hash truncation\n\
-replace/-noreplace	enable or disable the optimization of procedure calls\n"),
	stream);
#endif
}

/* Decide from what point a pc-relative relocation is relative to,
   relative to the pc-relative fixup.  Er, relatively speaking.  */

long
md_pcrel_from (fixS *fixP)
{
  valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;

  switch (fixP->fx_r_type)
    {
    case BFD_RELOC_23_PCREL_S2:
    case BFD_RELOC_ALPHA_HINT:
    case BFD_RELOC_ALPHA_BRSGP:
      return addr + 4;
    default:
      return addr;
    }
}

/* Attempt to simplify or even eliminate a fixup.  The return value is
   ignored; perhaps it was once meaningful, but now it is historical.
   To indicate that a fixup has been eliminated, set fixP->fx_done.

   For ELF, here it is that we transform the GPDISP_HI16 reloc we used
   internally into the GPDISP reloc used externally.  We had to do
   this so that we'd have the GPDISP_LO16 reloc as a tag to compute
   the distance to the "lda" instruction for setting the addend to
   GPDISP.  */

void
md_apply_fix (fixS *fixP, valueT * valP, segT seg)
{
  char * const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where;
  valueT value = * valP;
  unsigned image, size;

  switch (fixP->fx_r_type)
    {
      /* The GPDISP relocations are processed internally with a symbol
	 referring to the current function's section;  we need to drop
	 in a value which, when added to the address of the start of
	 the function, gives the desired GP.  */
    case BFD_RELOC_ALPHA_GPDISP_HI16:
      {
	fixS *next = fixP->fx_next;

	/* With user-specified !gpdisp relocations, we can be missing
	   the matching LO16 reloc.  We will have already issued an
	   error message.  */
	if (next)
	  fixP->fx_offset = (next->fx_frag->fr_address + next->fx_where
			     - fixP->fx_frag->fr_address - fixP->fx_where);

	value = (value - sign_extend_16 (value)) >> 16;
      }
#ifdef OBJ_ELF
      fixP->fx_r_type = BFD_RELOC_ALPHA_GPDISP;
#endif
      goto do_reloc_gp;

    case BFD_RELOC_ALPHA_GPDISP_LO16:
      value = sign_extend_16 (value);
      fixP->fx_offset = 0;
#ifdef OBJ_ELF
      fixP->fx_done = 1;
#endif

    do_reloc_gp:
      fixP->fx_addsy = section_symbol (seg);
      md_number_to_chars (fixpos, value, 2);
      break;

    case BFD_RELOC_8:
      if (fixP->fx_pcrel)
	fixP->fx_r_type = BFD_RELOC_8_PCREL;
      size = 1;
      goto do_reloc_xx;

    case BFD_RELOC_16:
      if (fixP->fx_pcrel)
	fixP->fx_r_type = BFD_RELOC_16_PCREL;
      size = 2;
      goto do_reloc_xx;

    case BFD_RELOC_32:
      if (fixP->fx_pcrel)
	fixP->fx_r_type = BFD_RELOC_32_PCREL;
      size = 4;
      goto do_reloc_xx;

    case BFD_RELOC_64:
      if (fixP->fx_pcrel)
	fixP->fx_r_type = BFD_RELOC_64_PCREL;
      size = 8;

    do_reloc_xx:
      if (fixP->fx_pcrel == 0 && fixP->fx_addsy == 0)
	{
	  md_number_to_chars (fixpos, value, size);
	  goto done;
	}
      return;

#ifdef OBJ_ECOFF
    case BFD_RELOC_GPREL32:
      gas_assert (fixP->fx_subsy == alpha_gp_symbol);
      fixP->fx_subsy = 0;
      /* FIXME: inherited this obliviousness of `value' -- why?  */
      md_number_to_chars (fixpos, -alpha_gp_value, 4);
      break;
#else
    case BFD_RELOC_GPREL32:
#endif
    case BFD_RELOC_GPREL16:
    case BFD_RELOC_ALPHA_GPREL_HI16:
    case BFD_RELOC_ALPHA_GPREL_LO16:
      return;

    case BFD_RELOC_23_PCREL_S2:
      if (fixP->fx_pcrel == 0 && fixP->fx_addsy == 0)
	{
	  image = bfd_getl32 (fixpos);
	  image = (image & ~0x1FFFFF) | ((value >> 2) & 0x1FFFFF);
	  goto write_done;
	}
      return;

    case BFD_RELOC_ALPHA_HINT:
      if (fixP->fx_pcrel == 0 && fixP->fx_addsy == 0)
	{
	  image = bfd_getl32 (fixpos);
	  image = (image & ~0x3FFF) | ((value >> 2) & 0x3FFF);
	  goto write_done;
	}
      return;

#ifdef OBJ_ELF
    case BFD_RELOC_ALPHA_BRSGP:
      return;

    case BFD_RELOC_ALPHA_TLSGD:
    case BFD_RELOC_ALPHA_TLSLDM:
    case BFD_RELOC_ALPHA_GOTDTPREL16:
    case BFD_RELOC_ALPHA_DTPREL_HI16:
    case BFD_RELOC_ALPHA_DTPREL_LO16:
    case BFD_RELOC_ALPHA_DTPREL16:
    case BFD_RELOC_ALPHA_GOTTPREL16:
    case BFD_RELOC_ALPHA_TPREL_HI16:
    case BFD_RELOC_ALPHA_TPREL_LO16:
    case BFD_RELOC_ALPHA_TPREL16:
      if (fixP->fx_addsy)
	S_SET_THREAD_LOCAL (fixP->fx_addsy);
      return;
#endif

#ifdef OBJ_ECOFF
    case BFD_RELOC_ALPHA_LITERAL:
      md_number_to_chars (fixpos, value, 2);
      return;
#endif
    case BFD_RELOC_ALPHA_ELF_LITERAL:
    case BFD_RELOC_ALPHA_LITUSE:
    case BFD_RELOC_ALPHA_LINKAGE:
    case BFD_RELOC_ALPHA_CODEADDR:
      return;

#ifdef OBJ_EVAX
    case BFD_RELOC_ALPHA_NOP:
      value -= (8 + 4); /* PC-relative, base is jsr+4.  */

      /* From B.4.5.2 of the OpenVMS Linker Utility Manual:
	 "Finally, the ETIR$C_STC_BSR command passes the same address
	  as ETIR$C_STC_NOP (so that they will fail or succeed together),
	  and the same test is done again."  */
      if (S_GET_SEGMENT (fixP->fx_addsy) == undefined_section)
	{
	  fixP->fx_addnumber = -value;
	  return;
	}

      if (value + (1u << 22) >= (1u << 23))
	goto done;
      else
	{
	  /* Change to a nop.  */
	  image = 0x47FF041F;
	  goto write_done;
	}

    case BFD_RELOC_ALPHA_LDA:
      /* fixup_segment sets fixP->fx_addsy to NULL when it can pre-compute
	 the value for an O_subtract.  */
      if (fixP->fx_addsy
	  && S_GET_SEGMENT (fixP->fx_addsy) == undefined_section)
	{
	  fixP->fx_addnumber = symbol_get_bfdsym (fixP->fx_subsy)->value;
	  return;
	}

      if (value + (1u << 15) >= (1u << 16))
	goto done;
      else
	{
	  /* Change to an lda.  */
	  image = 0x237B0000 | (value & 0xFFFF);
	  goto write_done;
	}

    case BFD_RELOC_ALPHA_BSR:
    case BFD_RELOC_ALPHA_BOH:
      value -= 4; /* PC-relative, base is jsr+4.  */

      /* See comment in the BFD_RELOC_ALPHA_NOP case above.  */
      if (S_GET_SEGMENT (fixP->fx_addsy) == undefined_section)
	{
	  fixP->fx_addnumber = -value;
	  return;
	}

      if (value + (1u << 22) >= (1u << 23))
	{
	  /* Out of range.  */
	  if (fixP->fx_r_type == BFD_RELOC_ALPHA_BOH)
	    {
	      /* Add a hint.  */
	      image = bfd_getl32(fixpos);
	      image = (image & ~0x3FFF) | ((value >> 2) & 0x3FFF);
	      goto write_done;
	    }
	  goto done;
	}
      else
	{
	  /* Change to a branch.  */
	  image = 0xD3400000 | ((value >> 2) & 0x1FFFFF);
	  goto write_done;
	}
#endif

    case BFD_RELOC_VTABLE_INHERIT:
    case BFD_RELOC_VTABLE_ENTRY:
      return;

    default:
      {
	const struct alpha_operand *operand;

	if ((int) fixP->fx_r_type >= 0)
	  as_fatal (_("unhandled relocation type %s"),
		    bfd_get_reloc_code_name (fixP->fx_r_type));

	gas_assert (-(int) fixP->fx_r_type < (int) alpha_num_operands);
	operand = &alpha_operands[-(int) fixP->fx_r_type];

	/* The rest of these fixups only exist internally during symbol
	   resolution and have no representation in the object file.
	   Therefore they must be completely resolved as constants.  */

	if (fixP->fx_addsy != 0
	    && S_GET_SEGMENT (fixP->fx_addsy) != absolute_section)
	  as_bad_where (fixP->fx_file, fixP->fx_line,
			_("non-absolute expression in constant field"));

	image = bfd_getl32 (fixpos);
	image = insert_operand (image, operand, (offsetT) value,
				fixP->fx_file, fixP->fx_line);
      }
      goto write_done;
    }

  if (fixP->fx_addsy != 0 || fixP->fx_pcrel != 0)
    return;
  else
    {
      as_warn_where (fixP->fx_file, fixP->fx_line,
		     _("type %d reloc done?\n"), (int) fixP->fx_r_type);
      goto done;
    }

 write_done:
  md_number_to_chars (fixpos, image, 4);

 done:
  fixP->fx_done = 1;
}

/* Look for a register name in the given symbol.  */

symbolS *
md_undefined_symbol (char *name)
{
  if (*name == '$')
    {
      int is_float = 0, num;

      switch (*++name)
	{
	case 'f':
	  if (name[1] == 'p' && name[2] == '\0')
	    return alpha_register_table[AXP_REG_FP];
	  is_float = 32;
	  /* Fall through.  */

	case 'r':
	  if (!ISDIGIT (*++name))
	    break;
	  /* Fall through.  */

	case '0': case '1': case '2': case '3': case '4':
	case '5': case '6': case '7': case '8': case '9':
	  if (name[1] == '\0')
	    num = name[0] - '0';
	  else if (name[0] != '0' && ISDIGIT (name[1]) && name[2] == '\0')
	    {
	      num = (name[0] - '0') * 10 + name[1] - '0';
	      if (num >= 32)
		break;
	    }
	  else
	    break;

	  if (!alpha_noat_on && (num + is_float) == AXP_REG_AT)
	    as_warn (_("Used $at without \".set noat\""));
	  return alpha_register_table[num + is_float];

	case 'a':
	  if (name[1] == 't' && name[2] == '\0')
	    {
	      if (!alpha_noat_on)
		as_warn (_("Used $at without \".set noat\""));
	      return alpha_register_table[AXP_REG_AT];
	    }
	  break;

	case 'g':
	  if (name[1] == 'p' && name[2] == '\0')
	    return alpha_register_table[alpha_gp_register];
	  break;

	case 's':
	  if (name[1] == 'p' && name[2] == '\0')
	    return alpha_register_table[AXP_REG_SP];
	  break;
	}
    }
  return NULL;
}

#ifdef OBJ_ECOFF
/* @@@ Magic ECOFF bits.  */

void
alpha_frob_ecoff_data (void)
{
  select_gp_value ();
  /* $zero and $f31 are read-only.  */
  alpha_gprmask &= ~1;
  alpha_fprmask &= ~1;
}
#endif

/* Hook to remember a recently defined label so that the auto-align
   code can adjust the symbol after we know what alignment will be
   required.  */

void
alpha_define_label (symbolS *sym)
{
  alpha_insn_label = sym;
#ifdef OBJ_ELF
  dwarf2_emit_label (sym);
#endif
}

/* Return true if we must always emit a reloc for a type and false if
   there is some hope of resolving it at assembly time.  */

int
alpha_force_relocation (fixS *f)
{
  if (alpha_flag_relax)
    return 1;

  switch (f->fx_r_type)
    {
    case BFD_RELOC_ALPHA_GPDISP_HI16:
    case BFD_RELOC_ALPHA_GPDISP_LO16:
    case BFD_RELOC_ALPHA_GPDISP:
    case BFD_RELOC_ALPHA_LITERAL:
    case BFD_RELOC_ALPHA_ELF_LITERAL:
    case BFD_RELOC_ALPHA_LITUSE:
    case BFD_RELOC_GPREL16:
    case BFD_RELOC_GPREL32:
    case BFD_RELOC_ALPHA_GPREL_HI16:
    case BFD_RELOC_ALPHA_GPREL_LO16:
    case BFD_RELOC_ALPHA_LINKAGE:
    case BFD_RELOC_ALPHA_CODEADDR:
    case BFD_RELOC_ALPHA_BRSGP:
    case BFD_RELOC_ALPHA_TLSGD:
    case BFD_RELOC_ALPHA_TLSLDM:
    case BFD_RELOC_ALPHA_GOTDTPREL16:
    case BFD_RELOC_ALPHA_DTPREL_HI16:
    case BFD_RELOC_ALPHA_DTPREL_LO16:
    case BFD_RELOC_ALPHA_DTPREL16:
    case BFD_RELOC_ALPHA_GOTTPREL16:
    case BFD_RELOC_ALPHA_TPREL_HI16:
    case BFD_RELOC_ALPHA_TPREL_LO16:
    case BFD_RELOC_ALPHA_TPREL16:
#ifdef OBJ_EVAX
    case BFD_RELOC_ALPHA_NOP:
    case BFD_RELOC_ALPHA_BSR:
    case BFD_RELOC_ALPHA_LDA:
    case BFD_RELOC_ALPHA_BOH:
#endif
      return 1;

    default:
      break;
    }

  return generic_force_reloc (f);
}

/* Return true if we can partially resolve a relocation now.  */

int
alpha_fix_adjustable (fixS *f)
{
  /* Are there any relocation types for which we must generate a
     reloc but we can adjust the values contained within it?   */
  switch (f->fx_r_type)
    {
    case BFD_RELOC_ALPHA_GPDISP_HI16:
    case BFD_RELOC_ALPHA_GPDISP_LO16:
    case BFD_RELOC_ALPHA_GPDISP:
      return 0;

    case BFD_RELOC_ALPHA_LITERAL:
    case BFD_RELOC_ALPHA_ELF_LITERAL:
    case BFD_RELOC_ALPHA_LITUSE:
    case BFD_RELOC_ALPHA_LINKAGE:
    case BFD_RELOC_ALPHA_CODEADDR:
      return 1;

    case BFD_RELOC_VTABLE_ENTRY:
    case BFD_RELOC_VTABLE_INHERIT:
      return 0;

    case BFD_RELOC_GPREL16:
    case BFD_RELOC_GPREL32:
    case BFD_RELOC_ALPHA_GPREL_HI16:
    case BFD_RELOC_ALPHA_GPREL_LO16:
    case BFD_RELOC_23_PCREL_S2:
    case BFD_RELOC_16:
    case BFD_RELOC_32:
    case BFD_RELOC_64:
    case BFD_RELOC_ALPHA_HINT:
      return 1;

    case BFD_RELOC_ALPHA_TLSGD:
    case BFD_RELOC_ALPHA_TLSLDM:
    case BFD_RELOC_ALPHA_GOTDTPREL16:
    case BFD_RELOC_ALPHA_DTPREL_HI16:
    case BFD_RELOC_ALPHA_DTPREL_LO16:
    case BFD_RELOC_ALPHA_DTPREL16:
    case BFD_RELOC_ALPHA_GOTTPREL16:
    case BFD_RELOC_ALPHA_TPREL_HI16:
    case BFD_RELOC_ALPHA_TPREL_LO16:
    case BFD_RELOC_ALPHA_TPREL16:
      /* ??? No idea why we can't return a reference to .tbss+10, but
	 we're preventing this in the other assemblers.  Follow for now.  */
      return 0;

#ifdef OBJ_ELF
    case BFD_RELOC_ALPHA_BRSGP:
      /* If we have a BRSGP reloc to a local symbol, adjust it to BRADDR and
         let it get resolved at assembly time.  */
      {
	symbolS *sym = f->fx_addsy;
	const char *name;
	int offset = 0;

	if (generic_force_reloc (f))
	  return 0;

	switch (S_GET_OTHER (sym) & STO_ALPHA_STD_GPLOAD)
	  {
	  case STO_ALPHA_NOPV:
	    break;
	  case STO_ALPHA_STD_GPLOAD:
	    offset = 8;
	    break;
	  default:
	    if (S_IS_LOCAL (sym))
	      name = "<local>";
	    else
	      name = S_GET_NAME (sym);
	    as_bad_where (f->fx_file, f->fx_line,
		_("!samegp reloc against symbol without .prologue: %s"),
		name);
	    break;
	  }
	f->fx_r_type = BFD_RELOC_23_PCREL_S2;
	f->fx_offset += offset;
	return 1;
      }
#endif
#ifdef OBJ_EVAX
    case BFD_RELOC_ALPHA_NOP:
    case BFD_RELOC_ALPHA_BSR:
    case BFD_RELOC_ALPHA_LDA:
    case BFD_RELOC_ALPHA_BOH:
      return 1;
#endif

    default:
      return 1;
    }
}

/* Generate the BFD reloc to be stuck in the object file from the
   fixup used internally in the assembler.  */

arelent *
tc_gen_reloc (asection *sec ATTRIBUTE_UNUSED,
	      fixS *fixp)
{
  arelent *reloc;

  reloc = XNEW (arelent);
  reloc->sym_ptr_ptr = XNEW (asymbol *);
  *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
  reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;

  /* Make sure none of our internal relocations make it this far.
     They'd better have been fully resolved by this point.  */
  gas_assert ((int) fixp->fx_r_type > 0);

  reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
  if (reloc->howto == NULL)
    {
      as_bad_where (fixp->fx_file, fixp->fx_line,
		    _("cannot represent `%s' relocation in object file"),
		    bfd_get_reloc_code_name (fixp->fx_r_type));
      return NULL;
    }

  if (!fixp->fx_pcrel != !reloc->howto->pc_relative)
    as_fatal (_("internal error? cannot generate `%s' relocation"),
	      bfd_get_reloc_code_name (fixp->fx_r_type));

  gas_assert (!fixp->fx_pcrel == !reloc->howto->pc_relative);

  reloc->addend = fixp->fx_offset;

#ifdef OBJ_ECOFF
  /* Fake out bfd_perform_relocation. sigh.  */
  /* ??? Better would be to use the special_function hook.  */
  if (fixp->fx_r_type == BFD_RELOC_ALPHA_LITERAL)
    reloc->addend = -alpha_gp_value;
#endif

#ifdef OBJ_EVAX
  switch (fixp->fx_r_type)
    {
      struct evax_private_udata_struct *udata;
      const char *pname;
      int pname_len;

    case BFD_RELOC_ALPHA_LINKAGE:
      /* Copy the linkage index.  */
      reloc->addend = fixp->fx_addnumber;
      break;

    case BFD_RELOC_ALPHA_NOP:
    case BFD_RELOC_ALPHA_BSR:
    case BFD_RELOC_ALPHA_LDA:
    case BFD_RELOC_ALPHA_BOH:
      pname = symbol_get_bfdsym (fixp->fx_addsy)->name;

      /* We need the non-suffixed name of the procedure.  Beware that
      the main symbol might be equated so look it up and take its name.  */
      pname_len = strlen (pname);
      if (pname_len > 4 && strcmp (pname + pname_len - 4, "..en") == 0)
	{
	  symbolS *sym;
	  char *my_pname = xmemdup0 (pname, pname_len - 4);
	  sym = symbol_find (my_pname);
	  free (my_pname);
	  if (sym == NULL)
	    abort ();

	  while (symbol_equated_reloc_p (sym))
	    {
	      symbolS *n = symbol_get_value_expression (sym)->X_add_symbol;

	      /* We must avoid looping, as that can occur with a badly
	         written program.  */
	      if (n == sym)
		break;
	      sym = n;
	    }
	  pname = symbol_get_bfdsym (sym)->name;
	}

      udata = XNEW (struct evax_private_udata_struct);
      udata->enbsym = symbol_get_bfdsym (fixp->fx_addsy);
      udata->bsym = symbol_get_bfdsym (fixp->tc_fix_data.info->psym);
      udata->origname = (char *)pname;
      udata->lkindex = ((struct evax_private_udata_struct *)
        symbol_get_bfdsym (fixp->tc_fix_data.info->sym)->udata.p)->lkindex;
      reloc->sym_ptr_ptr = (void *)udata;
      reloc->addend = fixp->fx_addnumber;

    default:
      break;
    }
#endif

  return reloc;
}

/* Parse a register name off of the input_line and return a register
   number.  Gets md_undefined_symbol above to do the register name
   matching for us.

   Only called as a part of processing the ECOFF .frame directive.  */

int
tc_get_register (int frame ATTRIBUTE_UNUSED)
{
  int framereg = AXP_REG_SP;

  SKIP_WHITESPACE ();
  if (*input_line_pointer == '$')
    {
      char *s;
      char c = get_symbol_name (&s);
      symbolS *sym = md_undefined_symbol (s);

      *strchr (s, '\0') = c;
      if (sym && (framereg = S_GET_VALUE (sym)) <= 31)
	goto found;
    }
  as_warn (_("frame reg expected, using $%d."), framereg);

 found:
  note_gpreg (framereg);
  return framereg;
}

/* This is called before the symbol table is processed.  In order to
   work with gcc when using mips-tfile, we must keep all local labels.
   However, in other cases, we want to discard them.  If we were
   called with -g, but we didn't see any debugging information, it may
   mean that gcc is smuggling debugging information through to
   mips-tfile, in which case we must generate all local labels.  */

#ifdef OBJ_ECOFF

void
alpha_frob_file_before_adjust (void)
{
  if (alpha_debug != 0
      && ! ecoff_debugging_seen)
    flag_keep_locals = 1;
}

#endif /* OBJ_ECOFF */

/* The Alpha has support for some VAX floating point types, as well as for
   IEEE floating point.  We consider IEEE to be the primary floating point
   format, and sneak in the VAX floating point support here.  */
#include "config/atof-vax.c"