/* CGEN support code for m32r. This file is machine generated. Copyright (C) 1996, 1997 Free Software Foundation, Inc. This file is part of the GNU Binutils and/or GDB, the GNU debugger. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "config.h" #include #include "ansidecl.h" #include "libiberty.h" #include "bfd.h" #include "m32r-opc.h" struct cgen_keyword_entry m32r_cgen_opval_mach_entries[] = { { "m32r", 0 }, { "test", 1 } }; struct cgen_keyword m32r_cgen_opval_mach = { & m32r_cgen_opval_mach_entries[0], 2 }; struct cgen_keyword_entry m32r_cgen_opval_h_gr_entries[] = { { "fp", 13 }, { "lr", 14 }, { "sp", 15 }, { "r0", 0 }, { "r1", 1 }, { "r2", 2 }, { "r3", 3 }, { "r4", 4 }, { "r5", 5 }, { "r6", 6 }, { "r7", 7 }, { "r8", 8 }, { "r9", 9 }, { "r10", 10 }, { "r11", 11 }, { "r12", 12 }, { "r13", 13 }, { "r14", 14 }, { "r15", 15 } }; struct cgen_keyword m32r_cgen_opval_h_gr = { & m32r_cgen_opval_h_gr_entries[0], 19 }; struct cgen_keyword_entry m32r_cgen_opval_h_cr_entries[] = { { "psw", 0 }, { "cbr", 1 }, { "spi", 2 }, { "spu", 3 }, { "bpc", 6 }, { "cr0", 0 }, { "cr1", 1 }, { "cr2", 2 }, { "cr3", 3 }, { "cr4", 4 }, { "cr5", 5 }, { "cr6", 6 } }; struct cgen_keyword m32r_cgen_opval_h_cr = { & m32r_cgen_opval_h_cr_entries[0], 12 }; static CGEN_HW_ENTRY m32r_cgen_hw_entries[] = { { & m32r_cgen_hw_entries[1], "pc", CGEN_ASM_KEYWORD /*FIXME*/, 0 }, { & m32r_cgen_hw_entries[2], "h-memory", CGEN_ASM_KEYWORD /*FIXME*/, 0 }, { & m32r_cgen_hw_entries[3], "h-sint", CGEN_ASM_KEYWORD /*FIXME*/, 0 }, { & m32r_cgen_hw_entries[4], "h-uint", CGEN_ASM_KEYWORD /*FIXME*/, 0 }, { & m32r_cgen_hw_entries[5], "h-addr", CGEN_ASM_KEYWORD /*FIXME*/, 0 }, { & m32r_cgen_hw_entries[6], "h-iaddr", CGEN_ASM_KEYWORD /*FIXME*/, 0 }, { & m32r_cgen_hw_entries[7], "h-hi16", CGEN_ASM_KEYWORD /*FIXME*/, 0 }, { & m32r_cgen_hw_entries[8], "h-slo16", CGEN_ASM_KEYWORD /*FIXME*/, 0 }, { & m32r_cgen_hw_entries[9], "h-ulo16", CGEN_ASM_KEYWORD /*FIXME*/, 0 }, { & m32r_cgen_hw_entries[10], "h-gr", CGEN_ASM_KEYWORD /*FIXME*/, & m32r_cgen_opval_h_gr }, { & m32r_cgen_hw_entries[11], "h-cr", CGEN_ASM_KEYWORD /*FIXME*/, & m32r_cgen_opval_h_cr }, { & m32r_cgen_hw_entries[12], "h-accum", CGEN_ASM_KEYWORD /*FIXME*/, 0 }, { & m32r_cgen_hw_entries[13], "h-cond", CGEN_ASM_KEYWORD /*FIXME*/, 0 }, { & m32r_cgen_hw_entries[14], "h-sm", CGEN_ASM_KEYWORD /*FIXME*/, 0 }, { & m32r_cgen_hw_entries[15], "h-bsm", CGEN_ASM_KEYWORD /*FIXME*/, 0 }, { & m32r_cgen_hw_entries[16], "h-ie", CGEN_ASM_KEYWORD /*FIXME*/, 0 }, { & m32r_cgen_hw_entries[17], "h-bie", CGEN_ASM_KEYWORD /*FIXME*/, 0 }, { & m32r_cgen_hw_entries[18], "h-bcond", CGEN_ASM_KEYWORD /*FIXME*/, 0 }, { NULL, "h-bpc", CGEN_ASM_KEYWORD /*FIXME*/, 0 } }; const struct cgen_operand m32r_cgen_operand_table[CGEN_NUM_OPERANDS] = { /* sr: source register */ { "sr", 12, 4, { 0, 0|(1<f_r2 = *valuep; break; case 1 : fields->f_r1 = *valuep; break; case 2 : fields->f_r1 = *valuep; break; case 3 : fields->f_r2 = *valuep; break; case 4 : fields->f_r2 = *valuep; break; case 5 : fields->f_r1 = *valuep; break; case 6 : fields->f_simm8 = *valuep; break; case 7 : fields->f_simm16 = *valuep; break; case 8 : fields->f_uimm4 = *valuep; break; case 9 : fields->f_uimm5 = *valuep; break; case 10 : fields->f_uimm16 = *valuep; break; case 11 : fields->f_hi16 = *valuep; break; case 12 : fields->f_simm16 = *valuep; break; case 13 : fields->f_uimm16 = *valuep; break; case 14 : fields->f_uimm24 = *valuep; break; case 15 : fields->f_disp8 = *valuep; break; case 16 : fields->f_disp16 = *valuep; break; case 17 : fields->f_disp24 = *valuep; break; default : fprintf (stderr, "Unrecognized field %d while setting operand.\n", opindex); abort (); } } /* Main entry point for getting values from cgen_fields. */ CGEN_INLINE long m32r_cgen_get_operand (opindex, fields) int opindex; const struct cgen_fields *fields; { long value; switch (opindex) { case 0 : value = fields->f_r2; break; case 1 : value = fields->f_r1; break; case 2 : value = fields->f_r1; break; case 3 : value = fields->f_r2; break; case 4 : value = fields->f_r2; break; case 5 : value = fields->f_r1; break; case 6 : value = fields->f_simm8; break; case 7 : value = fields->f_simm16; break; case 8 : value = fields->f_uimm4; break; case 9 : value = fields->f_uimm5; break; case 10 : value = fields->f_uimm16; break; case 11 : value = fields->f_hi16; break; case 12 : value = fields->f_simm16; break; case 13 : value = fields->f_uimm16; break; case 14 : value = fields->f_uimm24; break; case 15 : value = fields->f_disp8; break; case 16 : value = fields->f_disp16; break; case 17 : value = fields->f_disp24; break; default : fprintf (stderr, "Unrecognized field %d while getting operand.\n", opindex); abort (); } return value; }