From c3f6f71df382eaaaac4440a91e6f310d03fb8da6 Mon Sep 17 00:00:00 2001 From: Jason Molenda Date: Thu, 6 Jan 2000 03:07:20 +0000 Subject: import gdb-2000-01-05 snapshot --- sim/ChangeLog | 5 + sim/d10v/ChangeLog | 14 +++ sim/d10v/d10v_sim.h | 3 +- sim/d10v/interp.c | 1 + sim/d10v/simops.c | 209 +++++++++++++++++++++++++++++----- sim/testsuite/d10v-elf/ChangeLog | 12 ++ sim/testsuite/d10v-elf/Makefile.in | 23 ++++ sim/testsuite/d10v-elf/t-ae-ld-d.s | 13 +++ sim/testsuite/d10v-elf/t-ae-ld-i.s | 16 +++ sim/testsuite/d10v-elf/t-ae-ld-id.s | 15 +++ sim/testsuite/d10v-elf/t-ae-ld-im.s | 16 +++ sim/testsuite/d10v-elf/t-ae-ld-ip.s | 16 +++ sim/testsuite/d10v-elf/t-ae-ld2w-d.s | 13 +++ sim/testsuite/d10v-elf/t-ae-ld2w-i.s | 16 +++ sim/testsuite/d10v-elf/t-ae-ld2w-id.s | 14 +++ sim/testsuite/d10v-elf/t-ae-ld2w-im.s | 16 +++ sim/testsuite/d10v-elf/t-ae-ld2w-ip.s | 16 +++ sim/testsuite/d10v-elf/t-ae-st-d.s | 13 +++ sim/testsuite/d10v-elf/t-ae-st-i.s | 16 +++ sim/testsuite/d10v-elf/t-ae-st-id.s | 14 +++ sim/testsuite/d10v-elf/t-ae-st-im.s | 16 +++ sim/testsuite/d10v-elf/t-ae-st-ip.s | 16 +++ sim/testsuite/d10v-elf/t-ae-st-is.s | 16 +++ sim/testsuite/d10v-elf/t-ae-st2w-d.s | 13 +++ sim/testsuite/d10v-elf/t-ae-st2w-i.s | 16 +++ sim/testsuite/d10v-elf/t-ae-st2w-id.s | 14 +++ sim/testsuite/d10v-elf/t-ae-st2w-im.s | 16 +++ sim/testsuite/d10v-elf/t-ae-st2w-ip.s | 16 +++ sim/testsuite/d10v-elf/t-ae-st2w-is.s | 16 +++ sim/testsuite/d10v-elf/t-macros.i | 73 +++++++++++- sim/testsuite/d10v-elf/t-mod-ld-pre.s | 126 ++++++++++++++++++++ 31 files changed, 767 insertions(+), 32 deletions(-) create mode 100644 sim/testsuite/d10v-elf/t-ae-ld-d.s create mode 100644 sim/testsuite/d10v-elf/t-ae-ld-i.s create mode 100644 sim/testsuite/d10v-elf/t-ae-ld-id.s create mode 100644 sim/testsuite/d10v-elf/t-ae-ld-im.s create mode 100644 sim/testsuite/d10v-elf/t-ae-ld-ip.s create mode 100644 sim/testsuite/d10v-elf/t-ae-ld2w-d.s create mode 100644 sim/testsuite/d10v-elf/t-ae-ld2w-i.s create mode 100644 sim/testsuite/d10v-elf/t-ae-ld2w-id.s create mode 100644 sim/testsuite/d10v-elf/t-ae-ld2w-im.s create mode 100644 sim/testsuite/d10v-elf/t-ae-ld2w-ip.s create mode 100644 sim/testsuite/d10v-elf/t-ae-st-d.s create mode 100644 sim/testsuite/d10v-elf/t-ae-st-i.s create mode 100644 sim/testsuite/d10v-elf/t-ae-st-id.s create mode 100644 sim/testsuite/d10v-elf/t-ae-st-im.s create mode 100644 sim/testsuite/d10v-elf/t-ae-st-ip.s create mode 100644 sim/testsuite/d10v-elf/t-ae-st-is.s create mode 100644 sim/testsuite/d10v-elf/t-ae-st2w-d.s create mode 100644 sim/testsuite/d10v-elf/t-ae-st2w-i.s create mode 100644 sim/testsuite/d10v-elf/t-ae-st2w-id.s create mode 100644 sim/testsuite/d10v-elf/t-ae-st2w-im.s create mode 100644 sim/testsuite/d10v-elf/t-ae-st2w-ip.s create mode 100644 sim/testsuite/d10v-elf/t-ae-st2w-is.s create mode 100644 sim/testsuite/d10v-elf/t-mod-ld-pre.s (limited to 'sim') diff --git a/sim/ChangeLog b/sim/ChangeLog index 2dd4f3a..74fa51e 100644 --- a/sim/ChangeLog +++ b/sim/ChangeLog @@ -1,3 +1,8 @@ +1999-12-30 Chandra Chavva + + * d10v/d10v_sim.h (INC_ADDR): Added code to assign + proper address for loads with predec operations. + 1999-11-18 Ben Elliston * configure.in: Require autoconf 2.13 and remove obsolete diff --git a/sim/d10v/ChangeLog b/sim/d10v/ChangeLog index f39999d..a497981 100644 --- a/sim/d10v/ChangeLog +++ b/sim/d10v/ChangeLog @@ -1,3 +1,17 @@ +Mon Jan 3 02:06:07 2000 Andrew Cagney + + * interp.c (lookup_hash): Stop the update of the PC when there was + an illegal instruction exception. + +Mon Jan 3 00:14:33 2000 Andrew Cagney + + * simops.c (address_exception): New function. + (OP_30000000, OP_6401, OP_6001, OP_6000, OP_32010000, OP_31000000, + OP_6601, OP_6201, OP_6200, OP_33010000, OP_34000000, OP_6800, + OP_6C1F, OP_6801, OP_6C01, OP_36010000, OP_35000000, OP_6A00, + OP_6E1F, OP_6A01, OP_6E01, OP_37010000): For "ld", "ld2w", "st" + and "st2w" check that the address is aligned. + 1999-11-25 Nick Clifton * simops.c (OP_4E0F): New function: Simulate new bit pattern for diff --git a/sim/d10v/d10v_sim.h b/sim/d10v/d10v_sim.h index 130aed9..5cf43e2 100644 --- a/sim/d10v/d10v_sim.h +++ b/sim/d10v/d10v_sim.h @@ -432,7 +432,8 @@ enum #define INC_ADDR(x,i) \ do \ { \ - if (PSW_MD && GPR (x) == (MOD_E & ~((i) - 1))) \ + int test_i = i < 0 ? i : ~((i) - 1); \ + if (PSW_MD && GPR (x) == (MOD_E & test_i)) \ SET_GPR (x, MOD_S); \ else \ SET_GPR (x, GPR (x) + (i)); \ diff --git a/sim/d10v/interp.c b/sim/d10v/interp.c index 2a9ae04..33b5dca 100644 --- a/sim/d10v/interp.c +++ b/sim/d10v/interp.c @@ -102,6 +102,7 @@ lookup_hash (ins, size) (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: Illegal instruction %x at PC %x\n", ins, PC); State.exception = SIGILL; + State.pc_changed = 1; /* Don't increment the PC. */ return NULL; } h = h->next; diff --git a/sim/d10v/simops.c b/sim/d10v/simops.c index 9c1f3f6..23bc9da 100644 --- a/sim/d10v/simops.c +++ b/sim/d10v/simops.c @@ -118,6 +118,16 @@ move_to_cr (int cr, reg_t mask, reg_t val, int psw_hw_p) return val; } +/* Modify registers according to an AE - address exception. */ +static void +address_exception (void) +{ + SET_BPC (PC); + SET_BPSW (PSW); + SET_HW_PSW ((PSW & (PSW_F0_BIT | PSW_F1_BIT | PSW_C_BIT))); + JMP (AE_VECTOR_START); +} + #ifdef DEBUG static void trace_input_func PARAMS ((char *name, enum op_types in1, @@ -1313,8 +1323,15 @@ void OP_30000000 () { uint16 tmp; + uint16 addr = OP[1] + GPR (OP[2]); trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID); - tmp = RW (OP[1] + GPR (OP[2])); + if ((addr & 1)) + { + address_exception (); + trace_output_void (); + return; + } + tmp = RW (addr); SET_GPR (OP[0], tmp); trace_output_16 (tmp); } @@ -1324,8 +1341,15 @@ void OP_6401 () { uint16 tmp; + uint16 addr = GPR (OP[1]); trace_input ("ld", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID); - tmp = RW (GPR (OP[1])); + if ((addr & 1)) + { + address_exception (); + trace_output_void (); + return; + } + tmp = RW (addr); SET_GPR (OP[0], tmp); if (OP[0] != OP[1]) INC_ADDR (OP[1], -2); @@ -1337,8 +1361,15 @@ void OP_6001 () { uint16 tmp; + uint16 addr = GPR (OP[1]); trace_input ("ld", OP_REG_OUTPUT, OP_POSTINC, OP_VOID); - tmp = RW (GPR (OP[1])); + if ((addr & 1)) + { + address_exception (); + trace_output_void (); + return; + } + tmp = RW (addr); SET_GPR (OP[0], tmp); if (OP[0] != OP[1]) INC_ADDR (OP[1], 2); @@ -1350,8 +1381,15 @@ void OP_6000 () { uint16 tmp; + uint16 addr = GPR (OP[1]); trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID); - tmp = RW (GPR (OP[1])); + if ((addr & 1)) + { + address_exception (); + trace_output_void (); + return; + } + tmp = RW (addr); SET_GPR (OP[0], tmp); trace_output_16 (tmp); } @@ -1361,9 +1399,15 @@ void OP_32010000 () { uint16 tmp; - + uint16 addr = OP[1]; trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF3, OP_VOID); - tmp = RW (OP[1]); + if ((addr & 1)) + { + address_exception (); + trace_output_void (); + return; + } + tmp = RW (addr); SET_GPR (OP[0], tmp); trace_output_16 (tmp); } @@ -1373,9 +1417,15 @@ void OP_31000000 () { int32 tmp; - uint16 addr = GPR (OP[2]); + uint16 addr = OP[1] + GPR (OP[2]); trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID); - tmp = RLW (OP[1] + addr); + if ((addr & 1)) + { + address_exception (); + trace_output_void (); + return; + } + tmp = RLW (addr); SET_GPR32 (OP[0], tmp); trace_output_32 (tmp); } @@ -1387,6 +1437,12 @@ OP_6601 () uint16 addr = GPR (OP[1]); int32 tmp; trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID); + if ((addr & 1)) + { + address_exception (); + trace_output_void (); + return; + } tmp = RLW (addr); SET_GPR32 (OP[0], tmp); if (OP[0] != OP[1] && ((OP[0] + 1) != OP[1])) @@ -1401,6 +1457,12 @@ OP_6201 () int32 tmp; uint16 addr = GPR (OP[1]); trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTINC, OP_VOID); + if ((addr & 1)) + { + address_exception (); + trace_output_void (); + return; + } tmp = RLW (addr); SET_GPR32 (OP[0], tmp); if (OP[0] != OP[1] && ((OP[0] + 1) != OP[1])) @@ -1415,7 +1477,13 @@ OP_6200 () uint16 addr = GPR (OP[1]); int32 tmp; trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF, OP_VOID); - tmp = RLW (addr + 0); + if ((addr & 1)) + { + address_exception (); + trace_output_void (); + return; + } + tmp = RLW (addr); SET_GPR32 (OP[0], tmp); trace_output_32 (tmp); } @@ -1425,9 +1493,15 @@ void OP_33010000 () { int32 tmp; - + uint16 addr = OP[1]; trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF3, OP_VOID); - tmp = RLW (OP[1]); + if ((addr & 1)) + { + address_exception (); + trace_output_void (); + return; + } + tmp = RLW (addr); SET_GPR32 (OP[0], tmp); trace_output_32 (tmp); } @@ -2663,8 +2737,15 @@ OP_4609 () void OP_34000000 () { + uint16 addr = OP[1] + GPR (OP[2]); trace_input ("st", OP_REG, OP_MEMREF2, OP_VOID); - SW (OP[1] + GPR (OP[2]), GPR (OP[0])); + if ((addr & 1)) + { + address_exception (); + trace_output_void (); + return; + } + SW (addr, GPR (OP[0])); trace_output_void (); } @@ -2672,12 +2753,20 @@ OP_34000000 () void OP_6800 () { + uint16 addr = GPR (OP[1]); trace_input ("st", OP_REG, OP_MEMREF, OP_VOID); - SW (GPR (OP[1]), GPR (OP[0])); + if ((addr & 1)) + { + address_exception (); + trace_output_void (); + return; + } + SW (addr, GPR (OP[0])); trace_output_void (); } /* st */ +/* st Rsrc1,@-SP */ void OP_6C1F () { @@ -2689,6 +2778,12 @@ OP_6C1F () State.exception = SIGILL; return; } + if ((addr & 1)) + { + address_exception (); + trace_output_void (); + return; + } SW (addr, GPR (OP[0])); SET_GPR (OP[1], addr); trace_output_void (); @@ -2698,8 +2793,15 @@ OP_6C1F () void OP_6801 () { + uint16 addr = GPR (OP[1]); trace_input ("st", OP_REG, OP_POSTINC, OP_VOID); - SW (GPR (OP[1]), GPR (OP[0])); + if ((addr & 1)) + { + address_exception (); + trace_output_void (); + return; + } + SW (addr, GPR (OP[0])); INC_ADDR (OP[1], 2); trace_output_void (); } @@ -2708,6 +2810,7 @@ OP_6801 () void OP_6C01 () { + uint16 addr = GPR (OP[1]); trace_input ("st", OP_REG, OP_POSTDEC, OP_VOID); if ( OP[1] == 15 ) { @@ -2715,7 +2818,13 @@ OP_6C01 () State.exception = SIGILL; return; } - SW (GPR (OP[1]), GPR (OP[0])); + if ((addr & 1)) + { + address_exception (); + trace_output_void (); + return; + } + SW (addr, GPR (OP[0])); INC_ADDR (OP[1], -2); trace_output_void (); } @@ -2724,8 +2833,15 @@ OP_6C01 () void OP_36010000 () { + uint16 addr = OP[1]; trace_input ("st", OP_REG, OP_MEMREF3, OP_VOID); - SW (OP[1], GPR (OP[0])); + if ((addr & 1)) + { + address_exception (); + trace_output_void (); + return; + } + SW (addr, GPR (OP[0])); trace_output_void (); } @@ -2733,9 +2849,16 @@ OP_36010000 () void OP_35000000 () { + uint16 addr = GPR (OP[2])+ OP[1]; trace_input ("st2w", OP_DREG, OP_MEMREF2, OP_VOID); - SW (GPR (OP[2])+ OP[1] + 0, GPR (OP[0] + 0)); - SW (GPR (OP[2])+ OP[1] + 2, GPR (OP[0] + 1)); + if ((addr & 1)) + { + address_exception (); + trace_output_void (); + return; + } + SW (addr + 0, GPR (OP[0] + 0)); + SW (addr + 2, GPR (OP[0] + 1)); trace_output_void (); } @@ -2743,9 +2866,16 @@ OP_35000000 () void OP_6A00 () { + uint16 addr = GPR (OP[1]); trace_input ("st2w", OP_DREG, OP_MEMREF, OP_VOID); - SW (GPR (OP[1]) + 0, GPR (OP[0] + 0)); - SW (GPR (OP[1]) + 2, GPR (OP[0] + 1)); + if ((addr & 1)) + { + address_exception (); + trace_output_void (); + return; + } + SW (addr + 0, GPR (OP[0] + 0)); + SW (addr + 2, GPR (OP[0] + 1)); trace_output_void (); } @@ -2761,6 +2891,12 @@ OP_6E1F () State.exception = SIGILL; return; } + if ((addr & 1)) + { + address_exception (); + trace_output_void (); + return; + } SW (addr + 0, GPR (OP[0] + 0)); SW (addr + 2, GPR (OP[0] + 1)); SET_GPR (OP[1], addr); @@ -2771,9 +2907,16 @@ OP_6E1F () void OP_6A01 () { + uint16 addr = GPR (OP[1]); trace_input ("st2w", OP_DREG, OP_POSTINC, OP_VOID); - SW (GPR (OP[1]) + 0, GPR (OP[0] + 0)); - SW (GPR (OP[1]) + 2, GPR (OP[0] + 1)); + if ((addr & 1)) + { + address_exception (); + trace_output_void (); + return; + } + SW (addr + 0, GPR (OP[0] + 0)); + SW (addr + 2, GPR (OP[0] + 1)); INC_ADDR (OP[1], 4); trace_output_void (); } @@ -2782,6 +2925,7 @@ OP_6A01 () void OP_6E01 () { + uint16 addr = GPR (OP[1]); trace_input ("st2w", OP_DREG, OP_POSTDEC, OP_VOID); if ( OP[1] == 15 ) { @@ -2789,8 +2933,14 @@ OP_6E01 () State.exception = SIGILL; return; } - SW (GPR (OP[1]) + 0, GPR (OP[0] + 0)); - SW (GPR (OP[1]) + 2, GPR (OP[0] + 1)); + if ((addr & 1)) + { + address_exception (); + trace_output_void (); + return; + } + SW (addr + 0, GPR (OP[0] + 0)); + SW (addr + 2, GPR (OP[0] + 1)); INC_ADDR (OP[1], -4); trace_output_void (); } @@ -2799,9 +2949,16 @@ OP_6E01 () void OP_37010000 () { + uint16 addr = OP[1]; trace_input ("st2w", OP_DREG, OP_MEMREF3, OP_VOID); - SW (OP [1] + 0, GPR (OP[0] + 0)); - SW (OP [1] + 2, GPR (OP[0] + 1)); + if ((addr & 1)) + { + address_exception (); + trace_output_void (); + return; + } + SW (addr + 0, GPR (OP[0] + 0)); + SW (addr + 2, GPR (OP[0] + 1)); trace_output_void (); } diff --git a/sim/testsuite/d10v-elf/ChangeLog b/sim/testsuite/d10v-elf/ChangeLog index de4a22c..1d73e29 100644 --- a/sim/testsuite/d10v-elf/ChangeLog +++ b/sim/testsuite/d10v-elf/ChangeLog @@ -1,3 +1,15 @@ +Mon Jan 3 00:17:28 2000 Andrew Cagney + + * t-ae-ld-d.s, t-ae-ld-i.s, t-ae-ld-id.s, t-ae-ld-im.s , + t-ae-ld-ip.s, t-ae-ld2w-d.s, t-ae-ld2w-i.s, t-ae-ld2w-id.s , + t-ae-ld2w-im.s, t-ae-ld2w-ip.s, t-ae-st-d.s, t-ae-st-i.s , + t-ae-st-id.s, t-ae-st-im.s, t-ae-st-ip.s, t-ae-st-is.s , + t-ae-st2w-d.s, t-ae-st2w-i.s, t-ae-st2w-id.s, t-ae-st2w-im.s , + t-ae-st2w-ip.s, t-ae-st2w-is.s: New tests. Check that an address + exception occures when a word/two-word load/store is not word + aligned. + * Makefile.in (TESTS): Update. + Fri Oct 29 18:36:34 1999 Andrew Cagney * t-mvtc.s: Check that the user can not modify the DM bit in the diff --git a/sim/testsuite/d10v-elf/Makefile.in b/sim/testsuite/d10v-elf/Makefile.in index b170f37..079f95d 100644 --- a/sim/testsuite/d10v-elf/Makefile.in +++ b/sim/testsuite/d10v-elf/Makefile.in @@ -60,6 +60,29 @@ TESTS = \ t-sub2w.ok \ t-sub.ok \ t-subi.ok \ + t-ae-ld-d.ok \ + t-ae-ld-i.ok \ + t-ae-ld-id.ok \ + t-ae-ld-im.ok \ + t-ae-ld-ip.ok \ + t-ae-ld2w-d.ok \ + t-ae-ld2w-i.ok \ + t-ae-ld2w-id.ok \ + t-ae-ld2w-im.ok \ + t-ae-ld2w-ip.ok \ + t-ae-st-d.ok \ + t-ae-st-i.ok \ + t-ae-st-id.ok \ + t-ae-st-im.ok \ + t-ae-st-ip.ok \ + t-ae-st-is.ok \ + t-ae-st2w-d.ok \ + t-ae-st2w-i.ok \ + t-ae-st2w-id.ok \ + t-ae-st2w-im.ok \ + t-ae-st2w-ip.ok \ + t-ae-st2w-is.ok \ + t-mod-ld-pre.ok \ # AS_FOR_TARGET = `\ diff --git a/sim/testsuite/d10v-elf/t-ae-ld-d.s b/sim/testsuite/d10v-elf/t-ae-ld-d.s new file mode 100644 index 0000000..1be783f --- /dev/null +++ b/sim/testsuite/d10v-elf/t-ae-ld-d.s @@ -0,0 +1,13 @@ +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_ld + + ld r8,@0x4000 +test_ld: + ld r8,@0x4001 + nop + exit47 diff --git a/sim/testsuite/d10v-elf/t-ae-ld-i.s b/sim/testsuite/d10v-elf/t-ae-ld-i.s new file mode 100644 index 0000000..42168e1 --- /dev/null +++ b/sim/testsuite/d10v-elf/t-ae-ld-i.s @@ -0,0 +1,16 @@ +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_ld + + ldi r10, #0x4000 + ld r8, @r10 + + ldi r10, #0x4001 +test_ld: + ld r8,@r10 + nop + exit47 diff --git a/sim/testsuite/d10v-elf/t-ae-ld-id.s b/sim/testsuite/d10v-elf/t-ae-ld-id.s new file mode 100644 index 0000000..86b7382 --- /dev/null +++ b/sim/testsuite/d10v-elf/t-ae-ld-id.s @@ -0,0 +1,15 @@ +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_ld + + ldi r10, #0x4001 + ld r8, @(1,r10) + +test_ld: + ld r8,@(2,r10) + nop + exit47 diff --git a/sim/testsuite/d10v-elf/t-ae-ld-im.s b/sim/testsuite/d10v-elf/t-ae-ld-im.s new file mode 100644 index 0000000..08e2ba6 --- /dev/null +++ b/sim/testsuite/d10v-elf/t-ae-ld-im.s @@ -0,0 +1,16 @@ +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_ld + + ldi r10, #0x4000 + ld r8, @r10- + + ldi r10, #0x4001 +test_ld: + ld r8,@r10- + nop + exit47 diff --git a/sim/testsuite/d10v-elf/t-ae-ld-ip.s b/sim/testsuite/d10v-elf/t-ae-ld-ip.s new file mode 100644 index 0000000..cad6660 --- /dev/null +++ b/sim/testsuite/d10v-elf/t-ae-ld-ip.s @@ -0,0 +1,16 @@ +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_ld + + ldi r10, #0x4000 + ld r8, @r10+ + + ldi r10, #0x4001 +test_ld: + ld r8,@r10+ + nop + exit47 diff --git a/sim/testsuite/d10v-elf/t-ae-ld2w-d.s b/sim/testsuite/d10v-elf/t-ae-ld2w-d.s new file mode 100644 index 0000000..c8254ab --- /dev/null +++ b/sim/testsuite/d10v-elf/t-ae-ld2w-d.s @@ -0,0 +1,13 @@ +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_ld2w + + ld2w r8,@0x4000 +test_ld2w: + ld2w r8,@0x4001 + nop + exit47 diff --git a/sim/testsuite/d10v-elf/t-ae-ld2w-i.s b/sim/testsuite/d10v-elf/t-ae-ld2w-i.s new file mode 100644 index 0000000..4b32df5 --- /dev/null +++ b/sim/testsuite/d10v-elf/t-ae-ld2w-i.s @@ -0,0 +1,16 @@ +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_ld2w + + ldi r10, #0x4000 + ld2w r8, @r10 + + ldi r10, #0x4001 +test_ld2w: + ld2w r8,@r10 + nop + exit47 diff --git a/sim/testsuite/d10v-elf/t-ae-ld2w-id.s b/sim/testsuite/d10v-elf/t-ae-ld2w-id.s new file mode 100644 index 0000000..906b2a0 --- /dev/null +++ b/sim/testsuite/d10v-elf/t-ae-ld2w-id.s @@ -0,0 +1,14 @@ +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_ld2w + + ldi r10, #0x4001 + ld2w r8,@(1,r10) +test_ld2w: + ld2w r8,@(2,r10) + nop + exit47 diff --git a/sim/testsuite/d10v-elf/t-ae-ld2w-im.s b/sim/testsuite/d10v-elf/t-ae-ld2w-im.s new file mode 100644 index 0000000..71a7286 --- /dev/null +++ b/sim/testsuite/d10v-elf/t-ae-ld2w-im.s @@ -0,0 +1,16 @@ +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_ld2w + + ldi r10, #0x4000 + ld2w r8, @r10- + + ldi r10, #0x4001 +test_ld2w: + ld2w r8,@r10- + nop + exit47 diff --git a/sim/testsuite/d10v-elf/t-ae-ld2w-ip.s b/sim/testsuite/d10v-elf/t-ae-ld2w-ip.s new file mode 100644 index 0000000..38cfab6 --- /dev/null +++ b/sim/testsuite/d10v-elf/t-ae-ld2w-ip.s @@ -0,0 +1,16 @@ +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_ld2w + + ldi r10, #0x4000 + ld2w r8, @r10+ + + ldi r10, #0x4001 +test_ld2w: + ld2w r8,@r10+ + nop + exit47 diff --git a/sim/testsuite/d10v-elf/t-ae-st-d.s b/sim/testsuite/d10v-elf/t-ae-st-d.s new file mode 100644 index 0000000..1f0edd8 --- /dev/null +++ b/sim/testsuite/d10v-elf/t-ae-st-d.s @@ -0,0 +1,13 @@ +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st + + st r8,@0x4000 +test_st: + st r8,@0x4001 + nop + exit47 diff --git a/sim/testsuite/d10v-elf/t-ae-st-i.s b/sim/testsuite/d10v-elf/t-ae-st-i.s new file mode 100644 index 0000000..1524598 --- /dev/null +++ b/sim/testsuite/d10v-elf/t-ae-st-i.s @@ -0,0 +1,16 @@ +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st + + ldi r10,#0x4000 + st r8, @r10 + + ldi r10,#0x4001 +test_st: + st r8,@r10 + nop + exit47 diff --git a/sim/testsuite/d10v-elf/t-ae-st-id.s b/sim/testsuite/d10v-elf/t-ae-st-id.s new file mode 100644 index 0000000..4caa1b4fa --- /dev/null +++ b/sim/testsuite/d10v-elf/t-ae-st-id.s @@ -0,0 +1,14 @@ +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st + + ldi r10,#0x4001 + st r8, @(1,r10) +test_st: + st r8,@(2,r10) + nop + exit47 diff --git a/sim/testsuite/d10v-elf/t-ae-st-im.s b/sim/testsuite/d10v-elf/t-ae-st-im.s new file mode 100644 index 0000000..d4c8baf --- /dev/null +++ b/sim/testsuite/d10v-elf/t-ae-st-im.s @@ -0,0 +1,16 @@ +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st + + ldi r10,#0x4000 + st r8, @r10- + + ldi r10,#0x4001 +test_st: + st r8,@r10- + nop + exit47 diff --git a/sim/testsuite/d10v-elf/t-ae-st-ip.s b/sim/testsuite/d10v-elf/t-ae-st-ip.s new file mode 100644 index 0000000..e3a02ee --- /dev/null +++ b/sim/testsuite/d10v-elf/t-ae-st-ip.s @@ -0,0 +1,16 @@ +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st + + ldi r10,#0x4000 + st r8, @r10+ + + ldi r10,#0x4001 +test_st: + st r8,@r10+ + nop + exit47 diff --git a/sim/testsuite/d10v-elf/t-ae-st-is.s b/sim/testsuite/d10v-elf/t-ae-st-is.s new file mode 100644 index 0000000..4868780 --- /dev/null +++ b/sim/testsuite/d10v-elf/t-ae-st-is.s @@ -0,0 +1,16 @@ +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st + + ldi sp,#0x4000 + st r8, @-SP + + ldi sp,#0x4001 +test_st: + st r8,@-SP + nop + exit47 diff --git a/sim/testsuite/d10v-elf/t-ae-st2w-d.s b/sim/testsuite/d10v-elf/t-ae-st2w-d.s new file mode 100644 index 0000000..a0d9c31 --- /dev/null +++ b/sim/testsuite/d10v-elf/t-ae-st2w-d.s @@ -0,0 +1,13 @@ +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st2w + + st2w r8,@0x4000 +test_st2w: + st2w r8,@0x4001 + nop + exit47 diff --git a/sim/testsuite/d10v-elf/t-ae-st2w-i.s b/sim/testsuite/d10v-elf/t-ae-st2w-i.s new file mode 100644 index 0000000..8c24bc9 --- /dev/null +++ b/sim/testsuite/d10v-elf/t-ae-st2w-i.s @@ -0,0 +1,16 @@ +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st2w + + ldi r10, #0x4000 + st2w r8, @r10 + + ldi r10, #0x4001 +test_st2w: + st2w r8,@r10 + nop + exit47 diff --git a/sim/testsuite/d10v-elf/t-ae-st2w-id.s b/sim/testsuite/d10v-elf/t-ae-st2w-id.s new file mode 100644 index 0000000..bfbfd4d --- /dev/null +++ b/sim/testsuite/d10v-elf/t-ae-st2w-id.s @@ -0,0 +1,14 @@ +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st2w + + ldi r10, #0x4001 + st2w r8, @(1,r10) +test_st2w: + st2w r8,@(2,r10) + nop + exit47 diff --git a/sim/testsuite/d10v-elf/t-ae-st2w-im.s b/sim/testsuite/d10v-elf/t-ae-st2w-im.s new file mode 100644 index 0000000..ee0a9eb --- /dev/null +++ b/sim/testsuite/d10v-elf/t-ae-st2w-im.s @@ -0,0 +1,16 @@ +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st2w + + ldi r10, #0x4000 + st2w r8, @r10- + + ldi r10, #0x4001 +test_st2w: + st2w r8,@r10- + nop + exit47 diff --git a/sim/testsuite/d10v-elf/t-ae-st2w-ip.s b/sim/testsuite/d10v-elf/t-ae-st2w-ip.s new file mode 100644 index 0000000..dc911f7 --- /dev/null +++ b/sim/testsuite/d10v-elf/t-ae-st2w-ip.s @@ -0,0 +1,16 @@ +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st2w + + ldi r10, #0x4000 + st2w r8, @r10+ + + ldi r10, #0x4001 +test_st2w: + st2w r8,@r10+ + nop + exit47 diff --git a/sim/testsuite/d10v-elf/t-ae-st2w-is.s b/sim/testsuite/d10v-elf/t-ae-st2w-is.s new file mode 100644 index 0000000..e39d71c --- /dev/null +++ b/sim/testsuite/d10v-elf/t-ae-st2w-is.s @@ -0,0 +1,16 @@ +.include "t-macros.i" + + start + + PSW_BITS = 0 + point_dmap_at_imem + check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st2w + + ldi sp, #0x4004 + st2w r8, @-SP + + ldi sp, #0x4005 +test_st2w: + st2w r8,@-SP + nop + exit47 diff --git a/sim/testsuite/d10v-elf/t-macros.i b/sim/testsuite/d10v-elf/t-macros.i index 2f54d1c..f424acf 100644 --- a/sim/testsuite/d10v-elf/t-macros.i +++ b/sim/testsuite/d10v-elf/t-macros.i @@ -21,6 +21,20 @@ _start: .endm + .macro exit1 + ldi r4, 1 + ldi r0, 1 + trap 15 + .endm + + + .macro exit2 + ldi r4, 1 + ldi r0, 2 + trap 15 + .endm + + .macro load reg val ldi \reg, #\val .endm @@ -128,6 +142,53 @@ _start: .endm +;;; Blat our DMAP registers so that they point at on-chip imem + .macro point_dmap_at_imem + .text + ldi r2, MAP_INSN | 0xf + st r2, @(DMAP_REG,r0) + ldi r2, MAP_INSN + st r2, @(IMAP1_REG,r0) + .endm + +;;; Patch VEC so that it jumps back to code that checks PSW +;;; and then exits with success. + .macro check_interrupt vec psw src +;;; Patch the interrupt vector's AE entry with a jmp to success + .text + ldi r4, #1f + ldi r5, \vec + ;; + ld2w r2, @(0,r4) + st2w r2, @(0,r5) + ld2w r2, @(4,r4) + st2w r2, @(4,r5) + ;; + bra 9f + nop +;;; Code that gets patched into the interrupt vector + .data +1: ldi r1, 2f@word + jmp r1 +;;; Successfull trap jumps back to here + .text +;;; Verify the PSW +2: mvfc r2, cr0 + cmpeqi r2, #\psw + brf0t 3f + nop + exit1 +;;; Verify the original addr +3: mvfc r2, bpc + cmpeqi r2, #\src@word + brf0t 4f + exit2 +4: exit0 +;;; continue as normal +9: + .endm + + PSW_SM = 0x8000 PSW_01 = 0x4000 PSW_EA = 0x2000 @@ -159,12 +220,14 @@ _start: ;;; - VEC_RI = 0x3fc00 - VEC_BAE = 0x3fc04 - VEC_RIE = 0x3fc08 - VEC_AE = 0x3fc0c - VEC_TRAP = 0x3fc10 + VEC_RI = 0x3ff00 + VEC_BAE = 0x3ff04 + VEC_RIE = 0x3ff08 + VEC_AE = 0x3ff0c + VEC_TRAP = 0x3ff10 VEC_DBT = 0x3ff50 VEC_SDBT = 0x3fff4 VEC_DBI = 0x3ff58 VEC_EI = 0x3ff5c + + diff --git a/sim/testsuite/d10v-elf/t-mod-ld-pre.s b/sim/testsuite/d10v-elf/t-mod-ld-pre.s new file mode 100644 index 0000000..4536e03 --- /dev/null +++ b/sim/testsuite/d10v-elf/t-mod-ld-pre.s @@ -0,0 +1,126 @@ +.include "t-macros.i" + +.section .rodata + + .text + .globl main + .type main,@function +main: + mvfc r0, PSW || ldi.s r14, #0 + ldi.l r2, 0x100 ; MOD_E + ldi.l r3, 0x108 ; MOD_S + +test_mod_dec_ld: + mvtc r2, MOD_E || bseti r0, #7 + mvtc r3, MOD_S + mvtc r0, PSW ; modulo mode enable + mv r1,r3 ; r1=0x108 + ld r4, @r1- || nop ; r1=0x106 + ld r4, @r1- || nop ; r1=0x104 + ld r4, @r1- || nop ; r1=0x102 + ld r4, @r1- || nop ; r1=0x100 + ld r4, @r1- || nop ; r1=0x108 + ld r4, @r1- || nop ; r1=0x106 + + cmpeqi r1,#0x106 + brf0f _ERR ; branch to error + +test_mod_inc_ld: + mvtc r2, MOD_S + mvtc r3, MOD_E + mv r1,r2 ; r1=0x100 + ld r4, @r1+ || nop ; r1=0x102 + ld r4, @r1+ || nop ; r1=0x104 + ld r4, @r1+ || nop ; r1=0x106 + ld r4, @r1+ || nop ; r1=0x108 + ld r4, @r1+ || nop ; r1=0x100 + ld r4, @r1+ || nop ; r1=0x102 + + cmpeqi r1,#0x102 + brf0f _ERR + +test_mod_dec_ld2w: + mvtc r2, MOD_E + mvtc r3, MOD_S + mv r1,r3 ; r1=0x108 + ld2W r4, @r1- || nop ; r1=0x104 + ld2W r4, @r1- || nop ; r1=0x100 + ld2W r4, @r1- || nop ; r1=0x108 + ld2W r4, @r1- || nop ; r1=0x104 + + cmpeqi r1,#0x104 + brf0f _ERR ; <= branch to error + +test_mod_inc_ld2w: + mvtc r2, MOD_S + mvtc r3, MOD_E || BCLRI r0, #7 + mv r1,r2 ; r1=0x100 + ld2W r4, @r1+ || nop ; r1=0x104 + ld2W r4, @r1+ || nop ; r1=0x108 + ld2W r4, @r1+ || nop ; r1=0x100 + ld2W r4, @r1+ || nop ; r1=0x104 + + cmpeqi r1,#0x104 + brf0f _ERR + +test_mod_dec_ld_dis: + mvtc r0, PSW ; modulo mode disable + mvtc r2, MOD_E + mvtc r3, MOD_S + mv r1,r3 ; r1=0x108 + ld r4, @r1- || nop ; r1=0x106 + ld r4, @r1- || nop ; r1=0x104 + ld r4, @r1- || nop ; r1=0x102 + ld r4, @r1- || nop ; r1=0x100 + ld r4, @r1- || nop ; r1=0xFE + ld r4, @r1- || nop ; r1=0xFC + + cmpeqi r1,#0xFC + brf0f _ERR + +test_mod_inc_ld_dis: + mvtc r2, MOD_S + mvtc r3, MOD_E + mv r1,r2 ; r1=0x100 + ld r4, @r1+ || nop ; r1=0x102 + ld r4, @r1+ || nop ; r1=0x104 + ld r4, @r1+ || nop ; r1=0x106 + ld r4, @r1+ || nop ; r1=0x108 + ld r4, @r1+ || nop ; r1=0x10A + ld r4, @r1+ || nop ; r1=0x10C + + cmpeqi r1,#0x10C + brf0f _ERR + +test_mod_dec_ld2w_dis: + mvtc r2, MOD_E + mvtc r3, MOD_S + mv r1,r3 ; r1=0x108 + ld2W r4, @r1- || nop ; r1=0x104 + ld2W r4, @r1- || nop ; r1=0x100 + ld2W r4, @r1- || nop ; r1=0xFC + ld2W r4, @r1- || nop ; r1=0xF8 + + cmpeqi r1,#0xF8 + brf0f _ERR + + test_mod_inc_ld2w_dis: + mvtc r2, MOD_S + mvtc r3, MOD_E + mv r1,r2 ; r1=0x100 + ld2W r4, @r1+ || nop ; r1=0x104 + ld2W r4, @r1+ || nop ; r1=0x108 + ld2W r4, @r1+ || nop ; r1=0x10C + ld2W r4, @r1+ || nop ; r1=0x110 + + cmpeqi r1,#0x110 + brf0f _ERR + +_OK: + exit0 + +_ERR: + exit47 + + + -- cgit v1.1