From 531d5282c0dda68c4618e0353157e61723334711 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Mon, 24 Jun 2013 01:44:55 +0000 Subject: sim: bfin: speed up all insn testcases slightly The main body of the "all insn" test is executed once per tested insn, and we test millions of insns here. Any shrinkage we can do in this loop will speed things up nicely (since it's multiplied per tested insn). To that end, simplify the end-of-table test into one less insn, and omit the SSYNC when we build for the sim. When we build to run on the hardware, this insn matters, but the sim doesn't have write store buffers in the chip that might get in the way (memory writes are atomic). --- sim/testsuite/sim/bfin/ChangeLog | 5 +++++ sim/testsuite/sim/bfin/se_allopcodes.h | 5 +++-- 2 files changed, 8 insertions(+), 2 deletions(-) (limited to 'sim') diff --git a/sim/testsuite/sim/bfin/ChangeLog b/sim/testsuite/sim/bfin/ChangeLog index ddcce86..11a3072 100644 --- a/sim/testsuite/sim/bfin/ChangeLog +++ b/sim/testsuite/sim/bfin/ChangeLog @@ -1,5 +1,10 @@ 2013-06-23 Mike Frysinger + * se_allopcodes.h (_match): Simplify register test to one less insn. + Omit the SSYNC insn when compiling for the sim. + +2013-06-23 Mike Frysinger + * testutils.inc: Trim trailing whitespace. 2013-06-17 Mike Frysinger diff --git a/sim/testsuite/sim/bfin/se_allopcodes.h b/sim/testsuite/sim/bfin/se_allopcodes.h index 8f96125..796d5c4 100644 --- a/sim/testsuite/sim/bfin/se_allopcodes.h +++ b/sim/testsuite/sim/bfin/se_allopcodes.h @@ -102,8 +102,7 @@ _match: se_all_load_table /* is this the end of the table? */ - R4 = 0; - CC = R4 == R7; + CC = R7 == 0; IF CC jump _new_instruction; /* is the opcode (R0) greater than the 2nd entry in the table (R6) */ @@ -168,8 +167,10 @@ _legal_instruction: _next_instruction: se_all_next_insn +.ifdef BFIN_JTAG /* Make sure the opcode isn't in a write buffer */ SSYNC; +.endif R1 = P5; RETX = R1; -- cgit v1.1