From 0592e80bcf1bbab2fbbb110ea395f9608e4f594c Mon Sep 17 00:00:00 2001 From: Jim Wilson Date: Wed, 7 Apr 2021 18:51:52 -0700 Subject: Aarch64 sim fix for gcc-10 miscompilation. This fixes a problem that occurs when compiled by gcc-10, as the code is relying on undefined overflow behavior. This is fixed by replacing compares between 32-bit and 64-bit results with compares that just use the 64-bit results with a cast. PR sim/27483 * simulator.c (set_flags_for_add32): Compare uresult against itself. Compare sresult against itself. --- sim/aarch64/ChangeLog | 6 ++++++ sim/aarch64/simulator.c | 4 ++-- 2 files changed, 8 insertions(+), 2 deletions(-) (limited to 'sim') diff --git a/sim/aarch64/ChangeLog b/sim/aarch64/ChangeLog index e667c47..d328fcd 100644 --- a/sim/aarch64/ChangeLog +++ b/sim/aarch64/ChangeLog @@ -1,3 +1,9 @@ +2021-04-07 Jim Wilson + + PR sim/27483 + * simulator.c (set_flags_for_add32): Compare uresult against + itself. Compare sresult against itself. + 2021-04-02 Mike Frysinger * aclocal.m4, configure: Regenerate. diff --git a/sim/aarch64/simulator.c b/sim/aarch64/simulator.c index 6ba29a0..e0b428d 100644 --- a/sim/aarch64/simulator.c +++ b/sim/aarch64/simulator.c @@ -1650,10 +1650,10 @@ set_flags_for_add32 (sim_cpu *cpu, int32_t value1, int32_t value2) if (result & (1 << 31)) flags |= N; - if (uresult != (uint32_t)result) + if (uresult != (uint32_t)uresult) flags |= C; - if (sresult != result) + if (sresult != (int32_t)sresult) flags |= V; aarch64_set_CPSR (cpu, flags); -- cgit v1.1