From 60fe0e06a825b1e36c35534d53d2196f01a3d74d Mon Sep 17 00:00:00 2001
From: Andrew Cagney <cagney@redhat.com>
Date: Fri, 19 Sep 1997 00:50:19 +0000
Subject: Fix cmov insn.

---
 sim/v850/sim-main.h | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

(limited to 'sim/v850/sim-main.h')

diff --git a/sim/v850/sim-main.h b/sim/v850/sim-main.h
index a4c57af..2d1bf6a 100644
--- a/sim/v850/sim-main.h
+++ b/sim/v850/sim-main.h
@@ -224,6 +224,10 @@ sim_core_write_unaligned_##LEN (STATE_CPU (simulator, 0), \
 				PC, sim_core_write_map, (ADDR), (DATA))
 
 
+/* compare cccc field against PSW */
+unsigned int condition_met (unsigned code);
+
+
 /* Debug/tracing calls */
 
 enum op_types
@@ -310,6 +314,19 @@ do { \
   } \
 } while (0)
 
+#define TRACE_ALU_INPUT3(IN0, IN1, IN2) \
+do { \
+  if (TRACE_ALU_P (CPU)) { \
+    trace_module = "alu"; \
+    trace_pc = cia; \
+    trace_name = itable[MY_INDEX].name; \
+    trace_values[0] = (IN0); \
+    trace_values[1] = (IN1); \
+    trace_values[2] = (IN2); \
+    trace_num_values = 3; \
+  } \
+} while (0)
+
 #define TRACE_ALU_RESULT(RESULT) \
 do { \
   if (TRACE_ALU_P (CPU)) { \
-- 
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