From 9335d9f8235a13777ae058b1ad59f124b678f4fc Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Thu, 8 Jul 2021 02:33:28 -0400 Subject: sim: rename ChangeLog files to ChangeLog-2021 Now that ChangeLog entries are no longer used for sim patches, this commit renames all relevant sim ChangeLog to ChangeLog-2021, similar to what we would do in the context of the "Start of New Year" procedure. The purpose of this change is to avoid people merging ChangeLog entries by mistake when applying existing commits that they are currently working on. Also throw in a .gitignore entry to keep people from adding new ChangeLog files anywhere in the sim tree. --- sim/testsuite/ChangeLog | 475 --------------------------- sim/testsuite/ChangeLog-2021 | 475 +++++++++++++++++++++++++++ sim/testsuite/aarch64/ChangeLog | 91 ----- sim/testsuite/aarch64/ChangeLog-2021 | 91 +++++ sim/testsuite/arm/ChangeLog | 133 -------- sim/testsuite/arm/ChangeLog-2021 | 133 ++++++++ sim/testsuite/avr/ChangeLog | 15 - sim/testsuite/avr/ChangeLog-2021 | 15 + sim/testsuite/bfin/ChangeLog | 386 ---------------------- sim/testsuite/bfin/ChangeLog-2021 | 386 ++++++++++++++++++++++ sim/testsuite/bpf/ChangeLog | 28 -- sim/testsuite/bpf/ChangeLog-2021 | 28 ++ sim/testsuite/cr16/ChangeLog | 60 ---- sim/testsuite/cr16/ChangeLog-2021 | 60 ++++ sim/testsuite/cris/ChangeLog | 213 ------------ sim/testsuite/cris/ChangeLog-2021 | 213 ++++++++++++ sim/testsuite/d10v/ChangeLog | 151 --------- sim/testsuite/d10v/ChangeLog-2021 | 151 +++++++++ sim/testsuite/example-synacor/ChangeLog | 9 - sim/testsuite/example-synacor/ChangeLog-2021 | 9 + sim/testsuite/frv/ChangeLog | 94 ------ sim/testsuite/frv/ChangeLog-2021 | 94 ++++++ sim/testsuite/ft32/ChangeLog | 16 - sim/testsuite/ft32/ChangeLog-2021 | 16 + sim/testsuite/h8300/ChangeLog | 134 -------- sim/testsuite/h8300/ChangeLog-2021 | 134 ++++++++ sim/testsuite/iq2000/ChangeLog | 11 - sim/testsuite/iq2000/ChangeLog-2021 | 11 + sim/testsuite/lm32/ChangeLog | 11 - sim/testsuite/lm32/ChangeLog-2021 | 11 + sim/testsuite/m32c/ChangeLog | 18 - sim/testsuite/m32c/ChangeLog-2021 | 18 + sim/testsuite/m32r/ChangeLog | 140 -------- sim/testsuite/m32r/ChangeLog-2021 | 140 ++++++++ sim/testsuite/m68hc11/ChangeLog | 11 - sim/testsuite/m68hc11/ChangeLog-2021 | 11 + sim/testsuite/mcore/ChangeLog | 16 - sim/testsuite/mcore/ChangeLog-2021 | 16 + sim/testsuite/microblaze/ChangeLog | 19 -- sim/testsuite/microblaze/ChangeLog-2021 | 19 ++ sim/testsuite/mips/ChangeLog | 126 ------- sim/testsuite/mips/ChangeLog-2021 | 126 +++++++ sim/testsuite/mn10300/ChangeLog | 11 - sim/testsuite/mn10300/ChangeLog-2021 | 11 + sim/testsuite/moxie/ChangeLog | 11 - sim/testsuite/moxie/ChangeLog-2021 | 11 + sim/testsuite/msp430/ChangeLog | 25 -- sim/testsuite/msp430/ChangeLog-2021 | 25 ++ sim/testsuite/or1k/ChangeLog | 54 --- sim/testsuite/or1k/ChangeLog-2021 | 54 +++ sim/testsuite/pru/ChangeLog | 25 -- sim/testsuite/pru/ChangeLog-2021 | 25 ++ sim/testsuite/riscv/ChangeLog | 11 - sim/testsuite/riscv/ChangeLog-2021 | 11 + sim/testsuite/sh/ChangeLog | 85 ----- sim/testsuite/sh/ChangeLog-2021 | 85 +++++ sim/testsuite/v850/ChangeLog | 27 -- sim/testsuite/v850/ChangeLog-2021 | 27 ++ 58 files changed, 2406 insertions(+), 2406 deletions(-) delete mode 100644 sim/testsuite/ChangeLog create mode 100644 sim/testsuite/ChangeLog-2021 delete mode 100644 sim/testsuite/aarch64/ChangeLog create mode 100644 sim/testsuite/aarch64/ChangeLog-2021 delete mode 100644 sim/testsuite/arm/ChangeLog create mode 100644 sim/testsuite/arm/ChangeLog-2021 delete mode 100644 sim/testsuite/avr/ChangeLog create mode 100644 sim/testsuite/avr/ChangeLog-2021 delete mode 100644 sim/testsuite/bfin/ChangeLog create mode 100644 sim/testsuite/bfin/ChangeLog-2021 delete mode 100644 sim/testsuite/bpf/ChangeLog create mode 100644 sim/testsuite/bpf/ChangeLog-2021 delete mode 100644 sim/testsuite/cr16/ChangeLog create mode 100644 sim/testsuite/cr16/ChangeLog-2021 delete mode 100644 sim/testsuite/cris/ChangeLog create mode 100644 sim/testsuite/cris/ChangeLog-2021 delete mode 100644 sim/testsuite/d10v/ChangeLog create mode 100644 sim/testsuite/d10v/ChangeLog-2021 delete mode 100644 sim/testsuite/example-synacor/ChangeLog create mode 100644 sim/testsuite/example-synacor/ChangeLog-2021 delete mode 100644 sim/testsuite/frv/ChangeLog create mode 100644 sim/testsuite/frv/ChangeLog-2021 delete mode 100644 sim/testsuite/ft32/ChangeLog create mode 100644 sim/testsuite/ft32/ChangeLog-2021 delete mode 100644 sim/testsuite/h8300/ChangeLog create mode 100644 sim/testsuite/h8300/ChangeLog-2021 delete mode 100644 sim/testsuite/iq2000/ChangeLog create mode 100644 sim/testsuite/iq2000/ChangeLog-2021 delete mode 100644 sim/testsuite/lm32/ChangeLog create mode 100644 sim/testsuite/lm32/ChangeLog-2021 delete mode 100644 sim/testsuite/m32c/ChangeLog create mode 100644 sim/testsuite/m32c/ChangeLog-2021 delete mode 100644 sim/testsuite/m32r/ChangeLog create mode 100644 sim/testsuite/m32r/ChangeLog-2021 delete mode 100644 sim/testsuite/m68hc11/ChangeLog create mode 100644 sim/testsuite/m68hc11/ChangeLog-2021 delete mode 100644 sim/testsuite/mcore/ChangeLog create mode 100644 sim/testsuite/mcore/ChangeLog-2021 delete mode 100644 sim/testsuite/microblaze/ChangeLog create mode 100644 sim/testsuite/microblaze/ChangeLog-2021 delete mode 100644 sim/testsuite/mips/ChangeLog create mode 100644 sim/testsuite/mips/ChangeLog-2021 delete mode 100644 sim/testsuite/mn10300/ChangeLog create mode 100644 sim/testsuite/mn10300/ChangeLog-2021 delete mode 100644 sim/testsuite/moxie/ChangeLog create mode 100644 sim/testsuite/moxie/ChangeLog-2021 delete mode 100644 sim/testsuite/msp430/ChangeLog create mode 100644 sim/testsuite/msp430/ChangeLog-2021 delete mode 100644 sim/testsuite/or1k/ChangeLog create mode 100644 sim/testsuite/or1k/ChangeLog-2021 delete mode 100644 sim/testsuite/pru/ChangeLog create mode 100644 sim/testsuite/pru/ChangeLog-2021 delete mode 100644 sim/testsuite/riscv/ChangeLog create mode 100644 sim/testsuite/riscv/ChangeLog-2021 delete mode 100644 sim/testsuite/sh/ChangeLog create mode 100644 sim/testsuite/sh/ChangeLog-2021 delete mode 100644 sim/testsuite/v850/ChangeLog create mode 100644 sim/testsuite/v850/ChangeLog-2021 (limited to 'sim/testsuite') diff --git a/sim/testsuite/ChangeLog b/sim/testsuite/ChangeLog deleted file mode 100644 index 7265ed8..0000000 --- a/sim/testsuite/ChangeLog +++ /dev/null @@ -1,475 +0,0 @@ -2021-06-14 Mike Frysinger - - * common/local.mk (%D%/bits32m0.c, %D%/bits32m31.c, %D%/bits64m0.c, - %D%/bits64m63.c): Use AM_V_GEN & AM_V_at wrappers. - -2021-05-07 Dimitar Dimitrov - - * local.mk (%C%_CPPFLAGS): Add ../bfd include path. - -2021-04-08 Mike Frysinger - - * lib/sim-defs.exp (run_sim_test): Set status to unsupported if - $return_code is 77. - -2021-04-08 Mike Frysinger - - * lib/sim-defs.exp (run_sim_test): Return if sim_tool_path does not - exist. - -2021-04-08 Mike Frysinger - - * lib/sim-defs.exp (sim_tool_path): New function. - (sim_run): Set sim to [sim_tool_path]. - -2021-04-03 Mike Frysinger - - * lib/sim-defs.exp (run_sim_test): Convert examples to binaries. - -2021-04-03 Mike Frysinger - - * local.mk: Include %D%/common/local.mk. - * common/Makefile.in: Removed. - * common/local.mk: New file. - -2021-03-07 Mike Frysinger - - * Makefile.in: Removed. - * lib/sim-defs.exp (sim): Update default path. - * local.mk: New file based on Makefile.in. - -2021-02-13 Mike Frysinger - - * Makefile.in (arch): Delete. - (site.exp): Do not output $arch. - -2021-02-04 Mike Frysinger - - * riscv/: New directory. - -2021-01-15 Mike Frysinger - - * Makefile.in (site.exp): Delete tool setting. - * sim/*/: Move subdirs up a directory. - -2021-01-15 Mike Frysinger - - * configure, configure.ac: Delete. - * Makefile.in (Makefile, config.status): Switch to ../config.status. - -2021-01-15 Mike Frysinger - - * configure.ac (target): Delete d10v-*-elf case. - * configure: Regenerate. - * d10v-elf/: Move directory ... - * sim/d10v/: ... here. - -2021-01-15 Mike Frysinger - - * configure.ac (target): Delete mips64el-*-elf case. - * configure: Regenerate. - * mips64el-elf/: Delete directory. - -2021-01-15 Mike Frysinger - - * configure.ac (target): Delete frv-*-elf case. - * configure: Regenerate. - * frv-elf/: Delete directory. - -2021-01-15 Mike Frysinger - - * configure.ac (target): Delete m32r-*-elf case. - * configure: Regenerate. - * m32r-elf/: Delete directory. - -2021-01-15 Mike Frysinger - - * lib/sim-defs.exp (sim_run): Delete status and return return_code. - (run_sim_test): Define status option. Change sim_run return to - return_code. Define status. Log return_code. - -2021-01-11 Mike Frysinger - - * common/alu-tst.c: Include stdlib.h. - (PACKAGE): Define. - (print_hex): Change printf to use %llx. - * common/bits-gen.c: Include stdlib.h, string.h, and unistd.h. - (gen_struct): Change long long to unsigned64. - (gen_bit): Change bit cast to bit mask. Change printf to use %llx. - (gen_mask): Likewise. - (usage): Delete default case. - (main): Change WITH_HOST_WORD_BITSIZE printf from %d to %zu. Emit - PACKAGE define and stdlib.h & string.h includes. - * common/bits-tst.c (calc): Change printf to use %llx. - (check_sext, check_rot, check_extract, check_bits): Likewise. - -2021-01-09 Mike Frysinger - - * configure: Regenerate. - * sim/sh64/: Delete. - -2021-01-05 Mike Frysinger - - * sim/fr30/: Delete. - -2021-01-05 Mike Frysinger - - * common/Make-common.in: Delete. - -2021-01-04 Mike Frysinger - - * configure: Regenerate. - -2020-10-06 Andrew Burgess - - * configure: Regnerate. - * configure.ac (AC_CONFIG_AUX_DIR): Update. - -2020-08-04 David Faust - Jose E. Marchesi - - * configure: Regenerate. - * sim/bpf: New directory. - -2020-07-29 Simon Marchi - - * configure: Re-generate. - -2019-12-19 Tom Tromey - - PR build/24572: - * Makefile.in (install-strip): New target. - -2019-09-23 Dimitar Dimitrov - - * configure: Regenerate. - -2017-12-12 Stafford Horne - Peter Gavin - - * configure: Regenerated. - -2016-01-10 Mike Frysinger - - * configure: Regenerate. - -2016-01-02 Mike Frysinger - - * common/bits-gen.c (main): Change BIG_ENDIAN to BFD_ENDIAN_BIG and - LITTLE_ENDIAN and BFD_ENDIAN_LITTLE. - -2015-11-24 Nick Clifton - - * configure: Regenerate. - * sim/aarch64: New directory. - -2015-11-14 Mike Frysinger - - * lib/sim-defs.exp (slurp_options): Pull in global subdir/srcdir. - Replace $srcdir and $subdir in the read option. - -2015-04-13 Hans-Peter Nilsson - - * lib/sim-defs.exp (sim_init): Unset target ldscript here. - -2015-03-30 Mike Frysinger - - * configure.ac: Add d10v-*-elf. - * configure: Regenerate. - -2015-03-29 Mike Frysinger - - * lib/sim-defs.exp (run_sim_test): Declare seen_output as 0. When - the test has an output keyword, set it to 1. Set default output only - when seen_output is 0. - -2015-03-29 Mike Frysinger - - * configure: Regenerate. - -2015-03-28 Mike Frysinger - - * configure: Regenerate. - -2015-03-28 James Bowman - - * configure: Regenerate. - -2014-03-10 Mike Frysinger - - * configure: Regenerate. - -2014-03-04 Mike Frysinger - - * common/bits-gen.c (main): Change to new style prototype. - -2013-09-23 Alan Modra - - * configure: Regenerate. - -2012-06-15 Joel Brobecker - - * configure: Regenerate. - -2012-03-24 Mike Frysinger - - * configure: Regenerate. - -2012-03-18 Mike Frysinger - - * .gitignore: New file. - -2011-10-17 Mike Frysinger - - * configure: Regenerate after bfin testsuite update. - -2011-05-16 Mike Frysinger - - * lib/sim-defs.exp: Support cc tag in test files. - (run_sim_test): Support global_cc_options in boards files. Convert - assembler options into compiler options (c_as_options) with -Wa. - Convert linker options into compiler options (c_ld_options) with -Wl. - Compile .c and .S files into .x programs. - -2011-05-04 Joseph Myers - - * configure: Regenerate. - -2010-04-26 Mike Frysinger - - * Makefile.in (arch): Set to @sim_arch@. - * configure.ac: Delete arch logic and include ../configure.tgt. - * configure: Regenerated. - * lib/sim-defs.exp (sim_run): Default sim to ../arch/run. - -2009-08-22 Ralf Wildenhues - - * configure: Regenerate. - -2009-01-18 Hans-Peter Nilsson - - * lib/sim-defs.exp (run_sim_test): New option progopts. - -2005-01-11 Andrew Cagney - - * configure: Regenerated to track ../common/aclocal.m4 changes. - -2005-01-07 Andrew Cagney - - * configure.ac: Rename configure.in, require autoconf 2.59. - * configure: Re-generate. - - * configure.in: Pass literal subdirectories to AC_CONFIG_SUBDIRS. - * configure: Re-generate. - - * fr30-elf, d30v-elf: Delete directory. - -2004-11-16 Hans-Peter Nilsson - - * lib/sim-defs.exp (run_sim_test): Make multiple "output" - specifications concatenate, not override. - Support "xfail" and "kfail". - -2004-10-26 Nick Clifton - - * lib/sim-defs.exp (sim_run): Add support for the "rawsid" - protocol. - -2004-09-13 DJ Delorie - - * lib/sim-defs.exp (run_sim_test): Add global_as_options, - global_ld_options, and global_sim_options to all test cases, if - defined. - -2004-05-12 Ben Elliston - - * lib/sim-defs.exp: Remove stray semicolons. - -2004-01-26 Chris Demetriou - - * sim/mips: New directory. Tests for the MIPS simulator. - -2004-01-23 Ben Elliston - - * lib/sim-defs.exp (run_sim_test): Delete the .o and .x files if a - test passes. - -2003-08-20 Michael Snyder - On behalf of Dave Brolley - - * sim/frv: New testsuite. - * frv-elf: New testsuite. - -2003-07-09 Michael Snyder - - * sim/sh: New directory. Tests for Renesas sh family. - -2003-04-13 Michael Snyder - - * sim/h8300: New directory. Tests for Renesas h8/300 family. - -2002-06-16 Andrew Cagney - - * configure: Regenerated to track ../common/aclocal.m4 changes. - -2001-07-31 Ben Elliston - - * lib/sim-defs.exp (run_sim_test): Include a description such as - "assembling" or "linking" that identifies the phase a test fails - in, for easier analysis of failures. - -2000-11-01 Dave Brolley - - * lib/sim-defs.exp (run_sm_test): Correct comment. "output" and - "xerror" options do not use a list of machines. Clear options from - previous test case. Use "$cpu_option" to identify the machine to the - assembler, if specified. - -Tue May 23 21:39:23 2000 Andrew Cagney - - * configure: Regenerated to track ../common/aclocal.m4 changes. - -1999-09-15 Doug Evans - - * sim/arm/b.cgs: New testcase. - * sim/arm/bic.cgs: New testcase. - * sim/arm/bl.cgs: New testcase. - -Thu Sep 2 18:15:53 1999 Andrew Cagney - - * configure: Regenerated to track ../common/aclocal.m4 changes. - -1999-08-30 Doug Evans - - * lib/sim-defs.exp (run_sim_test): Rename all_machs arg to - requested_machs, now is list of machs to run tests for. - Delete locals AS,ASFLAGS,LD,LDFLAGS. Use target_assemble - and target_link instead. - -Fri Feb 5 12:41:11 1999 Doug Evans - - * lib/sim-defs.exp (sim_run): Print simulator arguments log message. - -1999-01-05 Doug Evans - - * lib/sim-defs.exp (run_sim_test): New arg all_machs. - -1998-12-14 Doug Evans - - * lib/sim-defs.exp (run_sim_test): New option xerror, for expected - errors. Translate \n sequences in expected output to newline char. - (slurp_options): Make parentheses optional. - (sim_run): Look for board_info sim,options. - -Wed Nov 18 10:50:19 1998 Andrew Cagney - - * common/bits-gen.c (main): Add BYTE_ORDER so that it matches - recent sim/common/sim-basics.h changes. - * common/Makefile.in: Update. - -Fri Oct 30 00:37:31 1998 Felix Lee - - * lib/sim-defs.exp (sim_run): download target program to remote - host, if necessary. for unix-driven win32 testing. - -Fri Jul 31 17:49:13 1998 Felix Lee - - * lib/sim-defs.exp (sim_run): remote_spawn, use writeto instead of - writeonly. - -Fri Jul 24 09:40:34 1998 Doug Evans - - * Makefile.in (clean,mostlyclean): Change leading spaces to a tab. - -Tue Jun 16 15:44:01 1998 Jillian Ye - - * lib/sim-defs.exp: Print out timeout setting info when "-v" is used. - -Thu Jun 11 15:24:53 1998 Doug Evans - - * lib/sim-defs.exp (sim_run): Argument env_vals renamed to options, - which is now a list of options controlling the behaviour of sim_run. - -Mon Jun 1 18:54:22 1998 Frank Ch. Eigler - - * lib/sim-defs.exp (sim_run): Add possible environment variable - list to simulator run. - -Thu May 28 14:59:46 1998 Jillian Ye - - * Makefile.in: Take RUNTEST out of FLAG_TO_PASS - so that make check can be invoked recursively. - -Thu May 14 11:48:35 1998 Doug Evans - - * config/default.exp (CC,SIM): Delete. - - * lib/sim-defs.exp (sim_run): Fix handling of output redirection. - New arg prog_opts. All callers updated. - -Fri May 8 18:10:28 1998 Jillian Ye - - * Makefile.in: Made "check" the target of two - dependencies (test1, test2) so that test2 get a chance to - run even when test1 failed if "make -k check" is used. - -Fri May 8 14:41:28 1998 Doug Evans - - * lib/sim-defs.exp (sim_version): Simplify. - (sim_run): Implement. - (run_sim_test): Use sim_run. - (sim_compile): New proc. - -Mon May 4 17:59:11 1998 Frank Ch. Eigler - - * config/default.exp: Added C compiler settings. - -Wed Apr 22 12:26:28 1998 Doug Evans - - * Makefile.in (TARGET_FLAGS_TO_PASS): Delete LIBS, LDFLAGS. - -Tue Apr 21 10:49:03 1998 Doug Evans - - * lib/sim-defs.exp (run_sim_test): Don't exit early if one mach fails, - try all machs. - -Wed Feb 25 11:01:17 1998 Doug Evans - - * Makefile.in (RUNTEST): Fix path to runtest. - -Tue Feb 17 12:46:05 1998 Doug Evans - - * config/default.exp: New file. - * lib/sim-defs.exp: New file. - - * Makefile.in (build_alias): Define. - (arch): Define. - (RUNTEST_FOR_TARGET): Delete. - (RUNTEST): Fix. - (check): Depend on site.exp. Run dejagnu. - (site.exp): New target. - * configure.in (arch): Define from target_cpu. - * configure: Regenerate. - -Wed Sep 17 10:21:26 1997 Andrew Cagney - - * common/bits-gen.c (gen_bit): Pass in the full name of the macro. - (gen_mask): Ditto. - - * common/bits-tst.c (main): Add tests for LSSEXT, MSSEXT. - (calc): Add support for 8 bit version of macros. - (main): Add tests for 8 bit versions of macros. - (check_sext): Check SEXT of zero clears bits. - - * common/bits-gen.c (main): Generate tests for 8 bit versions of - macros. - -Thu Sep 11 13:04:40 1997 Andrew Cagney - - * common/Make-common.in: New file, provide generic rules for - running checks. - -Mon Sep 1 16:43:55 1997 Andrew Cagney - - * configure.in (configdirs): Test for the target directory instead - of matching on a target. diff --git a/sim/testsuite/ChangeLog-2021 b/sim/testsuite/ChangeLog-2021 new file mode 100644 index 0000000..7265ed8 --- /dev/null +++ b/sim/testsuite/ChangeLog-2021 @@ -0,0 +1,475 @@ +2021-06-14 Mike Frysinger + + * common/local.mk (%D%/bits32m0.c, %D%/bits32m31.c, %D%/bits64m0.c, + %D%/bits64m63.c): Use AM_V_GEN & AM_V_at wrappers. + +2021-05-07 Dimitar Dimitrov + + * local.mk (%C%_CPPFLAGS): Add ../bfd include path. + +2021-04-08 Mike Frysinger + + * lib/sim-defs.exp (run_sim_test): Set status to unsupported if + $return_code is 77. + +2021-04-08 Mike Frysinger + + * lib/sim-defs.exp (run_sim_test): Return if sim_tool_path does not + exist. + +2021-04-08 Mike Frysinger + + * lib/sim-defs.exp (sim_tool_path): New function. + (sim_run): Set sim to [sim_tool_path]. + +2021-04-03 Mike Frysinger + + * lib/sim-defs.exp (run_sim_test): Convert examples to binaries. + +2021-04-03 Mike Frysinger + + * local.mk: Include %D%/common/local.mk. + * common/Makefile.in: Removed. + * common/local.mk: New file. + +2021-03-07 Mike Frysinger + + * Makefile.in: Removed. + * lib/sim-defs.exp (sim): Update default path. + * local.mk: New file based on Makefile.in. + +2021-02-13 Mike Frysinger + + * Makefile.in (arch): Delete. + (site.exp): Do not output $arch. + +2021-02-04 Mike Frysinger + + * riscv/: New directory. + +2021-01-15 Mike Frysinger + + * Makefile.in (site.exp): Delete tool setting. + * sim/*/: Move subdirs up a directory. + +2021-01-15 Mike Frysinger + + * configure, configure.ac: Delete. + * Makefile.in (Makefile, config.status): Switch to ../config.status. + +2021-01-15 Mike Frysinger + + * configure.ac (target): Delete d10v-*-elf case. + * configure: Regenerate. + * d10v-elf/: Move directory ... + * sim/d10v/: ... here. + +2021-01-15 Mike Frysinger + + * configure.ac (target): Delete mips64el-*-elf case. + * configure: Regenerate. + * mips64el-elf/: Delete directory. + +2021-01-15 Mike Frysinger + + * configure.ac (target): Delete frv-*-elf case. + * configure: Regenerate. + * frv-elf/: Delete directory. + +2021-01-15 Mike Frysinger + + * configure.ac (target): Delete m32r-*-elf case. + * configure: Regenerate. + * m32r-elf/: Delete directory. + +2021-01-15 Mike Frysinger + + * lib/sim-defs.exp (sim_run): Delete status and return return_code. + (run_sim_test): Define status option. Change sim_run return to + return_code. Define status. Log return_code. + +2021-01-11 Mike Frysinger + + * common/alu-tst.c: Include stdlib.h. + (PACKAGE): Define. + (print_hex): Change printf to use %llx. + * common/bits-gen.c: Include stdlib.h, string.h, and unistd.h. + (gen_struct): Change long long to unsigned64. + (gen_bit): Change bit cast to bit mask. Change printf to use %llx. + (gen_mask): Likewise. + (usage): Delete default case. + (main): Change WITH_HOST_WORD_BITSIZE printf from %d to %zu. Emit + PACKAGE define and stdlib.h & string.h includes. + * common/bits-tst.c (calc): Change printf to use %llx. + (check_sext, check_rot, check_extract, check_bits): Likewise. + +2021-01-09 Mike Frysinger + + * configure: Regenerate. + * sim/sh64/: Delete. + +2021-01-05 Mike Frysinger + + * sim/fr30/: Delete. + +2021-01-05 Mike Frysinger + + * common/Make-common.in: Delete. + +2021-01-04 Mike Frysinger + + * configure: Regenerate. + +2020-10-06 Andrew Burgess + + * configure: Regnerate. + * configure.ac (AC_CONFIG_AUX_DIR): Update. + +2020-08-04 David Faust + Jose E. Marchesi + + * configure: Regenerate. + * sim/bpf: New directory. + +2020-07-29 Simon Marchi + + * configure: Re-generate. + +2019-12-19 Tom Tromey + + PR build/24572: + * Makefile.in (install-strip): New target. + +2019-09-23 Dimitar Dimitrov + + * configure: Regenerate. + +2017-12-12 Stafford Horne + Peter Gavin + + * configure: Regenerated. + +2016-01-10 Mike Frysinger + + * configure: Regenerate. + +2016-01-02 Mike Frysinger + + * common/bits-gen.c (main): Change BIG_ENDIAN to BFD_ENDIAN_BIG and + LITTLE_ENDIAN and BFD_ENDIAN_LITTLE. + +2015-11-24 Nick Clifton + + * configure: Regenerate. + * sim/aarch64: New directory. + +2015-11-14 Mike Frysinger + + * lib/sim-defs.exp (slurp_options): Pull in global subdir/srcdir. + Replace $srcdir and $subdir in the read option. + +2015-04-13 Hans-Peter Nilsson + + * lib/sim-defs.exp (sim_init): Unset target ldscript here. + +2015-03-30 Mike Frysinger + + * configure.ac: Add d10v-*-elf. + * configure: Regenerate. + +2015-03-29 Mike Frysinger + + * lib/sim-defs.exp (run_sim_test): Declare seen_output as 0. When + the test has an output keyword, set it to 1. Set default output only + when seen_output is 0. + +2015-03-29 Mike Frysinger + + * configure: Regenerate. + +2015-03-28 Mike Frysinger + + * configure: Regenerate. + +2015-03-28 James Bowman + + * configure: Regenerate. + +2014-03-10 Mike Frysinger + + * configure: Regenerate. + +2014-03-04 Mike Frysinger + + * common/bits-gen.c (main): Change to new style prototype. + +2013-09-23 Alan Modra + + * configure: Regenerate. + +2012-06-15 Joel Brobecker + + * configure: Regenerate. + +2012-03-24 Mike Frysinger + + * configure: Regenerate. + +2012-03-18 Mike Frysinger + + * .gitignore: New file. + +2011-10-17 Mike Frysinger + + * configure: Regenerate after bfin testsuite update. + +2011-05-16 Mike Frysinger + + * lib/sim-defs.exp: Support cc tag in test files. + (run_sim_test): Support global_cc_options in boards files. Convert + assembler options into compiler options (c_as_options) with -Wa. + Convert linker options into compiler options (c_ld_options) with -Wl. + Compile .c and .S files into .x programs. + +2011-05-04 Joseph Myers + + * configure: Regenerate. + +2010-04-26 Mike Frysinger + + * Makefile.in (arch): Set to @sim_arch@. + * configure.ac: Delete arch logic and include ../configure.tgt. + * configure: Regenerated. + * lib/sim-defs.exp (sim_run): Default sim to ../arch/run. + +2009-08-22 Ralf Wildenhues + + * configure: Regenerate. + +2009-01-18 Hans-Peter Nilsson + + * lib/sim-defs.exp (run_sim_test): New option progopts. + +2005-01-11 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +2005-01-07 Andrew Cagney + + * configure.ac: Rename configure.in, require autoconf 2.59. + * configure: Re-generate. + + * configure.in: Pass literal subdirectories to AC_CONFIG_SUBDIRS. + * configure: Re-generate. + + * fr30-elf, d30v-elf: Delete directory. + +2004-11-16 Hans-Peter Nilsson + + * lib/sim-defs.exp (run_sim_test): Make multiple "output" + specifications concatenate, not override. + Support "xfail" and "kfail". + +2004-10-26 Nick Clifton + + * lib/sim-defs.exp (sim_run): Add support for the "rawsid" + protocol. + +2004-09-13 DJ Delorie + + * lib/sim-defs.exp (run_sim_test): Add global_as_options, + global_ld_options, and global_sim_options to all test cases, if + defined. + +2004-05-12 Ben Elliston + + * lib/sim-defs.exp: Remove stray semicolons. + +2004-01-26 Chris Demetriou + + * sim/mips: New directory. Tests for the MIPS simulator. + +2004-01-23 Ben Elliston + + * lib/sim-defs.exp (run_sim_test): Delete the .o and .x files if a + test passes. + +2003-08-20 Michael Snyder + On behalf of Dave Brolley + + * sim/frv: New testsuite. + * frv-elf: New testsuite. + +2003-07-09 Michael Snyder + + * sim/sh: New directory. Tests for Renesas sh family. + +2003-04-13 Michael Snyder + + * sim/h8300: New directory. Tests for Renesas h8/300 family. + +2002-06-16 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +2001-07-31 Ben Elliston + + * lib/sim-defs.exp (run_sim_test): Include a description such as + "assembling" or "linking" that identifies the phase a test fails + in, for easier analysis of failures. + +2000-11-01 Dave Brolley + + * lib/sim-defs.exp (run_sm_test): Correct comment. "output" and + "xerror" options do not use a list of machines. Clear options from + previous test case. Use "$cpu_option" to identify the machine to the + assembler, if specified. + +Tue May 23 21:39:23 2000 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +1999-09-15 Doug Evans + + * sim/arm/b.cgs: New testcase. + * sim/arm/bic.cgs: New testcase. + * sim/arm/bl.cgs: New testcase. + +Thu Sep 2 18:15:53 1999 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +1999-08-30 Doug Evans + + * lib/sim-defs.exp (run_sim_test): Rename all_machs arg to + requested_machs, now is list of machs to run tests for. + Delete locals AS,ASFLAGS,LD,LDFLAGS. Use target_assemble + and target_link instead. + +Fri Feb 5 12:41:11 1999 Doug Evans + + * lib/sim-defs.exp (sim_run): Print simulator arguments log message. + +1999-01-05 Doug Evans + + * lib/sim-defs.exp (run_sim_test): New arg all_machs. + +1998-12-14 Doug Evans + + * lib/sim-defs.exp (run_sim_test): New option xerror, for expected + errors. Translate \n sequences in expected output to newline char. + (slurp_options): Make parentheses optional. + (sim_run): Look for board_info sim,options. + +Wed Nov 18 10:50:19 1998 Andrew Cagney + + * common/bits-gen.c (main): Add BYTE_ORDER so that it matches + recent sim/common/sim-basics.h changes. + * common/Makefile.in: Update. + +Fri Oct 30 00:37:31 1998 Felix Lee + + * lib/sim-defs.exp (sim_run): download target program to remote + host, if necessary. for unix-driven win32 testing. + +Fri Jul 31 17:49:13 1998 Felix Lee + + * lib/sim-defs.exp (sim_run): remote_spawn, use writeto instead of + writeonly. + +Fri Jul 24 09:40:34 1998 Doug Evans + + * Makefile.in (clean,mostlyclean): Change leading spaces to a tab. + +Tue Jun 16 15:44:01 1998 Jillian Ye + + * lib/sim-defs.exp: Print out timeout setting info when "-v" is used. + +Thu Jun 11 15:24:53 1998 Doug Evans + + * lib/sim-defs.exp (sim_run): Argument env_vals renamed to options, + which is now a list of options controlling the behaviour of sim_run. + +Mon Jun 1 18:54:22 1998 Frank Ch. Eigler + + * lib/sim-defs.exp (sim_run): Add possible environment variable + list to simulator run. + +Thu May 28 14:59:46 1998 Jillian Ye + + * Makefile.in: Take RUNTEST out of FLAG_TO_PASS + so that make check can be invoked recursively. + +Thu May 14 11:48:35 1998 Doug Evans + + * config/default.exp (CC,SIM): Delete. + + * lib/sim-defs.exp (sim_run): Fix handling of output redirection. + New arg prog_opts. All callers updated. + +Fri May 8 18:10:28 1998 Jillian Ye + + * Makefile.in: Made "check" the target of two + dependencies (test1, test2) so that test2 get a chance to + run even when test1 failed if "make -k check" is used. + +Fri May 8 14:41:28 1998 Doug Evans + + * lib/sim-defs.exp (sim_version): Simplify. + (sim_run): Implement. + (run_sim_test): Use sim_run. + (sim_compile): New proc. + +Mon May 4 17:59:11 1998 Frank Ch. Eigler + + * config/default.exp: Added C compiler settings. + +Wed Apr 22 12:26:28 1998 Doug Evans + + * Makefile.in (TARGET_FLAGS_TO_PASS): Delete LIBS, LDFLAGS. + +Tue Apr 21 10:49:03 1998 Doug Evans + + * lib/sim-defs.exp (run_sim_test): Don't exit early if one mach fails, + try all machs. + +Wed Feb 25 11:01:17 1998 Doug Evans + + * Makefile.in (RUNTEST): Fix path to runtest. + +Tue Feb 17 12:46:05 1998 Doug Evans + + * config/default.exp: New file. + * lib/sim-defs.exp: New file. + + * Makefile.in (build_alias): Define. + (arch): Define. + (RUNTEST_FOR_TARGET): Delete. + (RUNTEST): Fix. + (check): Depend on site.exp. Run dejagnu. + (site.exp): New target. + * configure.in (arch): Define from target_cpu. + * configure: Regenerate. + +Wed Sep 17 10:21:26 1997 Andrew Cagney + + * common/bits-gen.c (gen_bit): Pass in the full name of the macro. + (gen_mask): Ditto. + + * common/bits-tst.c (main): Add tests for LSSEXT, MSSEXT. + (calc): Add support for 8 bit version of macros. + (main): Add tests for 8 bit versions of macros. + (check_sext): Check SEXT of zero clears bits. + + * common/bits-gen.c (main): Generate tests for 8 bit versions of + macros. + +Thu Sep 11 13:04:40 1997 Andrew Cagney + + * common/Make-common.in: New file, provide generic rules for + running checks. + +Mon Sep 1 16:43:55 1997 Andrew Cagney + + * configure.in (configdirs): Test for the target directory instead + of matching on a target. diff --git a/sim/testsuite/aarch64/ChangeLog b/sim/testsuite/aarch64/ChangeLog deleted file mode 100644 index 9a6c834..0000000 --- a/sim/testsuite/aarch64/ChangeLog +++ /dev/null @@ -1,91 +0,0 @@ -2021-04-08 Mike Frysinger - - * allinsn.exp (arch): Delete. - -2021-02-13 Mike Frysinger - - * allinsn.exp: Define arch. - -2017-04-22 Jim Wilson - - * fcvtz.s, fstur.s, ldn_single.s, ldnr.s, mla.s, mls.s, uzp.s: Align - data. - * sumulh.s: Delete unnecessary data alignment. - * stn_single.s: Align data. Fix unaligned ldr insns. Adjust cmp - arguments to match change. - * ldn_multiple.s, stn_multiple.s: New. - -2017-04-08 Jim Wilson - - * fcvtl.s: New. - - * fcmXX.s: New. - -2017-03-25 Jim Wilson - - * adds.s: Add checks for values -2 and 1, where C is not set. - -2017-03-03 Jim Wilson - - * sumov.s: Correct compare test values. - * sumulh.s: New. - -2017-02-25 Jim Wilson - - * sumov.s: New. - - * cnt.s: New. - -2017-02-19 Jim Wilson - - * bit.s: Change cmp immediates to account for addv bug fix. - * cmtst.s, ldn_single.s, stn_single.s: Likewise. - * xtl.s: New. - -2017-02-14 Jim Wilson - - * mla.s: New. - - * bit.s: New. - - * ldn_single.s: New. - * ldnr.s: New. - * stn_single.s: New. - -2017-01-23 Jim Wilson - - * cmtst.s: New. - -2017-01-17 Jim Wilson - - * addv.s: New. - * xtn.s: New. - -2017-01-09 Jim Wilson - - * uzp.s: New. - -2017-01-04 Jim Wilson - - * fcsel.s: New. - * fcvtz.s: New. - * fminnm.s: New. - * mls.s: New. - * mul.s: New. - -2016-12-21 Jim Wilson - - * fcmp.s: New. - -2016-12-13 Jim Wilson - - * testutils.inc (pass): Move .Lpass to start. - (fail): Move .Lfail to start. Return 1 instead of 0. - (start): Moved .Lpass and .Lfail to here. - * adds.s: New. - * fstur.s: New. - * tbnz.s: New. - -2015-11-24 Nick Clifton - - * pass.s, allinsn.exp, testutils.inc: New files. diff --git a/sim/testsuite/aarch64/ChangeLog-2021 b/sim/testsuite/aarch64/ChangeLog-2021 new file mode 100644 index 0000000..9a6c834 --- /dev/null +++ b/sim/testsuite/aarch64/ChangeLog-2021 @@ -0,0 +1,91 @@ +2021-04-08 Mike Frysinger + + * allinsn.exp (arch): Delete. + +2021-02-13 Mike Frysinger + + * allinsn.exp: Define arch. + +2017-04-22 Jim Wilson + + * fcvtz.s, fstur.s, ldn_single.s, ldnr.s, mla.s, mls.s, uzp.s: Align + data. + * sumulh.s: Delete unnecessary data alignment. + * stn_single.s: Align data. Fix unaligned ldr insns. Adjust cmp + arguments to match change. + * ldn_multiple.s, stn_multiple.s: New. + +2017-04-08 Jim Wilson + + * fcvtl.s: New. + + * fcmXX.s: New. + +2017-03-25 Jim Wilson + + * adds.s: Add checks for values -2 and 1, where C is not set. + +2017-03-03 Jim Wilson + + * sumov.s: Correct compare test values. + * sumulh.s: New. + +2017-02-25 Jim Wilson + + * sumov.s: New. + + * cnt.s: New. + +2017-02-19 Jim Wilson + + * bit.s: Change cmp immediates to account for addv bug fix. + * cmtst.s, ldn_single.s, stn_single.s: Likewise. + * xtl.s: New. + +2017-02-14 Jim Wilson + + * mla.s: New. + + * bit.s: New. + + * ldn_single.s: New. + * ldnr.s: New. + * stn_single.s: New. + +2017-01-23 Jim Wilson + + * cmtst.s: New. + +2017-01-17 Jim Wilson + + * addv.s: New. + * xtn.s: New. + +2017-01-09 Jim Wilson + + * uzp.s: New. + +2017-01-04 Jim Wilson + + * fcsel.s: New. + * fcvtz.s: New. + * fminnm.s: New. + * mls.s: New. + * mul.s: New. + +2016-12-21 Jim Wilson + + * fcmp.s: New. + +2016-12-13 Jim Wilson + + * testutils.inc (pass): Move .Lpass to start. + (fail): Move .Lfail to start. Return 1 instead of 0. + (start): Moved .Lpass and .Lfail to here. + * adds.s: New. + * fstur.s: New. + * tbnz.s: New. + +2015-11-24 Nick Clifton + + * pass.s, allinsn.exp, testutils.inc: New files. diff --git a/sim/testsuite/arm/ChangeLog b/sim/testsuite/arm/ChangeLog deleted file mode 100644 index 89fab48..0000000 --- a/sim/testsuite/arm/ChangeLog +++ /dev/null @@ -1,133 +0,0 @@ -2021-04-08 Mike Frysinger - - * allinsn.exp (arch): Delete. - * iwmmxt/iwmmxt.exp, misc.exp, thumb/allthumb.exp, xscale/xscale.exp: - Likewise. - -2021-02-13 Mike Frysinger - - * allinsn.exp, iwmmxt/iwmmxt.exp, misc.exp, thumb/allthumb.ex, - xscale/xscale.exp: Define arch. - -2013-05-07 Jayant Sonar - Kaushik Phatak - - * movw-movt.ms: New file: Test movw & movt instructions. - -2011-07-01 Nick Clifton - - PR sim/12737 - * iwmmxt/wcmpgt.cgs: Remove expectation of failure. - * iwmmxt/wmac.cgs: Remove expectation of failure. - * iwmmxt/wsra.cgs: Remove expectation of failure. - * xscale/blx.cgs: Remove expectation of failure. - -2011-05-11 Joseph Myers - Hans-Peter Nilsson - - PR sim/12737 - * iwmmxt/wcmpgt.cgs, iwmmxt/wmac.cgs, - iwmmxt/wsra.cgs, xscale/blx.cgs: Kfail. - -2011-05-04 Joseph Myers - - * allinsn.exp (xscale*-*-*): Don't handle target. - * misc.exp (thumb*-*-*, xscale*-*-*): Don't handle - targets. - * iwmmxt/iwmmxt.exp: Test for arm*-*-* instead of - xscale*-*-*. - * thumb/allthumb.exp (thumb*-*-*): Don't handle target. - * xscale/xscale.exp: Test for arm*-*-* instead of - xscale*-*-*. - -2003-04-01 Nick Clifton - - * .: New directory: Tests for ARM simulator. - * allinsn.exp: New file: Test script. - * testutils.inc: New file: Test macros. - * adc.cgs, add.cgs, and.cgs, - b.cgs, bic.cgs, bl.cgs, bx.cgs, - cmn.cgs, cmp.cgs, eor.cgs, - hello.ms, ldm.cgs, ldr.cgs, - ldrb.cgs, ldrh.cgs, ldrsb.cgs, - ldrsh.cgs, misaligned1.ms, misaligned2.ms, - misaligned3.ms, misc.exp, mla.cgs, - mov.cgs, mrs.cgs, msr.cgs, - mul.cgs, mvn.cgs, orr.cgs, - rsb.cgs, rsc.cgs, sbc.cgs, - smlal.cgs, smull.cgs, stm.cgs, - str.cgs, strb.cgs, strh.cgs, - sub.cgs, swi.cgs, swp.cgs, - swpb.cgs, teq.cgs, tst.cgs, - umlal.cgs, umull.cgs: New files: ARM tests. - * iwmmxt: New Directory: Tests for iWMMXt. - * iwmmxt/iwmmxt.exp: New file: Test script. - * iwmmxt/testutils.inc: New file: Test macros. - * iwmmxt/tbcst.cgs, iwmmxt/textrm.cgs, - iwmmxt/tinsr.cgs, iwmmxt/tmia.cgs, - iwmmxt/tmiaph.cgs, iwmmxt/tmiaxy.cgs, - iwmmxt/tmovmsk.cgss, iwmmxt/wacc.cgs, - iwmmxt/wadd.cgs, iwmmxt/waligni.cgs, - iwmmxt/walignr.cgs, iwmmxt/wand.cgs, - iwmmxt/wandn.cgs, iwmmxt/wavg2.cgs, - iwmmxt/wcmpeq.cgs, iwmmxt/wcmpgt.cgs, - iwmmxt/wmac.cgs, iwmmxt/wmadd.cgs, - iwmmxt/wmax.cgs, iwmmxt/wmin.cgs, - iwmmxt/wmov.cgs, iwmmxt/wmul.cgs, - iwmmxt/wor.cgs, iwmmxt/wpack.cgs, - iwmmxt/wror.cgs, iwmmxt/wsad.cgs, - iwmmxt/wshufh.cgs, iwmmxt/wsll.cgs, - iwmmxt/wsra.cgs, iwmmxt/wsrl.cgs, - iwmmxt/wsub.cgs, iwmmxt/wunpckeh.cgs, - iwmmxt/wunpckel.cgs, iwmmxt/wunpckih.cgs, - iwmmxt/wunpckil.cgs, iwmmxt/wxor.cgs, - iwmmxt/wzero.cgs: New files: iWMMXt tests. - * thumb: New Directory: Thumb tests. - * thumb/allthumb.exp: New file: Test script. - * thumb/testutils.inc: New file: Test macros. - * thumb/adc.cgs, thumb/add-hd-hs.cgs, - thumb/add-hd-rs.cgs, thumb/add-rd-hs.cgs, - thumb/add-sp.cgs, thumb/add.cgs, - thumb/addi.cgs, thumb/addi8.cgs, - thumb/and.cgs, thumb/asr.cgs, thumb/b.cgs, - thumb/bcc.cgs, thumb/bcs.cgs, - thumb/beq.cgs, thumb/bge.cgs, - thumb/bgt.cgs, thumb/bhi.cgs, - thumb/bic.cgs, thumb/bl-hi.cgs, - thumb/bl-lo.cgs, thumb/ble.cgs, - thumb/bls.cgs, thumb/blt.cgs, - thumb/bmi.cgs, thumb/bne.cgs, - thumb/bpl.cgs, thumb/bvc.cgs, - thumb/bvs.cgs, thumb/bx-hs.cgs, - thumb/bx-rs.cgs, thumb/cmn.cgs, - thumb/cmp-hd-hs.cgs, thumb/cmp-hd-rs.cgs, - thumb/cmp-rd-hs.cgs, thumb/cmp.cgs, - thumb/eor.cgs, thumb/lda-pc.cgs, - thumb/lda-sp.cgs, thumb/ldmia.cgs, - thumb/ldr-imm.cgs, thumb/ldr-pc.cgs, - thumb/ldr-sprel.cgs, thumb/ldr.cgs, - thumb/ldrb-imm.cgs, thumb/ldrb.cgs, - thumb/ldrh-imm.cgs, thumb/ldrh.cgs, - thumb/ldsb.cgs, thumb/ldsh.cgs, - thumb/lsl.cgs, thumb/lsr.cgs, - thumb/mov-hd-hs.cgs, thumb/mov-hd-rs.cgs, - thumb/mov-rd-hs.cgs, thumb/mov.cgs, - thumb/mul.cgs, thumb/mvn.cgs, - thumb/neg.cgs, thumb/orr.cgs, - thumb/pop-pc.cgs, thumb/pop.cgs, - thumb/push-lr.cgs, thumb/push.cgs, - thumb/ror.cgs, thumb/sbc.cgs, - thumb/stmia.cgs, thumb/str-imm.cgs, - thumb/str-sprel.cgs, thumb/str.cgs, - thumb/strb-imm.cgs, thumb/strb.cgs, - thumb/strh-imm.cgs, thumb/strh.cgs, - thumb/sub-sp.cgs, thumb/sub.cgs, - thumb/subi.cgs, thumb/subi8.cgs, - thumb/swi.cgs, thumb/tst.cgs: New files: Thumb - tests. - * xscale: New directory. - * xscale/xscale.exp: New file: Test script. - * xscale/testutils.inc: New file: Test macros. - * xscale/blx.cgs, xscale/mia.cgs, - xscale/miaph.cgs, xscale/miaxy.cgs, - xscale/mra.cgs: New files: XScale tests. diff --git a/sim/testsuite/arm/ChangeLog-2021 b/sim/testsuite/arm/ChangeLog-2021 new file mode 100644 index 0000000..89fab48 --- /dev/null +++ b/sim/testsuite/arm/ChangeLog-2021 @@ -0,0 +1,133 @@ +2021-04-08 Mike Frysinger + + * allinsn.exp (arch): Delete. + * iwmmxt/iwmmxt.exp, misc.exp, thumb/allthumb.exp, xscale/xscale.exp: + Likewise. + +2021-02-13 Mike Frysinger + + * allinsn.exp, iwmmxt/iwmmxt.exp, misc.exp, thumb/allthumb.ex, + xscale/xscale.exp: Define arch. + +2013-05-07 Jayant Sonar + Kaushik Phatak + + * movw-movt.ms: New file: Test movw & movt instructions. + +2011-07-01 Nick Clifton + + PR sim/12737 + * iwmmxt/wcmpgt.cgs: Remove expectation of failure. + * iwmmxt/wmac.cgs: Remove expectation of failure. + * iwmmxt/wsra.cgs: Remove expectation of failure. + * xscale/blx.cgs: Remove expectation of failure. + +2011-05-11 Joseph Myers + Hans-Peter Nilsson + + PR sim/12737 + * iwmmxt/wcmpgt.cgs, iwmmxt/wmac.cgs, + iwmmxt/wsra.cgs, xscale/blx.cgs: Kfail. + +2011-05-04 Joseph Myers + + * allinsn.exp (xscale*-*-*): Don't handle target. + * misc.exp (thumb*-*-*, xscale*-*-*): Don't handle + targets. + * iwmmxt/iwmmxt.exp: Test for arm*-*-* instead of + xscale*-*-*. + * thumb/allthumb.exp (thumb*-*-*): Don't handle target. + * xscale/xscale.exp: Test for arm*-*-* instead of + xscale*-*-*. + +2003-04-01 Nick Clifton + + * .: New directory: Tests for ARM simulator. + * allinsn.exp: New file: Test script. + * testutils.inc: New file: Test macros. + * adc.cgs, add.cgs, and.cgs, + b.cgs, bic.cgs, bl.cgs, bx.cgs, + cmn.cgs, cmp.cgs, eor.cgs, + hello.ms, ldm.cgs, ldr.cgs, + ldrb.cgs, ldrh.cgs, ldrsb.cgs, + ldrsh.cgs, misaligned1.ms, misaligned2.ms, + misaligned3.ms, misc.exp, mla.cgs, + mov.cgs, mrs.cgs, msr.cgs, + mul.cgs, mvn.cgs, orr.cgs, + rsb.cgs, rsc.cgs, sbc.cgs, + smlal.cgs, smull.cgs, stm.cgs, + str.cgs, strb.cgs, strh.cgs, + sub.cgs, swi.cgs, swp.cgs, + swpb.cgs, teq.cgs, tst.cgs, + umlal.cgs, umull.cgs: New files: ARM tests. + * iwmmxt: New Directory: Tests for iWMMXt. + * iwmmxt/iwmmxt.exp: New file: Test script. + * iwmmxt/testutils.inc: New file: Test macros. + * iwmmxt/tbcst.cgs, iwmmxt/textrm.cgs, + iwmmxt/tinsr.cgs, iwmmxt/tmia.cgs, + iwmmxt/tmiaph.cgs, iwmmxt/tmiaxy.cgs, + iwmmxt/tmovmsk.cgss, iwmmxt/wacc.cgs, + iwmmxt/wadd.cgs, iwmmxt/waligni.cgs, + iwmmxt/walignr.cgs, iwmmxt/wand.cgs, + iwmmxt/wandn.cgs, iwmmxt/wavg2.cgs, + iwmmxt/wcmpeq.cgs, iwmmxt/wcmpgt.cgs, + iwmmxt/wmac.cgs, iwmmxt/wmadd.cgs, + iwmmxt/wmax.cgs, iwmmxt/wmin.cgs, + iwmmxt/wmov.cgs, iwmmxt/wmul.cgs, + iwmmxt/wor.cgs, iwmmxt/wpack.cgs, + iwmmxt/wror.cgs, iwmmxt/wsad.cgs, + iwmmxt/wshufh.cgs, iwmmxt/wsll.cgs, + iwmmxt/wsra.cgs, iwmmxt/wsrl.cgs, + iwmmxt/wsub.cgs, iwmmxt/wunpckeh.cgs, + iwmmxt/wunpckel.cgs, iwmmxt/wunpckih.cgs, + iwmmxt/wunpckil.cgs, iwmmxt/wxor.cgs, + iwmmxt/wzero.cgs: New files: iWMMXt tests. + * thumb: New Directory: Thumb tests. + * thumb/allthumb.exp: New file: Test script. + * thumb/testutils.inc: New file: Test macros. + * thumb/adc.cgs, thumb/add-hd-hs.cgs, + thumb/add-hd-rs.cgs, thumb/add-rd-hs.cgs, + thumb/add-sp.cgs, thumb/add.cgs, + thumb/addi.cgs, thumb/addi8.cgs, + thumb/and.cgs, thumb/asr.cgs, thumb/b.cgs, + thumb/bcc.cgs, thumb/bcs.cgs, + thumb/beq.cgs, thumb/bge.cgs, + thumb/bgt.cgs, thumb/bhi.cgs, + thumb/bic.cgs, thumb/bl-hi.cgs, + thumb/bl-lo.cgs, thumb/ble.cgs, + thumb/bls.cgs, thumb/blt.cgs, + thumb/bmi.cgs, thumb/bne.cgs, + thumb/bpl.cgs, thumb/bvc.cgs, + thumb/bvs.cgs, thumb/bx-hs.cgs, + thumb/bx-rs.cgs, thumb/cmn.cgs, + thumb/cmp-hd-hs.cgs, thumb/cmp-hd-rs.cgs, + thumb/cmp-rd-hs.cgs, thumb/cmp.cgs, + thumb/eor.cgs, thumb/lda-pc.cgs, + thumb/lda-sp.cgs, thumb/ldmia.cgs, + thumb/ldr-imm.cgs, thumb/ldr-pc.cgs, + thumb/ldr-sprel.cgs, thumb/ldr.cgs, + thumb/ldrb-imm.cgs, thumb/ldrb.cgs, + thumb/ldrh-imm.cgs, thumb/ldrh.cgs, + thumb/ldsb.cgs, thumb/ldsh.cgs, + thumb/lsl.cgs, thumb/lsr.cgs, + thumb/mov-hd-hs.cgs, thumb/mov-hd-rs.cgs, + thumb/mov-rd-hs.cgs, thumb/mov.cgs, + thumb/mul.cgs, thumb/mvn.cgs, + thumb/neg.cgs, thumb/orr.cgs, + thumb/pop-pc.cgs, thumb/pop.cgs, + thumb/push-lr.cgs, thumb/push.cgs, + thumb/ror.cgs, thumb/sbc.cgs, + thumb/stmia.cgs, thumb/str-imm.cgs, + thumb/str-sprel.cgs, thumb/str.cgs, + thumb/strb-imm.cgs, thumb/strb.cgs, + thumb/strh-imm.cgs, thumb/strh.cgs, + thumb/sub-sp.cgs, thumb/sub.cgs, + thumb/subi.cgs, thumb/subi8.cgs, + thumb/swi.cgs, thumb/tst.cgs: New files: Thumb + tests. + * xscale: New directory. + * xscale/xscale.exp: New file: Test script. + * xscale/testutils.inc: New file: Test macros. + * xscale/blx.cgs, xscale/mia.cgs, + xscale/miaph.cgs, xscale/miaxy.cgs, + xscale/mra.cgs: New files: XScale tests. diff --git a/sim/testsuite/avr/ChangeLog b/sim/testsuite/avr/ChangeLog deleted file mode 100644 index 5ce686f..0000000 --- a/sim/testsuite/avr/ChangeLog +++ /dev/null @@ -1,15 +0,0 @@ -2021-04-08 Mike Frysinger - - * allinsn.exp (arch): Delete. - -2021-02-13 Mike Frysinger - - * allinsn.exp: Define arch. - -2015-03-29 Mike Frysinger - - * testutils.inc (start): Change to _start and add global markings. - -2015-03-28 Mike Frysinger - - * pass.s, allinsn.exp, testutils.inc: New files. diff --git a/sim/testsuite/avr/ChangeLog-2021 b/sim/testsuite/avr/ChangeLog-2021 new file mode 100644 index 0000000..5ce686f --- /dev/null +++ b/sim/testsuite/avr/ChangeLog-2021 @@ -0,0 +1,15 @@ +2021-04-08 Mike Frysinger + + * allinsn.exp (arch): Delete. + +2021-02-13 Mike Frysinger + + * allinsn.exp: Define arch. + +2015-03-29 Mike Frysinger + + * testutils.inc (start): Change to _start and add global markings. + +2015-03-28 Mike Frysinger + + * pass.s, allinsn.exp, testutils.inc: New files. diff --git a/sim/testsuite/bfin/ChangeLog b/sim/testsuite/bfin/ChangeLog deleted file mode 100644 index ea617e3..0000000 --- a/sim/testsuite/bfin/ChangeLog +++ /dev/null @@ -1,386 +0,0 @@ -2021-04-18 Mike Frysinger - - * getpid.c: New test. - -2021-04-08 Mike Frysinger - - * allinsn.exp (arch): Delete. - -2021-02-13 Mike Frysinger - - * allinsn.exp: Define arch. - -2021-01-18 Mike Frysinger - - * s21.s: Delete accidental copyright line. - -2021-01-04 Mike Frysinger - - * mdma-skel.h: Include stdlib.h. - -2015-10-11 Mike Frysinger - - PR sim/18407 - * ashift_left.s: New test. - -2013-12-07 Mike Frysinger - - * run-tests.sh: Add +x file mode. - -2013-06-23 Mike Frysinger - - * run-tests.sh (usage): Fix typo in exit. - -2013-06-23 Mike Frysinger - - * se_all32bitopcodes.S (se_all_next_insn): Skip debug insn opcodes. - -2013-06-23 Mike Frysinger - - * se_allopcodes.h (_match): Simplify register test to one less insn. - Omit the SSYNC insn when compiling for the sim. - -2013-06-23 Mike Frysinger - - * testutils.inc: Trim trailing whitespace. - -2013-06-17 Mike Frysinger - - * run-tests.sh: Add support for running in parallel. - -2013-06-17 Mike Frysinger - - * se_allopcodes.h: Add debugging related comments. - -2013-06-17 Mike Frysinger - - * se_allopcodes.h: Do not clear RETN/RETE/RETI. - -2012-04-09 Robin Getz - - * random_0017.S, random_0018.S, random_0025.S: New ASTAT shift tests. - -2012-04-09 Robin Getz - - * random_0036.S, random_0037.S: New astat tests. - -2012-04-09 Mike Frysinger - - * se_all64bitg1opcodes.S: Delete xfail line. - * se_all64bitg2opcodes.S: Likewise. - -2012-04-08 Mike Frysinger - - * se_all16bitopcodes.S (SE_ALL_BITS): Define to 16. - (SE_ALL_NEW_INSN_STUB): Define. - (se_all_load_table): Delete. - (se_all_new_insn_log): Likewise. - * se_all32bitopcodes.S: Add more details on slowness. - (SE_ALL_BITS): Define to 13. - (se_all_load_table): Delete. - (se_all_new_insn_stub, se_all_new_insn_log): Likewise. - * se_all64bitg0opcodes.S: Add more details on slowness. - (se_all_new_insn_stub): Delete. - * se_all64bitg1opcodes.S: See mach to bfin. - (se_all_new_insn_stub): Delete. - * se_all64bitg2opcodes.S: See mach to bfin. - (se_all_new_insn_stub): Delete. - * se_allopcodes.h (LOAD_PFX): Define based on SE_ALL_BITS. - (se_all_new_16bit_insn_log, se_all_new_32bit_insn_log): Unify - into new se_all_new_insn_log helper. - (se_all_load_table): New helper. - (se_all_new_insn_stub): Likewise. - -2012-03-25 Mike Frysinger - - * c_dsp32mac_dr_a1a0.s: Change 0x12efbc5569 to 0xefbc5569. - * c_dsp32mac_dr_a1a0_iutsh.s: Change 0x12efbc556 to 0x2efbc556. - * c_dsp32mac_dr_a1a0_m.s: Change 0x12efbc5569 to 0xefbc5569. - * c_dsp32shift_vmaxvmax.s: Change 0xa11002001 to 0x11002001. - * c_dsp32shiftim_af_s.s: Change 0x3a1230001 to 0xa1230001. - - * fact.s: Comment out test with too large a number (6227020800). - - * allinsn.exp: If preprocessing usp.S fails, set has_cpp to 0, - else set it to 1. If compiling argc.c fails, set has_cc to 0, - else set it to 1. When processing each src file, if has_ccp is - 0 and the file ends in .S, skip it; if it has_cc is 0 and the - file ends in .c, skip it. - -2012-03-19 Mike Frysinger - - * se_all64bitg0opcodes.S, se_all64bitg1opcodes.S, - se_all64bitg2opcodes.S: New exhaustive parallel insn tests. - -2012-03-19 Mike Frysinger - - * se_allopcodes.h: New framework for testing opcode regions. - * se_all16bitopcodes.S: Convert over to se_allopcodes.h. - * se_all32bitopcodes.S: Likewise. - -2012-03-19 Stuart Henderson - - * c_dsp32shiftim_amix.s: Check edge cases in shift behavior. - -2012-03-19 Robin Getz - - * random_0014.S, random_0015.S, random_0016.S: New tests for shifts. - -2012-03-18 Mike Frysinger - - * se_all16bitopcodes.S: Merge code from se_all32bitopcodes.S. - -2011-09-28 Mike Frysinger - - * vit_max2.s: New tests for parallel VIT_MAX insns. - -2011-06-18 Robin Getz - - * random_0019.S, random_0020.S, random_0021.S, random_0022.S, - random_0023.S, random_0024.S, random_0026.S, random_0027.S, - random_0028.S, random_0029.S, random_0030.S, random_0032.S, - random_0035.S: New tests for dsp insns. - -2011-06-04 Mike Frysinger - - * .gitignore, 10272_small.s, 10436.s, 10622.s, 10742.s, 10799.s, - 11080.s, 7641.s, a0.s, a0shift.S, a10.s, a11.S, a12.s, a1.s, a20.S, - a21.s, a22.s, a23.s, a24.s, a25.s, a26.s, a2.s, a30.s, a3.s, a4.s, - a5.s, a6.s, a7.s, a8.s, a9.s, abs-2.S, abs-3.S, abs-4.S, abs_acc.s, - abs.S, acc-rot.s, acp5_19.s, acp5_4.s, add_imm7.s, add_shift.S, - add_sub_acc.s, addsub_flags.S, algnbug1.s, algnbug2.s, allinsn.exp, - argc.c, ashift_flags.s, ashift.s, b0.S, b1.s, b2.S, brcc.s, brevadd.s, - byteop16m.s, byteop16p.s, byteop1p.s, byteop2p.s, byteop3p.s, - byteunpack.s, c_alu2op_arith_r_sft.s, c_alu2op_conv_b.s, - c_alu2op_conv_h.s, c_alu2op_conv_mix.s, c_alu2op_conv_neg.s, - c_alu2op_conv_toggle.s, c_alu2op_conv_xb.s, c_alu2op_conv_xh.s, - c_alu2op_divq.s, c_alu2op_divs.s, c_alu2op_log_l_sft.s, - c_alu2op_log_r_sft.s, c_alu2op_shadd_1.s, c_alu2op_shadd_2.s, - c_brcc_bp1.s, c_brcc_bp2.s, c_brcc_bp3.s, c_brcc_bp4.s, - c_brcc_brf_bp.s, c_brcc_brf_brt_bp.s, c_brcc_brf_brt_nbp.s, - c_brcc_brf_fbkwd.s, c_brcc_brf_nbp.s, c_brcc_brt_bp.s, - c_brcc_brt_nbp.s, c_brcc_kills_dhits.s, c_brcc_kills_dmiss.s, - c_br_preg_killed_ac.s, c_br_preg_killed_ex1.s, c_br_preg_stall_ac.s, - c_br_preg_stall_ex1.s, cc0.s, cc1.s, cc5.S, c_cactrl_iflush_pr_pp.s, - c_cactrl_iflush_pr.s, c_calla_ljump.s, c_calla_subr.s, cc-alu.S, - cc-astat-bits.s, c_cc2dreg.s, c_cc2stat_cc_ac.S, c_cc2stat_cc_an.s, - c_cc2stat_cc_aq.s, c_cc2stat_cc_av0.S, c_cc2stat_cc_av1.S, - c_cc2stat_cc_az.s, c_ccflag_a0a1.S, c_cc_flag_ccmv_depend.S, - c_ccflag_dr_dr.s, c_ccflag_dr_dr_uu.s, c_cc_flagdreg_mvbrsft.s, - c_cc_flagdreg_mvbrsft_s1.s, c_cc_flagdreg_mvbrsft_sn.s, - c_ccflag_dr_imm3.s, c_ccflag_dr_imm3_uu.s, c_ccflag_pr_imm3.s, - c_ccflag_pr_imm3_uu.s, c_ccflag_pr_pr.s, c_ccflag_pr_pr_uu.s, - c_ccmv_cc_dr_dr.s, c_ccmv_cc_dr_pr.s, c_ccmv_cc_pr_pr.s, - c_ccmv_ncc_dr_dr.s, c_ccmv_ncc_dr_pr.s, c_ccmv_ncc_pr_pr.s, - c_cc_regmvlogi_mvbrsft.s, c_cc_regmvlogi_mvbrsft_s1.s, - c_cc_regmvlogi_mvbrsft_sn.S, c_comp3op_dr_and_dr.s, - c_comp3op_dr_minus_dr.s, c_comp3op_dr_mix.s, c_comp3op_dr_or_dr.s, - c_comp3op_dr_plus_dr.s, c_comp3op_dr_xor_dr.s, - c_comp3op_pr_plus_pr_sh1.s, c_comp3op_pr_plus_pr_sh2.s, - c_compi2opd_dr_add_i7_n.s, c_compi2opd_dr_add_i7_p.s, - c_compi2opd_dr_eq_i7_n.s, c_compi2opd_dr_eq_i7_p.s, - c_compi2opd_flags_2.S, c_compi2opd_flags.S, c_compi2opp_pr_add_i7_n.s, - c_compi2opp_pr_add_i7_p.s, c_compi2opp_pr_eq_i7_n.s, - c_compi2opp_pr_eq_i7_p.s, c_dagmodik_lnz_imgebl.s, - c_dagmodik_lnz_imltbl.s, c_dagmodik_lz_inc_dec.s, - c_dagmodim_lnz_imgebl.s, c_dagmodim_lnz_imltbl.s, - c_dagmodim_lz_inc_dec.s, c_dsp32alu_a0a1s.s, c_dsp32alu_a0_pm_a1.s, - c_dsp32alu_aa_absabs.s, c_dsp32alu_a_abs_a.s, c_dsp32alu_aa_negneg.s, - c_dsp32alu_absabs.s, c_dsp32alu_abs.s, c_dsp32alu_alhwx.s, - c_dsp32alu_a_neg_a.s, c_dsp32alu_awx.s, c_dsp32alu_byteop1ew.s, - c_dsp32alu_byteop2.s, c_dsp32alu_byteop3.s, c_dsp32alu_bytepack.s, - c_dsp32alu_byteunpack.s, c_dsp32alu_disalnexcpt.s, c_dsp32alu_maxmax.s, - c_dsp32alu_max.s, c_dsp32alu_minmin.s, c_dsp32alu_min.s, - c_dsp32alu_mix.s, c_dsp32alu_rh_m.s, c_dsp32alu_rh_p.s, - c_dsp32alu_rh_rnd12_m.s, c_dsp32alu_rh_rnd12_p.s, - c_dsp32alu_rh_rnd20_m.s, c_dsp32alu_rh_rnd20_p.s, - c_dsp32alu_r_lh_a0pa1.s, c_dsp32alu_rlh_rnd.s, c_dsp32alu_rl_m.s, - c_dsp32alu_rl_p.s, c_dsp32alu_rl_rnd12_m.s, c_dsp32alu_rl_rnd12_p.s, - c_dsp32alu_rl_rnd20_m.s, c_dsp32alu_rl_rnd20_p.s, c_dsp32alu_rmm.s, - c_dsp32alu_rmp.s, c_dsp32alu_rm.s, c_dsp32alu_r_negneg.s, - c_dsp32alu_rpm.s, c_dsp32alu_rpp.s, c_dsp32alu_rp.s, - c_dsp32alu_rr_lph_a1a0.s, c_dsp32alu_rrpm_aa.s, c_dsp32alu_rrpmmp.s, - c_dsp32alu_rrpmmp_sft.s, c_dsp32alu_rrpmmp_sft_x.s, c_dsp32alu_rrpm.s, - c_dsp32alu_rrppmm.s, c_dsp32alu_rrppmm_sft.s, - c_dsp32alu_rrppmm_sft_x.s, c_dsp32alu_saa.s, c_dsp32alu_sat_aa.S, - c_dsp32alu_search.s, c_dsp32alu_sgn.s, c_dsp32mac_a1a0_iuw32.s, - c_dsp32mac_a1a0_m.s, c_dsp32mac_a1a0.s, c_dsp32mac_dr_a0_ih.s, - c_dsp32mac_dr_a0_i.s, c_dsp32mac_dr_a0_is.s, c_dsp32mac_dr_a0_iu.s, - c_dsp32mac_dr_a0_m.s, c_dsp32mac_dr_a0.s, c_dsp32mac_dr_a0_s.s, - c_dsp32mac_dr_a0_t.s, c_dsp32mac_dr_a0_tu.s, c_dsp32mac_dr_a0_u.s, - c_dsp32mac_dr_a1a0_iutsh.s, c_dsp32mac_dr_a1a0_m.s, - c_dsp32mac_dr_a1a0.s, c_dsp32mac_dr_a1_ih.s, c_dsp32mac_dr_a1_i.s, - c_dsp32mac_dr_a1_is.s, c_dsp32mac_dr_a1_iu.s, c_dsp32mac_dr_a1_m.s, - c_dsp32mac_dr_a1.s, c_dsp32mac_dr_a1_s.s, c_dsp32mac_dr_a1_t.s, - c_dsp32mac_dr_a1_tu.s, c_dsp32mac_dr_a1_u.s, c_dsp32mac_mix.s, - c_dsp32mac_pair_a0_i.s, c_dsp32mac_pair_a0_is.s, - c_dsp32mac_pair_a0_m.s, c_dsp32mac_pair_a0.s, c_dsp32mac_pair_a0_s.s, - c_dsp32mac_pair_a0_u.s, c_dsp32mac_pair_a1a0_i.s, - c_dsp32mac_pair_a1a0_is.s, c_dsp32mac_pair_a1a0_m.s, - c_dsp32mac_pair_a1a0.s, c_dsp32mac_pair_a1a0_s.s, - c_dsp32mac_pair_a1a0_u.s, c_dsp32mac_pair_a1_i.s, - c_dsp32mac_pair_a1_is.s, c_dsp32mac_pair_a1_m.s, c_dsp32mac_pair_a1.s, - c_dsp32mac_pair_a1_s.s, c_dsp32mac_pair_a1_u.s, c_dsp32mac_pair_mix.s, - c_dsp32mult_dr_ih.s, c_dsp32mult_dr_i.s, c_dsp32mult_dr_is.s, - c_dsp32mult_dr_iu.s, c_dsp32mult_dr_m_i.s, c_dsp32mult_dr_m_iutsh.s, - c_dsp32mult_dr_mix.s, c_dsp32mult_dr_m.s, c_dsp32mult_dr_m_s.s, - c_dsp32mult_dr_m_t.s, c_dsp32mult_dr_m_u.s, c_dsp32mult_dr.s, - c_dsp32mult_dr_s.s, c_dsp32mult_dr_t.s, c_dsp32mult_dr_tu.s, - c_dsp32mult_dr_u.s, c_dsp32mult_pair_i.s, c_dsp32mult_pair_is.s, - c_dsp32mult_pair_m_i.s, c_dsp32mult_pair_m_is.s, c_dsp32mult_pair_m.s, - c_dsp32mult_pair_m_s.s, c_dsp32mult_pair_m_u.s, c_dsp32mult_pair.s, - c_dsp32mult_pair_s.s, c_dsp32mult_pair_u.s, c_dsp32shift_a0alr.s, - c_dsp32shift_af.s, c_dsp32shift_af_s.s, c_dsp32shift_ahalf_ln.s, - c_dsp32shift_ahalf_ln_s.s, c_dsp32shift_ahalf_lp.s, - c_dsp32shift_ahalf_lp_s.s, c_dsp32shift_ahalf_rn.s, - c_dsp32shift_ahalf_rn_s.s, c_dsp32shift_ahalf_rp.s, - c_dsp32shift_ahalf_rp_s.s, c_dsp32shift_ahh.s, c_dsp32shift_ahh_s.s, - c_dsp32shift_align16.s, c_dsp32shift_align24.s, c_dsp32shift_align8.s, - c_dsp32shift_amix.s, c_dsp32shift_bitmux.s, c_dsp32shift_bxor.s, - c_dsp32shift_expadj_h.s, c_dsp32shift_expadj_l.s, - c_dsp32shift_expadj_r.s, c_dsp32shift_expexp_r.s, c_dsp32shift_fdepx.s, - c_dsp32shift_fextx.s, c_dsp32shiftim_a0alr.s, c_dsp32shiftim_af.s, - c_dsp32shiftim_af_s.s, c_dsp32shiftim_ahalf_ln.s, - c_dsp32shiftim_ahalf_ln_s.s, c_dsp32shiftim_ahalf_lp.s, - c_dsp32shiftim_ahalf_lp_s.s, c_dsp32shiftim_ahalf_rn.s, - c_dsp32shiftim_ahalf_rn_s.s, c_dsp32shiftim_ahalf_rp.s, - c_dsp32shiftim_ahalf_rp_s.s, c_dsp32shiftim_ahh.s, - c_dsp32shiftim_ahh_s.s, c_dsp32shiftim_amix.s, c_dsp32shiftim_lf.s, - c_dsp32shiftim_lhalf_ln.s, c_dsp32shiftim_lhalf_lp.s, - c_dsp32shiftim_lhalf_rn.s, c_dsp32shiftim_lhalf_rp.s, - c_dsp32shiftim_lhh.s, c_dsp32shiftim_lmix.s, c_dsp32shiftim_rot.s, - c_dsp32shift_lf.s, c_dsp32shift_lhalf_ln.s, c_dsp32shift_lhalf_lp.s, - c_dsp32shift_lhalf_rn.s, c_dsp32shift_lhalf_rp.s, c_dsp32shift_lhh.s, - c_dsp32shift_lmix.s, c_dsp32shift_ones.s, c_dsp32shift_pack.s, - c_dsp32shift_rot_mix.s, c_dsp32shift_rot.s, c_dsp32shift_signbits_rh.s, - c_dsp32shift_signbits_rl.s, c_dsp32shift_signbits_r.s, - c_dsp32shift_vmax.s, c_dsp32shift_vmaxvmax.s, c_dspldst_ld_drhi_ipp.s, - c_dspldst_ld_drhi_i.s, c_dspldst_ld_dr_ippm.s, c_dspldst_ld_dr_ipp.s, - c_dspldst_ld_dr_i.s, c_dspldst_ld_drlo_ipp.s, c_dspldst_ld_drlo_i.s, - c_dspldst_st_drhi_ipp.s, c_dspldst_st_drhi_i.s, c_dspldst_st_dr_ippm.s, - c_dspldst_st_dr_ipp.s, c_dspldst_st_dr_i.s, c_dspldst_st_drlo_ipp.s, - c_dspldst_st_drlo_i.s, cec-exact-exception.S, cec-ifetch.S, - cec-multi-pending.S, cec-non-operating-env.s, cec-no-snen-reti.S, - cec-raise-reti.S, cec-snen-reti.S, cec-syscfg-ssstep.S, - cec-system-call.S, c_except_illopcode.S, c_except_sys_sstep.S, - c_except_user_mode.S, c_interr_disable_enable.S, c_interr_disable.S, - c_interr_excpt.S, c_interr_loopsetup_stld.S, c_interr_nested.S, - c_interr_nmi.S, c_interr_pending_2.S, c_interr_pending.S, - c_interr_timer_reload.S, c_interr_timer.S, c_interr_timer_tcount.S, - c_interr_timer_tscale.S, cir1.s, cir.s, c_ldimmhalf_dreg.s, - c_ldimmhalf_drhi.s, c_ldimmhalf_drlo.s, c_ldimmhalf_h_dr.s, - c_ldimmhalf_h_ibml.s, c_ldimmhalf_h_pr.s, c_ldimmhalf_l_dr.s, - c_ldimmhalf_l_ibml.s, c_ldimmhalf_l_pr.s, c_ldimmhalf_lz_dr.s, - c_ldimmhalf_lzhi_dr.s, c_ldimmhalf_lzhi_ibml.s, c_ldimmhalf_lzhi_pr.s, - c_ldimmhalf_lz_ibml.s, c_ldimmhalf_lz_pr.s, c_ldimmhalf_pibml.s, - c_ldstidxl_ld_dr_b.s, c_ldstidxl_ld_dreg.s, c_ldstidxl_ld_dr_h.s, - c_ldstidxl_ld_dr_xb.s, c_ldstidxl_ld_dr_xh.s, c_ldstidxl_ld_preg.s, - c_ldstidxl_st_dr_b.s, c_ldstidxl_st_dreg.s, c_ldstidxl_st_dr_h.s, - c_ldstidxl_st_preg.s, c_ldstiifp_ld_dreg.s, c_ldstiifp_ld_preg.s, - c_ldstiifp_st_dreg.s, c_ldstiifp_st_preg.s, c_ldstii_ld_dreg.s, - c_ldstii_ld_dr_h.s, c_ldstii_ld_dr_xh.s, c_ldstii_ld_preg.s, - c_ldstii_st_dreg.s, c_ldstii_st_dr_h.s, c_ldstii_st_preg.s, - c_ldst_ld_d_p_b.s, c_ldst_ld_d_p_h.s, c_ldst_ld_d_p_mm_b.s, - c_ldst_ld_d_p_mm_h.s, c_ldst_ld_d_p_mm.s, c_ldst_ld_d_p_mm_xb.s, - c_ldst_ld_d_p_mm_xh.s, c_ldst_ld_d_p_pp_b.s, c_ldst_ld_d_p_pp_h.s, - c_ldst_ld_d_p_ppmm_hbx.s, c_ldst_ld_d_p_pp.s, c_ldst_ld_d_p_pp_xb.s, - c_ldst_ld_d_p_pp_xh.s, c_ldst_ld_d_p.s, c_ldst_ld_d_p_xb.s, - c_ldst_ld_d_p_xh.s, c_ldst_ld_p_p_mm.s, c_ldst_ld_p_p_pp.s, - c_ldst_ld_p_p.s, c_ldstpmod_ld_dreg.s, c_ldstpmod_ld_dr_hi.s, - c_ldstpmod_ld_dr_lo.s, c_ldstpmod_ld_h_xh.s, c_ldstpmod_ld_lohi.s, - c_ldstpmod_st_dreg.s, c_ldstpmod_st_dr_hi.s, c_ldstpmod_st_dr_lo.s, - c_ldstpmod_st_lohi.s, c_ldst_st_p_d_b.s, c_ldst_st_p_d_h.s, - c_ldst_st_p_d_mm_b.s, c_ldst_st_p_d_mm_h.s, c_ldst_st_p_d_mm.s, - c_ldst_st_p_d_pp_b.s, c_ldst_st_p_d_pp_h.s, c_ldst_st_p_d_pp.s, - c_ldst_st_p_d.s, c_ldst_st_p_p_mm.s, c_ldst_st_p_p_pp.s, - c_ldst_st_p_p.s, c_linkage.s, cli-sti.s, c_logi2op_alshft_mix.s, - c_logi2op_arith_shft.s, c_logi2op_bitclr.s, c_logi2op_bitset.s, - c_logi2op_bittgl.s, c_logi2op_bittst.s, c_logi2op_log_l_shft_astat.S, - c_logi2op_log_l_shft.s, c_logi2op_log_r_shft_astat.S, - c_logi2op_log_r_shft.s, c_logi2op_nbittst.s, c_loopsetup_nested_bot.s, - c_loopsetup_nested_prelc.s, c_loopsetup_nested.s, - c_loopsetup_nested_top.s, c_loopsetup_overlap.s, - c_loopsetup_preg_div2_lc0.s, c_loopsetup_preg_div2_lc1.s, - c_loopsetup_preg_lc0.s, c_loopsetup_preg_lc1.s, - c_loopsetup_preg_stld.s, c_loopsetup_prelc.s, c_loopsetup_topbotcntr.s, - c_mmr_interr_ctl.s, c_mmr_loop.S, c_mmr_loop_user_except.S, - c_mmr_ppop_illegal_adr.S, c_mmr_ppopm_illegal_adr.S, c_mmr_timer.S, - c_mode_supervisor.S, c_mode_user.S, c_mode_user_superivsor.S, cmpacc.s, - cmpdreg.S, c_multi_issue_dsp_ld_ld.s, c_multi_issue_dsp_ldst_1.s, - c_multi_issue_dsp_ldst_2.s, compare.s, conv_enc_gen.s, - c_progctrl_call_pcpr.s, c_progctrl_call_pr.s, - c_progctrl_clisti_interr.S, c_progctrl_csync_mmr.S, - c_progctrl_except_rtx.S, c_progctrl_excpt.S, c_progctrl_jump_pcpr.s, - c_progctrl_jump_pr.s, c_progctrl_nop.s, c_progctrl_raise_rt_i_n.S, - c_progctrl_rts.s, c_ptr2op_pr_neg_pr.s, c_ptr2op_pr_sft_2_1.s, - c_ptr2op_pr_shadd_1_2.s, c_pushpopmultiple_dp_pair.s, - c_pushpopmultiple_dp.s, c_pushpopmultiple_dreg.s, - c_pushpopmultiple_preg.s, c_regmv_acc_acc.s, c_regmv_dag_lz_dep.s, - c_regmv_dr_acc_acc.s, c_regmv_dr_dep_nostall.s, c_regmv_dr_dr.s, - c_regmv_dr_imlb.s, c_regmv_dr_pr.s, c_regmv_imlb_dep_nostall.s, - c_regmv_imlb_dep_stall.s, c_regmv_imlb_dr.s, c_regmv_imlb_imlb.s, - c_regmv_imlb_pr.s, c_regmv_pr_dep_nostall.s, c_regmv_pr_dep_stall.s, - c_regmv_pr_dr.s, c_regmv_pr_imlb.s, c_regmv_pr_pr.s, - c_seq_ac_raise_mv_ppop.S, c_seq_ac_raise_mv.S, - c_seq_ac_regmv_pushpop.S, c_seq_dec_raise_pushpop.S, - c_seq_ex1_brcc_mv_pop.S, c_seq_ex1_call_mv_pop.S, c_seq_ex1_j_mv_pop.S, - c_seq_ex1_raise_brcc_mv_pop.S, c_seq_ex1_raise_call_mv_pop.S, - c_seq_ex1_raise_j_mv_pop.S, c_seq_ex2_brcc_mp_mv_pop.S, - c_seq_ex2_mmrj_mvpop.S, c_seq_ex2_mmr_mvpop.S, - c_seq_ex2_raise_mmrj_mvpop.S, c_seq_ex2_raise_mmr_mvpop.S, - c_seq_ex3_ls_brcc_mvp.S, c_seq_ex3_ls_mmrj_mvp.S, - c_seq_ex3_ls_mmr_mvp.S, c_seq_ex3_raise_ls_mmrj_mvp.S, - c_seq_wb_cs_lsmmrj_mvp.S, c_seq_wb_raisecs_lsmmrj_mvp.S, - c_seq_wb_rti_lsmmrj_mvp.S, c_seq_wb_rtn_lsmmrj_mvp.S, - c_seq_wb_rtx_lsmmrj_mvp.S, c_ujump.s, cycles.s, d0.s, d1.s, d2.s, - dbg_brprd_ntkn_src_kill.S, dbg_brtkn_nprd_src_kill.S, - dbg_jmp_src_kill.S, dbg_tr_basic.S, dbg_tr_simplejp.S, dbg_tr_tbuf0.S, - dbg_tr_umode.S, disalnexcpt_implicit.S, div0.s, divq.s, dotproduct2.s, - dotproduct.s, double_prec_mult.s, dsp_a4.s, dsp_a7.s, dsp_a8.s, - dsp_d0.s, dsp_d1.s, dsp_neg.S, dsp_s1.s, e0.s, edn_snafu.s, - eu_dsp32mac_s.s, events.s, f221.s, fact.s, fir.s, fsm.s, greg2.s, - hwloop-bits.S, hwloop-branch-in.s, hwloop-branch-out.s, - hwloop-lt-bits.s, hwloop-nested.s, i0.s, iir.s, issue103.s, issue109.s, - issue112.s, issue113.s, issue117.s, issue118.s, issue119.s, issue121.s, - issue123.s, issue124.s, issue125.s, issue126.s, issue127.s, issue129.s, - issue139.S, issue140.S, issue142.s, issue144.s, issue146.S, issue175.s, - issue205.s, issue257.s, issue272.S, issue83.s, issue89.s, l0.s, - l0shift.s, l2_loop.s, link-2.s, link.s, lmu_cplb_multiple0.S, - lmu_cplb_multiple1.S, lmu_excpt_align.S, lmu_excpt_default.S, - lmu_excpt_illaddr.S, lmu_excpt_prot0.S, lmu_excpt_prot1.S, load.s, - logic.s, loop_snafu.s, loop_strncpy.s, lp0.s, lp1.s, lsetup.s, - m0boundary.s, m10.s, m11.s, m12.s, m13.s, m14.s, m15.s, m16.s, m17.s, - m1.S, m2.s, m3.s, m4.s, m5.s, m6.s, m7.s, m8.s, m9.s, mac2halfreg.S, - Makefile, math.s, max_min_flags.s, mc_s2.s, mdma-32bit-1d.c, - mdma-32bit-1d-neg-count.c, mdma-8bit-1d.c, mdma-8bit-1d-neg-count.c, - mdma-skel.h, mem3.s, mmr-exception.s, move.s, msa_acp_5_10.s, - msa_acp_5.10.S, msa_acp_5.12_1.S, msa_acp_5.12_2.S, mult.s, neg-2.S, - neg-3.S, neg.S, nshift.s, PN_generator.s, pr.s, push-pop-multiple.s, - pushpopreg_1.s, push-pop.s, quadaddsub.s, random_0001.s, random_0002.S, - random_0003.S, random_0004.S, random_0005.S, random_0006.S, - random_0007.S, random_0008.S, random_0009.S, random_0010.S, - random_0011.S, random_0012.S, random_0013.S, random_0031.S, - random_0033.S, random_0034.S, run-tests.sh, s0.s, s10.s, s11.s, s12.s, - s13.s, s14.s, s15.s, s16.s, s17.s, s18.s, s19.s, s1.s, s20.s, s21.s, - s2.s, s30.s, s3.s, s4.s, s5.s, s6.s, s7.s, s8.s, s9.s, saatest.s, - se_all16bitopcodes.S, se_all32bitopcodes.lds, se_all32bitopcodes.S, - se_brtarget_stall.S, se_bug_ui2.S, se_bug_ui3.S, se_bug_ui.S, - se_cc2stat_haz.S, se_cc_kill.S, se_cof.S, se_event_quad.S, - se_excpt_dagprotviol.S, se_excpt_ifprotviol.S, se_excpt_ssstep.S, - se_illegalcombination.S, se_kills2.S, se_kill_wbbr.S, - se_loop_disable.S, se_loop_kill_01.S, se_loop_kill_dcr_01.S, - se_loop_kill_dcr.S, se_loop_kill.S, se_loop_lr.S, - se_loop_mv2lb_stall.S, se_loop_mv2lc.S, se_loop_mv2lc_stall.S, - se_loop_mv2lt_stall.S, se_loop_nest_ppm_1.S, se_loop_nest_ppm_2.S, - se_loop_nest_ppm.S, se_loop_ppm_1.S, se_loop_ppm_int.S, se_loop_ppm.S, - se_lsetup_kill.S, se_misaligned_fetch.S, se_more_ret_haz.S, se_mv2lp.S, - se_oneins_zoff.S, se_popkill.S, seqstat.s, se_regmv_usp_sysreg.S, - se_rets_hazard.s, se_rts_rti.S, se_ssstep_dagprotviol.S, se_ssync.S, - se_stall_if2.S, se_undefinedinstruction1.S, se_undefinedinstruction2.S, - se_undefinedinstruction3.S, se_undefinedinstruction4.S, - se_usermode_protviol.S, sign.s, simple0.s, sri.s, stk2.s, stk3.s, - stk4.s, stk5.s, stk6.s, stk.s, syscfg.s, tar10622.s, test-dma.h, - test.h, testset2.s, testset.s, testutils.inc, unlink.S, up0.s, usp.S, - vec-abs-2.S, vec-abs-3.S, vec-abs.S, vecadd.s, vec-neg-2.S, - vec-neg-3.S, vec-neg.S, viterbi2.s, vit_max.s, wtf.s, x1.s, zcall.s, - zeroflagrnd.s: New files. diff --git a/sim/testsuite/bfin/ChangeLog-2021 b/sim/testsuite/bfin/ChangeLog-2021 new file mode 100644 index 0000000..ea617e3 --- /dev/null +++ b/sim/testsuite/bfin/ChangeLog-2021 @@ -0,0 +1,386 @@ +2021-04-18 Mike Frysinger + + * getpid.c: New test. + +2021-04-08 Mike Frysinger + + * allinsn.exp (arch): Delete. + +2021-02-13 Mike Frysinger + + * allinsn.exp: Define arch. + +2021-01-18 Mike Frysinger + + * s21.s: Delete accidental copyright line. + +2021-01-04 Mike Frysinger + + * mdma-skel.h: Include stdlib.h. + +2015-10-11 Mike Frysinger + + PR sim/18407 + * ashift_left.s: New test. + +2013-12-07 Mike Frysinger + + * run-tests.sh: Add +x file mode. + +2013-06-23 Mike Frysinger + + * run-tests.sh (usage): Fix typo in exit. + +2013-06-23 Mike Frysinger + + * se_all32bitopcodes.S (se_all_next_insn): Skip debug insn opcodes. + +2013-06-23 Mike Frysinger + + * se_allopcodes.h (_match): Simplify register test to one less insn. + Omit the SSYNC insn when compiling for the sim. + +2013-06-23 Mike Frysinger + + * testutils.inc: Trim trailing whitespace. + +2013-06-17 Mike Frysinger + + * run-tests.sh: Add support for running in parallel. + +2013-06-17 Mike Frysinger + + * se_allopcodes.h: Add debugging related comments. + +2013-06-17 Mike Frysinger + + * se_allopcodes.h: Do not clear RETN/RETE/RETI. + +2012-04-09 Robin Getz + + * random_0017.S, random_0018.S, random_0025.S: New ASTAT shift tests. + +2012-04-09 Robin Getz + + * random_0036.S, random_0037.S: New astat tests. + +2012-04-09 Mike Frysinger + + * se_all64bitg1opcodes.S: Delete xfail line. + * se_all64bitg2opcodes.S: Likewise. + +2012-04-08 Mike Frysinger + + * se_all16bitopcodes.S (SE_ALL_BITS): Define to 16. + (SE_ALL_NEW_INSN_STUB): Define. + (se_all_load_table): Delete. + (se_all_new_insn_log): Likewise. + * se_all32bitopcodes.S: Add more details on slowness. + (SE_ALL_BITS): Define to 13. + (se_all_load_table): Delete. + (se_all_new_insn_stub, se_all_new_insn_log): Likewise. + * se_all64bitg0opcodes.S: Add more details on slowness. + (se_all_new_insn_stub): Delete. + * se_all64bitg1opcodes.S: See mach to bfin. + (se_all_new_insn_stub): Delete. + * se_all64bitg2opcodes.S: See mach to bfin. + (se_all_new_insn_stub): Delete. + * se_allopcodes.h (LOAD_PFX): Define based on SE_ALL_BITS. + (se_all_new_16bit_insn_log, se_all_new_32bit_insn_log): Unify + into new se_all_new_insn_log helper. + (se_all_load_table): New helper. + (se_all_new_insn_stub): Likewise. + +2012-03-25 Mike Frysinger + + * c_dsp32mac_dr_a1a0.s: Change 0x12efbc5569 to 0xefbc5569. + * c_dsp32mac_dr_a1a0_iutsh.s: Change 0x12efbc556 to 0x2efbc556. + * c_dsp32mac_dr_a1a0_m.s: Change 0x12efbc5569 to 0xefbc5569. + * c_dsp32shift_vmaxvmax.s: Change 0xa11002001 to 0x11002001. + * c_dsp32shiftim_af_s.s: Change 0x3a1230001 to 0xa1230001. + + * fact.s: Comment out test with too large a number (6227020800). + + * allinsn.exp: If preprocessing usp.S fails, set has_cpp to 0, + else set it to 1. If compiling argc.c fails, set has_cc to 0, + else set it to 1. When processing each src file, if has_ccp is + 0 and the file ends in .S, skip it; if it has_cc is 0 and the + file ends in .c, skip it. + +2012-03-19 Mike Frysinger + + * se_all64bitg0opcodes.S, se_all64bitg1opcodes.S, + se_all64bitg2opcodes.S: New exhaustive parallel insn tests. + +2012-03-19 Mike Frysinger + + * se_allopcodes.h: New framework for testing opcode regions. + * se_all16bitopcodes.S: Convert over to se_allopcodes.h. + * se_all32bitopcodes.S: Likewise. + +2012-03-19 Stuart Henderson + + * c_dsp32shiftim_amix.s: Check edge cases in shift behavior. + +2012-03-19 Robin Getz + + * random_0014.S, random_0015.S, random_0016.S: New tests for shifts. + +2012-03-18 Mike Frysinger + + * se_all16bitopcodes.S: Merge code from se_all32bitopcodes.S. + +2011-09-28 Mike Frysinger + + * vit_max2.s: New tests for parallel VIT_MAX insns. + +2011-06-18 Robin Getz + + * random_0019.S, random_0020.S, random_0021.S, random_0022.S, + random_0023.S, random_0024.S, random_0026.S, random_0027.S, + random_0028.S, random_0029.S, random_0030.S, random_0032.S, + random_0035.S: New tests for dsp insns. + +2011-06-04 Mike Frysinger + + * .gitignore, 10272_small.s, 10436.s, 10622.s, 10742.s, 10799.s, + 11080.s, 7641.s, a0.s, a0shift.S, a10.s, a11.S, a12.s, a1.s, a20.S, + a21.s, a22.s, a23.s, a24.s, a25.s, a26.s, a2.s, a30.s, a3.s, a4.s, + a5.s, a6.s, a7.s, a8.s, a9.s, abs-2.S, abs-3.S, abs-4.S, abs_acc.s, + abs.S, acc-rot.s, acp5_19.s, acp5_4.s, add_imm7.s, add_shift.S, + add_sub_acc.s, addsub_flags.S, algnbug1.s, algnbug2.s, allinsn.exp, + argc.c, ashift_flags.s, ashift.s, b0.S, b1.s, b2.S, brcc.s, brevadd.s, + byteop16m.s, byteop16p.s, byteop1p.s, byteop2p.s, byteop3p.s, + byteunpack.s, c_alu2op_arith_r_sft.s, c_alu2op_conv_b.s, + c_alu2op_conv_h.s, c_alu2op_conv_mix.s, c_alu2op_conv_neg.s, + c_alu2op_conv_toggle.s, c_alu2op_conv_xb.s, c_alu2op_conv_xh.s, + c_alu2op_divq.s, c_alu2op_divs.s, c_alu2op_log_l_sft.s, + c_alu2op_log_r_sft.s, c_alu2op_shadd_1.s, c_alu2op_shadd_2.s, + c_brcc_bp1.s, c_brcc_bp2.s, c_brcc_bp3.s, c_brcc_bp4.s, + c_brcc_brf_bp.s, c_brcc_brf_brt_bp.s, c_brcc_brf_brt_nbp.s, + c_brcc_brf_fbkwd.s, c_brcc_brf_nbp.s, c_brcc_brt_bp.s, + c_brcc_brt_nbp.s, c_brcc_kills_dhits.s, c_brcc_kills_dmiss.s, + c_br_preg_killed_ac.s, c_br_preg_killed_ex1.s, c_br_preg_stall_ac.s, + c_br_preg_stall_ex1.s, cc0.s, cc1.s, cc5.S, c_cactrl_iflush_pr_pp.s, + c_cactrl_iflush_pr.s, c_calla_ljump.s, c_calla_subr.s, cc-alu.S, + cc-astat-bits.s, c_cc2dreg.s, c_cc2stat_cc_ac.S, c_cc2stat_cc_an.s, + c_cc2stat_cc_aq.s, c_cc2stat_cc_av0.S, c_cc2stat_cc_av1.S, + c_cc2stat_cc_az.s, c_ccflag_a0a1.S, c_cc_flag_ccmv_depend.S, + c_ccflag_dr_dr.s, c_ccflag_dr_dr_uu.s, c_cc_flagdreg_mvbrsft.s, + c_cc_flagdreg_mvbrsft_s1.s, c_cc_flagdreg_mvbrsft_sn.s, + c_ccflag_dr_imm3.s, c_ccflag_dr_imm3_uu.s, c_ccflag_pr_imm3.s, + c_ccflag_pr_imm3_uu.s, c_ccflag_pr_pr.s, c_ccflag_pr_pr_uu.s, + c_ccmv_cc_dr_dr.s, c_ccmv_cc_dr_pr.s, c_ccmv_cc_pr_pr.s, + c_ccmv_ncc_dr_dr.s, c_ccmv_ncc_dr_pr.s, c_ccmv_ncc_pr_pr.s, + c_cc_regmvlogi_mvbrsft.s, c_cc_regmvlogi_mvbrsft_s1.s, + c_cc_regmvlogi_mvbrsft_sn.S, c_comp3op_dr_and_dr.s, + c_comp3op_dr_minus_dr.s, c_comp3op_dr_mix.s, c_comp3op_dr_or_dr.s, + c_comp3op_dr_plus_dr.s, c_comp3op_dr_xor_dr.s, + c_comp3op_pr_plus_pr_sh1.s, c_comp3op_pr_plus_pr_sh2.s, + c_compi2opd_dr_add_i7_n.s, c_compi2opd_dr_add_i7_p.s, + c_compi2opd_dr_eq_i7_n.s, c_compi2opd_dr_eq_i7_p.s, + c_compi2opd_flags_2.S, c_compi2opd_flags.S, c_compi2opp_pr_add_i7_n.s, + c_compi2opp_pr_add_i7_p.s, c_compi2opp_pr_eq_i7_n.s, + c_compi2opp_pr_eq_i7_p.s, c_dagmodik_lnz_imgebl.s, + c_dagmodik_lnz_imltbl.s, c_dagmodik_lz_inc_dec.s, + c_dagmodim_lnz_imgebl.s, c_dagmodim_lnz_imltbl.s, + c_dagmodim_lz_inc_dec.s, c_dsp32alu_a0a1s.s, c_dsp32alu_a0_pm_a1.s, + c_dsp32alu_aa_absabs.s, c_dsp32alu_a_abs_a.s, c_dsp32alu_aa_negneg.s, + c_dsp32alu_absabs.s, c_dsp32alu_abs.s, c_dsp32alu_alhwx.s, + c_dsp32alu_a_neg_a.s, c_dsp32alu_awx.s, c_dsp32alu_byteop1ew.s, + c_dsp32alu_byteop2.s, c_dsp32alu_byteop3.s, c_dsp32alu_bytepack.s, + c_dsp32alu_byteunpack.s, c_dsp32alu_disalnexcpt.s, c_dsp32alu_maxmax.s, + c_dsp32alu_max.s, c_dsp32alu_minmin.s, c_dsp32alu_min.s, + c_dsp32alu_mix.s, c_dsp32alu_rh_m.s, c_dsp32alu_rh_p.s, + c_dsp32alu_rh_rnd12_m.s, c_dsp32alu_rh_rnd12_p.s, + c_dsp32alu_rh_rnd20_m.s, c_dsp32alu_rh_rnd20_p.s, + c_dsp32alu_r_lh_a0pa1.s, c_dsp32alu_rlh_rnd.s, c_dsp32alu_rl_m.s, + c_dsp32alu_rl_p.s, c_dsp32alu_rl_rnd12_m.s, c_dsp32alu_rl_rnd12_p.s, + c_dsp32alu_rl_rnd20_m.s, c_dsp32alu_rl_rnd20_p.s, c_dsp32alu_rmm.s, + c_dsp32alu_rmp.s, c_dsp32alu_rm.s, c_dsp32alu_r_negneg.s, + c_dsp32alu_rpm.s, c_dsp32alu_rpp.s, c_dsp32alu_rp.s, + c_dsp32alu_rr_lph_a1a0.s, c_dsp32alu_rrpm_aa.s, c_dsp32alu_rrpmmp.s, + c_dsp32alu_rrpmmp_sft.s, c_dsp32alu_rrpmmp_sft_x.s, c_dsp32alu_rrpm.s, + c_dsp32alu_rrppmm.s, c_dsp32alu_rrppmm_sft.s, + c_dsp32alu_rrppmm_sft_x.s, c_dsp32alu_saa.s, c_dsp32alu_sat_aa.S, + c_dsp32alu_search.s, c_dsp32alu_sgn.s, c_dsp32mac_a1a0_iuw32.s, + c_dsp32mac_a1a0_m.s, c_dsp32mac_a1a0.s, c_dsp32mac_dr_a0_ih.s, + c_dsp32mac_dr_a0_i.s, c_dsp32mac_dr_a0_is.s, c_dsp32mac_dr_a0_iu.s, + c_dsp32mac_dr_a0_m.s, c_dsp32mac_dr_a0.s, c_dsp32mac_dr_a0_s.s, + c_dsp32mac_dr_a0_t.s, c_dsp32mac_dr_a0_tu.s, c_dsp32mac_dr_a0_u.s, + c_dsp32mac_dr_a1a0_iutsh.s, c_dsp32mac_dr_a1a0_m.s, + c_dsp32mac_dr_a1a0.s, c_dsp32mac_dr_a1_ih.s, c_dsp32mac_dr_a1_i.s, + c_dsp32mac_dr_a1_is.s, c_dsp32mac_dr_a1_iu.s, c_dsp32mac_dr_a1_m.s, + c_dsp32mac_dr_a1.s, c_dsp32mac_dr_a1_s.s, c_dsp32mac_dr_a1_t.s, + c_dsp32mac_dr_a1_tu.s, c_dsp32mac_dr_a1_u.s, c_dsp32mac_mix.s, + c_dsp32mac_pair_a0_i.s, c_dsp32mac_pair_a0_is.s, + c_dsp32mac_pair_a0_m.s, c_dsp32mac_pair_a0.s, c_dsp32mac_pair_a0_s.s, + c_dsp32mac_pair_a0_u.s, c_dsp32mac_pair_a1a0_i.s, + c_dsp32mac_pair_a1a0_is.s, c_dsp32mac_pair_a1a0_m.s, + c_dsp32mac_pair_a1a0.s, c_dsp32mac_pair_a1a0_s.s, + c_dsp32mac_pair_a1a0_u.s, c_dsp32mac_pair_a1_i.s, + c_dsp32mac_pair_a1_is.s, c_dsp32mac_pair_a1_m.s, c_dsp32mac_pair_a1.s, + c_dsp32mac_pair_a1_s.s, c_dsp32mac_pair_a1_u.s, c_dsp32mac_pair_mix.s, + c_dsp32mult_dr_ih.s, c_dsp32mult_dr_i.s, c_dsp32mult_dr_is.s, + c_dsp32mult_dr_iu.s, c_dsp32mult_dr_m_i.s, c_dsp32mult_dr_m_iutsh.s, + c_dsp32mult_dr_mix.s, c_dsp32mult_dr_m.s, c_dsp32mult_dr_m_s.s, + c_dsp32mult_dr_m_t.s, c_dsp32mult_dr_m_u.s, c_dsp32mult_dr.s, + c_dsp32mult_dr_s.s, c_dsp32mult_dr_t.s, c_dsp32mult_dr_tu.s, + c_dsp32mult_dr_u.s, c_dsp32mult_pair_i.s, c_dsp32mult_pair_is.s, + c_dsp32mult_pair_m_i.s, c_dsp32mult_pair_m_is.s, c_dsp32mult_pair_m.s, + c_dsp32mult_pair_m_s.s, c_dsp32mult_pair_m_u.s, c_dsp32mult_pair.s, + c_dsp32mult_pair_s.s, c_dsp32mult_pair_u.s, c_dsp32shift_a0alr.s, + c_dsp32shift_af.s, c_dsp32shift_af_s.s, c_dsp32shift_ahalf_ln.s, + c_dsp32shift_ahalf_ln_s.s, c_dsp32shift_ahalf_lp.s, + c_dsp32shift_ahalf_lp_s.s, c_dsp32shift_ahalf_rn.s, + c_dsp32shift_ahalf_rn_s.s, c_dsp32shift_ahalf_rp.s, + c_dsp32shift_ahalf_rp_s.s, c_dsp32shift_ahh.s, c_dsp32shift_ahh_s.s, + c_dsp32shift_align16.s, c_dsp32shift_align24.s, c_dsp32shift_align8.s, + c_dsp32shift_amix.s, c_dsp32shift_bitmux.s, c_dsp32shift_bxor.s, + c_dsp32shift_expadj_h.s, c_dsp32shift_expadj_l.s, + c_dsp32shift_expadj_r.s, c_dsp32shift_expexp_r.s, c_dsp32shift_fdepx.s, + c_dsp32shift_fextx.s, c_dsp32shiftim_a0alr.s, c_dsp32shiftim_af.s, + c_dsp32shiftim_af_s.s, c_dsp32shiftim_ahalf_ln.s, + c_dsp32shiftim_ahalf_ln_s.s, c_dsp32shiftim_ahalf_lp.s, + c_dsp32shiftim_ahalf_lp_s.s, c_dsp32shiftim_ahalf_rn.s, + c_dsp32shiftim_ahalf_rn_s.s, c_dsp32shiftim_ahalf_rp.s, + c_dsp32shiftim_ahalf_rp_s.s, c_dsp32shiftim_ahh.s, + c_dsp32shiftim_ahh_s.s, c_dsp32shiftim_amix.s, c_dsp32shiftim_lf.s, + c_dsp32shiftim_lhalf_ln.s, c_dsp32shiftim_lhalf_lp.s, + c_dsp32shiftim_lhalf_rn.s, c_dsp32shiftim_lhalf_rp.s, + c_dsp32shiftim_lhh.s, c_dsp32shiftim_lmix.s, c_dsp32shiftim_rot.s, + c_dsp32shift_lf.s, c_dsp32shift_lhalf_ln.s, c_dsp32shift_lhalf_lp.s, + c_dsp32shift_lhalf_rn.s, c_dsp32shift_lhalf_rp.s, c_dsp32shift_lhh.s, + c_dsp32shift_lmix.s, c_dsp32shift_ones.s, c_dsp32shift_pack.s, + c_dsp32shift_rot_mix.s, c_dsp32shift_rot.s, c_dsp32shift_signbits_rh.s, + c_dsp32shift_signbits_rl.s, c_dsp32shift_signbits_r.s, + c_dsp32shift_vmax.s, c_dsp32shift_vmaxvmax.s, c_dspldst_ld_drhi_ipp.s, + c_dspldst_ld_drhi_i.s, c_dspldst_ld_dr_ippm.s, c_dspldst_ld_dr_ipp.s, + c_dspldst_ld_dr_i.s, c_dspldst_ld_drlo_ipp.s, c_dspldst_ld_drlo_i.s, + c_dspldst_st_drhi_ipp.s, c_dspldst_st_drhi_i.s, c_dspldst_st_dr_ippm.s, + c_dspldst_st_dr_ipp.s, c_dspldst_st_dr_i.s, c_dspldst_st_drlo_ipp.s, + c_dspldst_st_drlo_i.s, cec-exact-exception.S, cec-ifetch.S, + cec-multi-pending.S, cec-non-operating-env.s, cec-no-snen-reti.S, + cec-raise-reti.S, cec-snen-reti.S, cec-syscfg-ssstep.S, + cec-system-call.S, c_except_illopcode.S, c_except_sys_sstep.S, + c_except_user_mode.S, c_interr_disable_enable.S, c_interr_disable.S, + c_interr_excpt.S, c_interr_loopsetup_stld.S, c_interr_nested.S, + c_interr_nmi.S, c_interr_pending_2.S, c_interr_pending.S, + c_interr_timer_reload.S, c_interr_timer.S, c_interr_timer_tcount.S, + c_interr_timer_tscale.S, cir1.s, cir.s, c_ldimmhalf_dreg.s, + c_ldimmhalf_drhi.s, c_ldimmhalf_drlo.s, c_ldimmhalf_h_dr.s, + c_ldimmhalf_h_ibml.s, c_ldimmhalf_h_pr.s, c_ldimmhalf_l_dr.s, + c_ldimmhalf_l_ibml.s, c_ldimmhalf_l_pr.s, c_ldimmhalf_lz_dr.s, + c_ldimmhalf_lzhi_dr.s, c_ldimmhalf_lzhi_ibml.s, c_ldimmhalf_lzhi_pr.s, + c_ldimmhalf_lz_ibml.s, c_ldimmhalf_lz_pr.s, c_ldimmhalf_pibml.s, + c_ldstidxl_ld_dr_b.s, c_ldstidxl_ld_dreg.s, c_ldstidxl_ld_dr_h.s, + c_ldstidxl_ld_dr_xb.s, c_ldstidxl_ld_dr_xh.s, c_ldstidxl_ld_preg.s, + c_ldstidxl_st_dr_b.s, c_ldstidxl_st_dreg.s, c_ldstidxl_st_dr_h.s, + c_ldstidxl_st_preg.s, c_ldstiifp_ld_dreg.s, c_ldstiifp_ld_preg.s, + c_ldstiifp_st_dreg.s, c_ldstiifp_st_preg.s, c_ldstii_ld_dreg.s, + c_ldstii_ld_dr_h.s, c_ldstii_ld_dr_xh.s, c_ldstii_ld_preg.s, + c_ldstii_st_dreg.s, c_ldstii_st_dr_h.s, c_ldstii_st_preg.s, + c_ldst_ld_d_p_b.s, c_ldst_ld_d_p_h.s, c_ldst_ld_d_p_mm_b.s, + c_ldst_ld_d_p_mm_h.s, c_ldst_ld_d_p_mm.s, c_ldst_ld_d_p_mm_xb.s, + c_ldst_ld_d_p_mm_xh.s, c_ldst_ld_d_p_pp_b.s, c_ldst_ld_d_p_pp_h.s, + c_ldst_ld_d_p_ppmm_hbx.s, c_ldst_ld_d_p_pp.s, c_ldst_ld_d_p_pp_xb.s, + c_ldst_ld_d_p_pp_xh.s, c_ldst_ld_d_p.s, c_ldst_ld_d_p_xb.s, + c_ldst_ld_d_p_xh.s, c_ldst_ld_p_p_mm.s, c_ldst_ld_p_p_pp.s, + c_ldst_ld_p_p.s, c_ldstpmod_ld_dreg.s, c_ldstpmod_ld_dr_hi.s, + c_ldstpmod_ld_dr_lo.s, c_ldstpmod_ld_h_xh.s, c_ldstpmod_ld_lohi.s, + c_ldstpmod_st_dreg.s, c_ldstpmod_st_dr_hi.s, c_ldstpmod_st_dr_lo.s, + c_ldstpmod_st_lohi.s, c_ldst_st_p_d_b.s, c_ldst_st_p_d_h.s, + c_ldst_st_p_d_mm_b.s, c_ldst_st_p_d_mm_h.s, c_ldst_st_p_d_mm.s, + c_ldst_st_p_d_pp_b.s, c_ldst_st_p_d_pp_h.s, c_ldst_st_p_d_pp.s, + c_ldst_st_p_d.s, c_ldst_st_p_p_mm.s, c_ldst_st_p_p_pp.s, + c_ldst_st_p_p.s, c_linkage.s, cli-sti.s, c_logi2op_alshft_mix.s, + c_logi2op_arith_shft.s, c_logi2op_bitclr.s, c_logi2op_bitset.s, + c_logi2op_bittgl.s, c_logi2op_bittst.s, c_logi2op_log_l_shft_astat.S, + c_logi2op_log_l_shft.s, c_logi2op_log_r_shft_astat.S, + c_logi2op_log_r_shft.s, c_logi2op_nbittst.s, c_loopsetup_nested_bot.s, + c_loopsetup_nested_prelc.s, c_loopsetup_nested.s, + c_loopsetup_nested_top.s, c_loopsetup_overlap.s, + c_loopsetup_preg_div2_lc0.s, c_loopsetup_preg_div2_lc1.s, + c_loopsetup_preg_lc0.s, c_loopsetup_preg_lc1.s, + c_loopsetup_preg_stld.s, c_loopsetup_prelc.s, c_loopsetup_topbotcntr.s, + c_mmr_interr_ctl.s, c_mmr_loop.S, c_mmr_loop_user_except.S, + c_mmr_ppop_illegal_adr.S, c_mmr_ppopm_illegal_adr.S, c_mmr_timer.S, + c_mode_supervisor.S, c_mode_user.S, c_mode_user_superivsor.S, cmpacc.s, + cmpdreg.S, c_multi_issue_dsp_ld_ld.s, c_multi_issue_dsp_ldst_1.s, + c_multi_issue_dsp_ldst_2.s, compare.s, conv_enc_gen.s, + c_progctrl_call_pcpr.s, c_progctrl_call_pr.s, + c_progctrl_clisti_interr.S, c_progctrl_csync_mmr.S, + c_progctrl_except_rtx.S, c_progctrl_excpt.S, c_progctrl_jump_pcpr.s, + c_progctrl_jump_pr.s, c_progctrl_nop.s, c_progctrl_raise_rt_i_n.S, + c_progctrl_rts.s, c_ptr2op_pr_neg_pr.s, c_ptr2op_pr_sft_2_1.s, + c_ptr2op_pr_shadd_1_2.s, c_pushpopmultiple_dp_pair.s, + c_pushpopmultiple_dp.s, c_pushpopmultiple_dreg.s, + c_pushpopmultiple_preg.s, c_regmv_acc_acc.s, c_regmv_dag_lz_dep.s, + c_regmv_dr_acc_acc.s, c_regmv_dr_dep_nostall.s, c_regmv_dr_dr.s, + c_regmv_dr_imlb.s, c_regmv_dr_pr.s, c_regmv_imlb_dep_nostall.s, + c_regmv_imlb_dep_stall.s, c_regmv_imlb_dr.s, c_regmv_imlb_imlb.s, + c_regmv_imlb_pr.s, c_regmv_pr_dep_nostall.s, c_regmv_pr_dep_stall.s, + c_regmv_pr_dr.s, c_regmv_pr_imlb.s, c_regmv_pr_pr.s, + c_seq_ac_raise_mv_ppop.S, c_seq_ac_raise_mv.S, + c_seq_ac_regmv_pushpop.S, c_seq_dec_raise_pushpop.S, + c_seq_ex1_brcc_mv_pop.S, c_seq_ex1_call_mv_pop.S, c_seq_ex1_j_mv_pop.S, + c_seq_ex1_raise_brcc_mv_pop.S, c_seq_ex1_raise_call_mv_pop.S, + c_seq_ex1_raise_j_mv_pop.S, c_seq_ex2_brcc_mp_mv_pop.S, + c_seq_ex2_mmrj_mvpop.S, c_seq_ex2_mmr_mvpop.S, + c_seq_ex2_raise_mmrj_mvpop.S, c_seq_ex2_raise_mmr_mvpop.S, + c_seq_ex3_ls_brcc_mvp.S, c_seq_ex3_ls_mmrj_mvp.S, + c_seq_ex3_ls_mmr_mvp.S, c_seq_ex3_raise_ls_mmrj_mvp.S, + c_seq_wb_cs_lsmmrj_mvp.S, c_seq_wb_raisecs_lsmmrj_mvp.S, + c_seq_wb_rti_lsmmrj_mvp.S, c_seq_wb_rtn_lsmmrj_mvp.S, + c_seq_wb_rtx_lsmmrj_mvp.S, c_ujump.s, cycles.s, d0.s, d1.s, d2.s, + dbg_brprd_ntkn_src_kill.S, dbg_brtkn_nprd_src_kill.S, + dbg_jmp_src_kill.S, dbg_tr_basic.S, dbg_tr_simplejp.S, dbg_tr_tbuf0.S, + dbg_tr_umode.S, disalnexcpt_implicit.S, div0.s, divq.s, dotproduct2.s, + dotproduct.s, double_prec_mult.s, dsp_a4.s, dsp_a7.s, dsp_a8.s, + dsp_d0.s, dsp_d1.s, dsp_neg.S, dsp_s1.s, e0.s, edn_snafu.s, + eu_dsp32mac_s.s, events.s, f221.s, fact.s, fir.s, fsm.s, greg2.s, + hwloop-bits.S, hwloop-branch-in.s, hwloop-branch-out.s, + hwloop-lt-bits.s, hwloop-nested.s, i0.s, iir.s, issue103.s, issue109.s, + issue112.s, issue113.s, issue117.s, issue118.s, issue119.s, issue121.s, + issue123.s, issue124.s, issue125.s, issue126.s, issue127.s, issue129.s, + issue139.S, issue140.S, issue142.s, issue144.s, issue146.S, issue175.s, + issue205.s, issue257.s, issue272.S, issue83.s, issue89.s, l0.s, + l0shift.s, l2_loop.s, link-2.s, link.s, lmu_cplb_multiple0.S, + lmu_cplb_multiple1.S, lmu_excpt_align.S, lmu_excpt_default.S, + lmu_excpt_illaddr.S, lmu_excpt_prot0.S, lmu_excpt_prot1.S, load.s, + logic.s, loop_snafu.s, loop_strncpy.s, lp0.s, lp1.s, lsetup.s, + m0boundary.s, m10.s, m11.s, m12.s, m13.s, m14.s, m15.s, m16.s, m17.s, + m1.S, m2.s, m3.s, m4.s, m5.s, m6.s, m7.s, m8.s, m9.s, mac2halfreg.S, + Makefile, math.s, max_min_flags.s, mc_s2.s, mdma-32bit-1d.c, + mdma-32bit-1d-neg-count.c, mdma-8bit-1d.c, mdma-8bit-1d-neg-count.c, + mdma-skel.h, mem3.s, mmr-exception.s, move.s, msa_acp_5_10.s, + msa_acp_5.10.S, msa_acp_5.12_1.S, msa_acp_5.12_2.S, mult.s, neg-2.S, + neg-3.S, neg.S, nshift.s, PN_generator.s, pr.s, push-pop-multiple.s, + pushpopreg_1.s, push-pop.s, quadaddsub.s, random_0001.s, random_0002.S, + random_0003.S, random_0004.S, random_0005.S, random_0006.S, + random_0007.S, random_0008.S, random_0009.S, random_0010.S, + random_0011.S, random_0012.S, random_0013.S, random_0031.S, + random_0033.S, random_0034.S, run-tests.sh, s0.s, s10.s, s11.s, s12.s, + s13.s, s14.s, s15.s, s16.s, s17.s, s18.s, s19.s, s1.s, s20.s, s21.s, + s2.s, s30.s, s3.s, s4.s, s5.s, s6.s, s7.s, s8.s, s9.s, saatest.s, + se_all16bitopcodes.S, se_all32bitopcodes.lds, se_all32bitopcodes.S, + se_brtarget_stall.S, se_bug_ui2.S, se_bug_ui3.S, se_bug_ui.S, + se_cc2stat_haz.S, se_cc_kill.S, se_cof.S, se_event_quad.S, + se_excpt_dagprotviol.S, se_excpt_ifprotviol.S, se_excpt_ssstep.S, + se_illegalcombination.S, se_kills2.S, se_kill_wbbr.S, + se_loop_disable.S, se_loop_kill_01.S, se_loop_kill_dcr_01.S, + se_loop_kill_dcr.S, se_loop_kill.S, se_loop_lr.S, + se_loop_mv2lb_stall.S, se_loop_mv2lc.S, se_loop_mv2lc_stall.S, + se_loop_mv2lt_stall.S, se_loop_nest_ppm_1.S, se_loop_nest_ppm_2.S, + se_loop_nest_ppm.S, se_loop_ppm_1.S, se_loop_ppm_int.S, se_loop_ppm.S, + se_lsetup_kill.S, se_misaligned_fetch.S, se_more_ret_haz.S, se_mv2lp.S, + se_oneins_zoff.S, se_popkill.S, seqstat.s, se_regmv_usp_sysreg.S, + se_rets_hazard.s, se_rts_rti.S, se_ssstep_dagprotviol.S, se_ssync.S, + se_stall_if2.S, se_undefinedinstruction1.S, se_undefinedinstruction2.S, + se_undefinedinstruction3.S, se_undefinedinstruction4.S, + se_usermode_protviol.S, sign.s, simple0.s, sri.s, stk2.s, stk3.s, + stk4.s, stk5.s, stk6.s, stk.s, syscfg.s, tar10622.s, test-dma.h, + test.h, testset2.s, testset.s, testutils.inc, unlink.S, up0.s, usp.S, + vec-abs-2.S, vec-abs-3.S, vec-abs.S, vecadd.s, vec-neg-2.S, + vec-neg-3.S, vec-neg.S, viterbi2.s, vit_max.s, wtf.s, x1.s, zcall.s, + zeroflagrnd.s: New files. diff --git a/sim/testsuite/bpf/ChangeLog b/sim/testsuite/bpf/ChangeLog deleted file mode 100644 index 5814a7c..0000000 --- a/sim/testsuite/bpf/ChangeLog +++ /dev/null @@ -1,28 +0,0 @@ -2021-04-08 Mike Frysinger - - * allinsn.exp (arch): Delete. - -2021-02-13 Mike Frysinger - - * allinsn.exp: Define arch. - -2020-09-08 David Faust - - * alu.s: Correct div and mod tests. - * alu32.s: Likewise. - -2020-08-04 David Faust - Jose E. Marchesi - - * allinsn.exp: New file. - * alu.s: Likewise. - * alu32.s: Likewise. - * endbe.s: Likewise. - * endle.s: Likewise. - * jmp.s: Likewise. - * jmp32.s: Likewise. - * ldabs.s: Likewise. - * mem.s: Likewise. - * mov.s: Likewise. - * testutils.inc: Likewise. - * xadd.s: Likewise. diff --git a/sim/testsuite/bpf/ChangeLog-2021 b/sim/testsuite/bpf/ChangeLog-2021 new file mode 100644 index 0000000..5814a7c --- /dev/null +++ b/sim/testsuite/bpf/ChangeLog-2021 @@ -0,0 +1,28 @@ +2021-04-08 Mike Frysinger + + * allinsn.exp (arch): Delete. + +2021-02-13 Mike Frysinger + + * allinsn.exp: Define arch. + +2020-09-08 David Faust + + * alu.s: Correct div and mod tests. + * alu32.s: Likewise. + +2020-08-04 David Faust + Jose E. Marchesi + + * allinsn.exp: New file. + * alu.s: Likewise. + * alu32.s: Likewise. + * endbe.s: Likewise. + * endle.s: Likewise. + * jmp.s: Likewise. + * jmp32.s: Likewise. + * ldabs.s: Likewise. + * mem.s: Likewise. + * mov.s: Likewise. + * testutils.inc: Likewise. + * xadd.s: Likewise. diff --git a/sim/testsuite/cr16/ChangeLog b/sim/testsuite/cr16/ChangeLog deleted file mode 100644 index 68353f0..0000000 --- a/sim/testsuite/cr16/ChangeLog +++ /dev/null @@ -1,60 +0,0 @@ -2021-04-08 Mike Frysinger - - * allinsn.exp (arch): Delete. - * misc.exp: Likewise. - -2021-02-13 Mike Frysinger - - * allinsn.exp, misc.exp: Define arch. - -2015-12-24 Mike Frysinger - - * allinsn.exp: Append --load-vma to global_sim_options. - * misc.exp: Likewise. - -2015-03-29 Mike Frysinger - - PR sim/12385 - * testutils.inc (START): Add _start symbol. - -2008-05-02 M R Swami Reddy - - * cbitb.cgs, cbitw.cgs, sbitb.cgs, sbitw.cgs, tbit.cgs, tbitb.cgs, - tbitw.cgs, hw-trap.ms, uread16.ms, uread32.ms: New testcases. - addb.cgs, addd.cgs, addi.cgs, andb.cgs, andd.cgs, andw.cgs, ashub.cgs, - ashub_i.cgs, ashud.cgs, ashud_i.cgs, ashuw.cgs, ashuw_i.cgs, cmpi.cgs, - cmpw.cgs, jlt.cgs, jump.cgs, loadd.cgs, loadw.cgs, lshb.cgs, lshb_i.cgs, - lshd.cgs, lshd_i.cgs, lshw.cgs, lshw_i.cgs, movb.cgs, movd.cgs, - movw.cgs, movxb.cgs, movxw.cgs, movzb.cgs, movzw.cgs, mulb.cgs, - muluw.cgs, mulw.cgs, orb.cgs, ord.cgs, orw.cgs, pop1.cgs, pop2.cgs, - pop3.cgs, popret1.cgs, popret2.cgs, popret3.cgs, push1.cgs, push2.cgs, - push3.cgs: Update testcase comment. - bnc8.cgs, bnc24.cgs and ret.cgs: Removed. - -2008-04-08 M R Swami Reddy - - * allinsn.exp: Remove target_alias and global_ld_options. - -2008-02-12 M R Swami Reddy - - * allinsn.exp, misc.exp: New files: Test scripts - testutils.inc: New file: Test macros. - addb.cgs, addd.cgs, addi.cgs, addw.cgs, andb.cgs, andd.cgs, andw.cgs, - ashub.cgs, ashub_i.cgs, ashud.cgs, ashud_i.cgs, ashuw.cgs, ashuw_i.cgs, - bal1_24.cgs, bal2_24.cgs, bcc.cgs, bcs.cgs, beq0b.cgs, beq0w.cgs, - beq.cgs, bge.cgs, bgt.cgs, bhi.cgs, bhs.cgs, bht.cgs, blo.cgs, bls.cgs, - blt.cgs, bnc24.cgs, bnc8.cgs, bne0b.cgs, bne0w.cgs, bne.cgs, br.cgs, - cmpb.cgs, cmpb_i.cgs, cmpd.cgs, cmpd_i.cgs, cmpi.cgs, cmpw.cgs, - cmpw_i.cgs, excp.cgs, hello.ms, jal.cgs, jcc.cgs, jcs.cgs, jeq.cgs, - jfc.cgs, jfs.cgs, jge.cgs, jgt.cgs, jhi.cgs, jhs.cgs, jlo.cgs, jls.cgs, - jlt.cgs, jne.cgs, jump.cgs, loadb.cgs, loadd.cgs, loadm.cgs, loadmp.cgs, - loadw.cgs, lprd-sprd.cgs, lpr-spr.cgs, lshb.cgs, lshb_i.cgs, lshd.cgs, - lshd_i.cgs, lshw.cgs, lshw_i.cgs, macqw.cgs, macsw.cgs, macuw.cgs, - movb.cgs, movd.cgs, movw.cgs, movxb.cgs, movxw.cgs, movzb.cgs, - movzw.cgs, mulb.cgs, mulsb.cgs, mulsw.cgs, muluw.cgs, mulw.cgs, - nop.cgs, orb.cgs, ord.cgs, orw.cgs, pop1.cgs, pop2.cgs, pop3.cgs, - popret1.cgs, popret2.cgs, popret3.cgs, push1.cgs, push2.cgs, push3.cgs, - ret.cgs, scc.cgs, scs.cgs, seq.cgs, sfc.cgs, sfs.cgs, sge.cgs, sgt.cgs, - shi.cgs, shs.cgs, slo.cgs, sls.cgs, slt.cgs, sne.cgs, storb.cgs, - stord.cgs, storw.cgs, subb.cgs, subd.cgs, subi.cgs, subw.cgs, - xorb.cgs, xord.cgs, xorw.cgs: New files diff --git a/sim/testsuite/cr16/ChangeLog-2021 b/sim/testsuite/cr16/ChangeLog-2021 new file mode 100644 index 0000000..68353f0 --- /dev/null +++ b/sim/testsuite/cr16/ChangeLog-2021 @@ -0,0 +1,60 @@ +2021-04-08 Mike Frysinger + + * allinsn.exp (arch): Delete. + * misc.exp: Likewise. + +2021-02-13 Mike Frysinger + + * allinsn.exp, misc.exp: Define arch. + +2015-12-24 Mike Frysinger + + * allinsn.exp: Append --load-vma to global_sim_options. + * misc.exp: Likewise. + +2015-03-29 Mike Frysinger + + PR sim/12385 + * testutils.inc (START): Add _start symbol. + +2008-05-02 M R Swami Reddy + + * cbitb.cgs, cbitw.cgs, sbitb.cgs, sbitw.cgs, tbit.cgs, tbitb.cgs, + tbitw.cgs, hw-trap.ms, uread16.ms, uread32.ms: New testcases. + addb.cgs, addd.cgs, addi.cgs, andb.cgs, andd.cgs, andw.cgs, ashub.cgs, + ashub_i.cgs, ashud.cgs, ashud_i.cgs, ashuw.cgs, ashuw_i.cgs, cmpi.cgs, + cmpw.cgs, jlt.cgs, jump.cgs, loadd.cgs, loadw.cgs, lshb.cgs, lshb_i.cgs, + lshd.cgs, lshd_i.cgs, lshw.cgs, lshw_i.cgs, movb.cgs, movd.cgs, + movw.cgs, movxb.cgs, movxw.cgs, movzb.cgs, movzw.cgs, mulb.cgs, + muluw.cgs, mulw.cgs, orb.cgs, ord.cgs, orw.cgs, pop1.cgs, pop2.cgs, + pop3.cgs, popret1.cgs, popret2.cgs, popret3.cgs, push1.cgs, push2.cgs, + push3.cgs: Update testcase comment. + bnc8.cgs, bnc24.cgs and ret.cgs: Removed. + +2008-04-08 M R Swami Reddy + + * allinsn.exp: Remove target_alias and global_ld_options. + +2008-02-12 M R Swami Reddy + + * allinsn.exp, misc.exp: New files: Test scripts + testutils.inc: New file: Test macros. + addb.cgs, addd.cgs, addi.cgs, addw.cgs, andb.cgs, andd.cgs, andw.cgs, + ashub.cgs, ashub_i.cgs, ashud.cgs, ashud_i.cgs, ashuw.cgs, ashuw_i.cgs, + bal1_24.cgs, bal2_24.cgs, bcc.cgs, bcs.cgs, beq0b.cgs, beq0w.cgs, + beq.cgs, bge.cgs, bgt.cgs, bhi.cgs, bhs.cgs, bht.cgs, blo.cgs, bls.cgs, + blt.cgs, bnc24.cgs, bnc8.cgs, bne0b.cgs, bne0w.cgs, bne.cgs, br.cgs, + cmpb.cgs, cmpb_i.cgs, cmpd.cgs, cmpd_i.cgs, cmpi.cgs, cmpw.cgs, + cmpw_i.cgs, excp.cgs, hello.ms, jal.cgs, jcc.cgs, jcs.cgs, jeq.cgs, + jfc.cgs, jfs.cgs, jge.cgs, jgt.cgs, jhi.cgs, jhs.cgs, jlo.cgs, jls.cgs, + jlt.cgs, jne.cgs, jump.cgs, loadb.cgs, loadd.cgs, loadm.cgs, loadmp.cgs, + loadw.cgs, lprd-sprd.cgs, lpr-spr.cgs, lshb.cgs, lshb_i.cgs, lshd.cgs, + lshd_i.cgs, lshw.cgs, lshw_i.cgs, macqw.cgs, macsw.cgs, macuw.cgs, + movb.cgs, movd.cgs, movw.cgs, movxb.cgs, movxw.cgs, movzb.cgs, + movzw.cgs, mulb.cgs, mulsb.cgs, mulsw.cgs, muluw.cgs, mulw.cgs, + nop.cgs, orb.cgs, ord.cgs, orw.cgs, pop1.cgs, pop2.cgs, pop3.cgs, + popret1.cgs, popret2.cgs, popret3.cgs, push1.cgs, push2.cgs, push3.cgs, + ret.cgs, scc.cgs, scs.cgs, seq.cgs, sfc.cgs, sfs.cgs, sge.cgs, sgt.cgs, + shi.cgs, shs.cgs, slo.cgs, sls.cgs, slt.cgs, sne.cgs, storb.cgs, + stord.cgs, storw.cgs, subb.cgs, subd.cgs, subi.cgs, subw.cgs, + xorb.cgs, xord.cgs, xorw.cgs: New files diff --git a/sim/testsuite/cris/ChangeLog b/sim/testsuite/cris/ChangeLog deleted file mode 100644 index 121b6f3..0000000 --- a/sim/testsuite/cris/ChangeLog +++ /dev/null @@ -1,213 +0,0 @@ -2021-04-08 Mike Frysinger - - * asm/asm.exp (arch): Delete. - * c/c.exp, hw/rv-n-cris/rvc.exp: Likewise. - -2021-02-13 Mike Frysinger - - * asm/asm.exp, c/c.exp, hw/rv-n-cris/rvc.exp: Define arch. - -2021-01-15 Mike Frysinger - - * c/c.exp: Change sim_run return to return_code. Set status to - pass/fail based on return_code. - * hw/rv-n-cris/rvc.exp (sim_has_rv_and_cris): Compare return_code - to 0. - -2021-01-09 Mike Frysinger - - * readlink4.c (main): Change rindex to strrchr. - -2021-01-07 Mike Frysinger - - PR ld/13900 - * c/helloaout.c: Disable test - -2021-01-07 Mike Frysinger - - * c/c.exp [cris*-*-elf] (CFLAGS_FOR_TARGET): Add -sim. - -2021-01-07 Mike Frysinger - - * c/kill2.c: Include unistd.h. - * c/pipe1.c, c/sched1.c, c/sched2.c, c/sched3.c, c/sched4.c, - c/sig5.c, c/sig8.c: Likewise. - * c/openpf1.c (main): Change close to fclose. - * c/openpf2.c: Likewise. - -2016-01-04 Mike Frysinger - - * asm/opterr1.ms: Update expected output. - * asm/opterr2.ms: Likewise. - -2015-12-25 Mike Frysinger - - * asm/io1.ms: Update expected output. - -2015-12-25 Mike Frysinger - - * hw/rv-n-cris/rvc.exp (rvdummy): Set up sane default. - -2012-03-24 Mike Frysinger - - * c/clone5.c: Update output to ignore decoded signal string. - * c/fcntl1.c, c/kill2.c, c/kill3.c, c/mprotect1.c, c/pipe5.c, - c/readlink5.c, c/rtsigprocmask1.c, c/rtsigsuspend1.c, c/sig10.c, - c/sig11.c, c/sig3.c, c/sig4.c, c/sig5.c, c/sig6.c, c/sig7.c, - c/sig8.c, c/sigreturn1.c, c/sigreturn2.c, c/syscall1.c, - c/syscall2.c, c/syscall3.c, c/syscall4.c, c/sysctl2.c: Likewise. - -2012-03-21 Mike Frysinger - - * asm/addqpc.ms: Update output to ignore decoded signal string. - * asm/boundmv32.ms, asm/fidxd.ms, asm/fidxi.ms, asm/ftagd.ms, - asm/ftagi.ms, asm/halt.ms, asm/io6.ms, asm/io7.ms, asm/io8.ms, - asm/io9.ms, asm/movecpc.ms, asm/movempc.ms, asm/movepcb.ms, - asm/movepcd.ms, asm/movepcw.ms, asm/moveqpc.ms, asm/moverbpc.ms, - asm/moverdpc.ms, asm/moverpcb.ms, asm/moverpcw.ms, asm/moverwpc.ms, - asm/movppc.ms, asm/movrss.ms, asm/movscpc.ms, asm/movsmpc.ms, - asm/movsrpc.ms, asm/movssr.ms, asm/movucpc.ms, asm/movumpc.ms, - asm/movurpc.ms, asm/msteppc1.ms, asm/msteppc2.ms, asm/msteppc3.ms, - asm/rfg.ms, asm/sbfs.ms, asm/subqpc.ms: Likewise. - -2010-10-07 Hans-Peter Nilsson - - * c/seek3.c, c/seek4.c: New tests. - -2010-08-24 Hans-Peter Nilsson - - * asm/nonvcv32.ms: Neutralize changed &&-in-macro gas syntax. - -2009-01-18 Hans-Peter Nilsson - - * asm/opterr5.ms, asm/opterr4.ms, - asm/opterr3.ms, asm/bare3.ms: New tests. - -2009-01-06 Hans-Peter Nilsson - - * c/mmap5.c, c/mmap6.c, c/mmap7.c, - c/mmap8.c, c/hellodyn3.c: New tests. - -2009-01-03 Hans-Peter Nilsson - - * c/settls1.c: New test. - * c/exitg1.c, c/exitg2.c: New tests. - * c/uname1.c: New test. - * c/mmap1.c (MMAP_FLAGS): Default-define to - MAP_PRIVATE and use this macro in the mmap call. - * c/mmap4.c: New test. - * c/access1.c: New test. - * asm/pid1.ms: New test. - -2008-12-30 Hans-Peter Nilsson - - * asm/badarch1.ms: Tweak error message match. - - * asm/badarch1.ms, c/badldso1.c, - c/badldso2.c, c/badldso3.c, - c/helloaout.c, c/hellodyn.c, - c/hellodyn2.c, c/writev1.c, - c/writev2.c: New tests. - * c/c.exp: If compiler links libc.so when attempting to - link dynamically, create symlink named "lib" to the directory - where it is found. Handle new test-case option "dynamic". - - * asm/opterr1.ms, asm/opterr2.ms: Adjust for - differences in getopt_long error message quoting. - -2007-11-08 Hans-Peter Nilsson - - * asm/x0-v10.ms, asm/x0-v32.ms: Tweak - stack-pointer match pattern for 4K host environment. - -2007-10-22 Edgar E. Iglesias - Hans-Peter Nilsson - - * asm/testutils.inc (test_move_cc): Add missing call to - test_cc. - * asm/asr.ms: Correct expected condition code flags. - * asm/boundr.ms: Ditto. - * asm/dstep.ms: Ditto. - * asm/lsr.ms: Ditto. - * asm/movecr.ms: Ditto. - * asm/mover.ms: Ditto. - * asm/neg.ms: Ditto. Use test_cc, not test_move_cc. - * asm/op3.ms: Check the condition code flags after the insn - under test. - * asm/movecrt10.ms: Update expected number of simulated - cycles. - * asm/movecrt32.ms: Ditto. - * asm/jsr.ms: Don't use local label 8. - * asm/nonvcv32.ms: New test. - -2007-10-11 Jesper Nilsson - - * c/freopen2.c: Added testcase. - -2006-10-02 Hans-Peter Nilsson - Edgar E. Iglesias - - * c/clone5.c, c/mprotect1.c, - c/rtsigprocmask1.c, c/rtsigsuspend1.c, - c/sig7.c, c/sigreturn1.c, - c/sigreturn2.c, c/syscall1.c, - c/syscall2.c, c/sysctl2.c, c/fcntl1.c, - c/readlink2.c: Add code to print ENOSYS if syscall being - tested returns ENOSYS. Add early exit where needed. Change any - existing code to print "xyzzy", not "pass". - * asm/option3.ms, asm/option4.ms, - c/clone6.c, c/fcntl2.c, - c/mprotect2.c, c/readlink11.c, - c/rtsigprocmask2.c, c/rtsigsuspend2.c, - c/sig13.c, c/sigreturn3.c, - c/sigreturn4.c, c/syscall3.c, - c/syscall4.c, c/syscall5.c, - c/syscall6.c, c/syscall7.c, - c/syscall8.c, c/sysctl3.c: New tests. - -2006-09-30 Hans-Peter Nilsson - - * c/pipe2.c: Adjust expected output. - (process): Don't write as much to the pipe as to trig the - inordinate-amount test in the sim pipe machinery. Correct test of - write return-value; check only that pipemax bytes were - successfully written. For error-case, emit strerror as well. - (main): Add a second read. - -2006-04-08 Hans-Peter Nilsson - - * hw/rv-n-cris/irq6.ms: New test. - -2006-04-03 Hans-Peter Nilsson - - * hw: New directory for subdirectories with tests. - * hw/rv-n-cris: New directory with tests. - -2006-04-02 Hans-Peter Nilsson - - * asm/testutils.inc (test_h_mem): Use register prefix. - (testr_h_dr, test_h_dr, ldmem_h_gr, mvr_h_mem): Ditto. Correct - syntax. - - * asm/x0-v10.ms, asm/x0-v32.ms: Widen regexp for - stack pointer values. - -2006-02-23 Hans-Peter Nilsson - - * c/time2.c: New test. - -2006-01-10 Hans-Peter Nilsson - - * asm/x1-v10.ms, asm/x3-v10.ms, - asm/x7-v10.ms: Update expected cycle output. - -2005-12-06 Hans-Peter Nilsson - - * asm/movmp8.ms, asm/pcplus.ms: New tests. - * asm/movmp.ms: Do not write to P0, P4 or P8. - * asm/raw13.ms: Write to MOF instead of WZ (P4). - -2005-11-21 Hans-Peter Nilsson - - * asm, c: New directory with C and assembly tests for the CRIS - simulator. diff --git a/sim/testsuite/cris/ChangeLog-2021 b/sim/testsuite/cris/ChangeLog-2021 new file mode 100644 index 0000000..121b6f3 --- /dev/null +++ b/sim/testsuite/cris/ChangeLog-2021 @@ -0,0 +1,213 @@ +2021-04-08 Mike Frysinger + + * asm/asm.exp (arch): Delete. + * c/c.exp, hw/rv-n-cris/rvc.exp: Likewise. + +2021-02-13 Mike Frysinger + + * asm/asm.exp, c/c.exp, hw/rv-n-cris/rvc.exp: Define arch. + +2021-01-15 Mike Frysinger + + * c/c.exp: Change sim_run return to return_code. Set status to + pass/fail based on return_code. + * hw/rv-n-cris/rvc.exp (sim_has_rv_and_cris): Compare return_code + to 0. + +2021-01-09 Mike Frysinger + + * readlink4.c (main): Change rindex to strrchr. + +2021-01-07 Mike Frysinger + + PR ld/13900 + * c/helloaout.c: Disable test + +2021-01-07 Mike Frysinger + + * c/c.exp [cris*-*-elf] (CFLAGS_FOR_TARGET): Add -sim. + +2021-01-07 Mike Frysinger + + * c/kill2.c: Include unistd.h. + * c/pipe1.c, c/sched1.c, c/sched2.c, c/sched3.c, c/sched4.c, + c/sig5.c, c/sig8.c: Likewise. + * c/openpf1.c (main): Change close to fclose. + * c/openpf2.c: Likewise. + +2016-01-04 Mike Frysinger + + * asm/opterr1.ms: Update expected output. + * asm/opterr2.ms: Likewise. + +2015-12-25 Mike Frysinger + + * asm/io1.ms: Update expected output. + +2015-12-25 Mike Frysinger + + * hw/rv-n-cris/rvc.exp (rvdummy): Set up sane default. + +2012-03-24 Mike Frysinger + + * c/clone5.c: Update output to ignore decoded signal string. + * c/fcntl1.c, c/kill2.c, c/kill3.c, c/mprotect1.c, c/pipe5.c, + c/readlink5.c, c/rtsigprocmask1.c, c/rtsigsuspend1.c, c/sig10.c, + c/sig11.c, c/sig3.c, c/sig4.c, c/sig5.c, c/sig6.c, c/sig7.c, + c/sig8.c, c/sigreturn1.c, c/sigreturn2.c, c/syscall1.c, + c/syscall2.c, c/syscall3.c, c/syscall4.c, c/sysctl2.c: Likewise. + +2012-03-21 Mike Frysinger + + * asm/addqpc.ms: Update output to ignore decoded signal string. + * asm/boundmv32.ms, asm/fidxd.ms, asm/fidxi.ms, asm/ftagd.ms, + asm/ftagi.ms, asm/halt.ms, asm/io6.ms, asm/io7.ms, asm/io8.ms, + asm/io9.ms, asm/movecpc.ms, asm/movempc.ms, asm/movepcb.ms, + asm/movepcd.ms, asm/movepcw.ms, asm/moveqpc.ms, asm/moverbpc.ms, + asm/moverdpc.ms, asm/moverpcb.ms, asm/moverpcw.ms, asm/moverwpc.ms, + asm/movppc.ms, asm/movrss.ms, asm/movscpc.ms, asm/movsmpc.ms, + asm/movsrpc.ms, asm/movssr.ms, asm/movucpc.ms, asm/movumpc.ms, + asm/movurpc.ms, asm/msteppc1.ms, asm/msteppc2.ms, asm/msteppc3.ms, + asm/rfg.ms, asm/sbfs.ms, asm/subqpc.ms: Likewise. + +2010-10-07 Hans-Peter Nilsson + + * c/seek3.c, c/seek4.c: New tests. + +2010-08-24 Hans-Peter Nilsson + + * asm/nonvcv32.ms: Neutralize changed &&-in-macro gas syntax. + +2009-01-18 Hans-Peter Nilsson + + * asm/opterr5.ms, asm/opterr4.ms, + asm/opterr3.ms, asm/bare3.ms: New tests. + +2009-01-06 Hans-Peter Nilsson + + * c/mmap5.c, c/mmap6.c, c/mmap7.c, + c/mmap8.c, c/hellodyn3.c: New tests. + +2009-01-03 Hans-Peter Nilsson + + * c/settls1.c: New test. + * c/exitg1.c, c/exitg2.c: New tests. + * c/uname1.c: New test. + * c/mmap1.c (MMAP_FLAGS): Default-define to + MAP_PRIVATE and use this macro in the mmap call. + * c/mmap4.c: New test. + * c/access1.c: New test. + * asm/pid1.ms: New test. + +2008-12-30 Hans-Peter Nilsson + + * asm/badarch1.ms: Tweak error message match. + + * asm/badarch1.ms, c/badldso1.c, + c/badldso2.c, c/badldso3.c, + c/helloaout.c, c/hellodyn.c, + c/hellodyn2.c, c/writev1.c, + c/writev2.c: New tests. + * c/c.exp: If compiler links libc.so when attempting to + link dynamically, create symlink named "lib" to the directory + where it is found. Handle new test-case option "dynamic". + + * asm/opterr1.ms, asm/opterr2.ms: Adjust for + differences in getopt_long error message quoting. + +2007-11-08 Hans-Peter Nilsson + + * asm/x0-v10.ms, asm/x0-v32.ms: Tweak + stack-pointer match pattern for 4K host environment. + +2007-10-22 Edgar E. Iglesias + Hans-Peter Nilsson + + * asm/testutils.inc (test_move_cc): Add missing call to + test_cc. + * asm/asr.ms: Correct expected condition code flags. + * asm/boundr.ms: Ditto. + * asm/dstep.ms: Ditto. + * asm/lsr.ms: Ditto. + * asm/movecr.ms: Ditto. + * asm/mover.ms: Ditto. + * asm/neg.ms: Ditto. Use test_cc, not test_move_cc. + * asm/op3.ms: Check the condition code flags after the insn + under test. + * asm/movecrt10.ms: Update expected number of simulated + cycles. + * asm/movecrt32.ms: Ditto. + * asm/jsr.ms: Don't use local label 8. + * asm/nonvcv32.ms: New test. + +2007-10-11 Jesper Nilsson + + * c/freopen2.c: Added testcase. + +2006-10-02 Hans-Peter Nilsson + Edgar E. Iglesias + + * c/clone5.c, c/mprotect1.c, + c/rtsigprocmask1.c, c/rtsigsuspend1.c, + c/sig7.c, c/sigreturn1.c, + c/sigreturn2.c, c/syscall1.c, + c/syscall2.c, c/sysctl2.c, c/fcntl1.c, + c/readlink2.c: Add code to print ENOSYS if syscall being + tested returns ENOSYS. Add early exit where needed. Change any + existing code to print "xyzzy", not "pass". + * asm/option3.ms, asm/option4.ms, + c/clone6.c, c/fcntl2.c, + c/mprotect2.c, c/readlink11.c, + c/rtsigprocmask2.c, c/rtsigsuspend2.c, + c/sig13.c, c/sigreturn3.c, + c/sigreturn4.c, c/syscall3.c, + c/syscall4.c, c/syscall5.c, + c/syscall6.c, c/syscall7.c, + c/syscall8.c, c/sysctl3.c: New tests. + +2006-09-30 Hans-Peter Nilsson + + * c/pipe2.c: Adjust expected output. + (process): Don't write as much to the pipe as to trig the + inordinate-amount test in the sim pipe machinery. Correct test of + write return-value; check only that pipemax bytes were + successfully written. For error-case, emit strerror as well. + (main): Add a second read. + +2006-04-08 Hans-Peter Nilsson + + * hw/rv-n-cris/irq6.ms: New test. + +2006-04-03 Hans-Peter Nilsson + + * hw: New directory for subdirectories with tests. + * hw/rv-n-cris: New directory with tests. + +2006-04-02 Hans-Peter Nilsson + + * asm/testutils.inc (test_h_mem): Use register prefix. + (testr_h_dr, test_h_dr, ldmem_h_gr, mvr_h_mem): Ditto. Correct + syntax. + + * asm/x0-v10.ms, asm/x0-v32.ms: Widen regexp for + stack pointer values. + +2006-02-23 Hans-Peter Nilsson + + * c/time2.c: New test. + +2006-01-10 Hans-Peter Nilsson + + * asm/x1-v10.ms, asm/x3-v10.ms, + asm/x7-v10.ms: Update expected cycle output. + +2005-12-06 Hans-Peter Nilsson + + * asm/movmp8.ms, asm/pcplus.ms: New tests. + * asm/movmp.ms: Do not write to P0, P4 or P8. + * asm/raw13.ms: Write to MOF instead of WZ (P4). + +2005-11-21 Hans-Peter Nilsson + + * asm, c: New directory with C and assembly tests for the CRIS + simulator. diff --git a/sim/testsuite/d10v/ChangeLog b/sim/testsuite/d10v/ChangeLog deleted file mode 100644 index f50a384..0000000 --- a/sim/testsuite/d10v/ChangeLog +++ /dev/null @@ -1,151 +0,0 @@ -2021-04-08 Mike Frysinger - - * allinsn.exp (arch): Delete. - -2021-02-13 Mike Frysinger - - * allinsn.exp: Define arch. - -2021-01-15 Mike Frysinger - - * allinsn.exp: New file. - * configure, configure.ac, loop.s, Makefile.in: Deleted. - -2020-10-06 Andrew Burgess - - * configure: Regnerate. - * configure.ac (AC_CONFIG_AUX_DIR): Update. - -2015-03-30 Mike Frysinger - - * Makefile.in (RUNFLAGS_FOR_TARGET): Set to --environment operating. - -2009-08-22 Ralf Wildenhues - - * configure: Regenerate. - -2005-01-07 Andrew Cagney - - * configure.ac: Rename configure.in, require autoconf 2.59. - * configure: Re-generate. - -Tue Apr 18 16:32:07 2000 Andrew Cagney - - * t-rie-xx.s (test_rie_xx): New test. - * Makefile.in (TESTS): Update. - -Tue Feb 22 17:36:34 2000 Andrew Cagney - - * Makefile.in: Force d10v into operating mode. - -Mon Jan 3 00:17:28 2000 Andrew Cagney - - * t-ae-ld-d.s, t-ae-ld-i.s, t-ae-ld-id.s, t-ae-ld-im.s , - t-ae-ld-ip.s, t-ae-ld2w-d.s, t-ae-ld2w-i.s, t-ae-ld2w-id.s , - t-ae-ld2w-im.s, t-ae-ld2w-ip.s, t-ae-st-d.s, t-ae-st-i.s , - t-ae-st-id.s, t-ae-st-im.s, t-ae-st-ip.s, t-ae-st-is.s , - t-ae-st2w-d.s, t-ae-st2w-i.s, t-ae-st2w-id.s, t-ae-st2w-im.s , - t-ae-st2w-ip.s, t-ae-st2w-is.s: New tests. Check that an address - exception occures when a word/two-word load/store is not word - aligned. - * Makefile.in (TESTS): Update. - -Fri Oct 29 18:36:34 1999 Andrew Cagney - - * t-mvtc.s: Check that the user can not modify the DM bit in the - BPSW or DPSW. - -Thu Oct 28 01:47:26 1999 Andrew Cagney - - * t-mvtc.s: Update. Check that user can not modify DM bit. - -Wed Sep 8 19:34:55 MDT 1999 Diego Novillo - - * t-ld-st.s: New file. - * t-sac.s: New file. - * t-sachi.s: New file. - * t-slae.s: New file. - -1999-01-13 Jason Molenda (jsm@bugshack.cygnus.com) - - * t-sadd.s: New file. - * Makefile.in (TESTS): Add t-sadd. - -Mon Feb 16 09:20:57 1998 Andrew Cagney - - * t-macros.i (VEC_*): Define. - (DMAP_REG, DMAP_BASE, DMAP_MASK): Define. - (IMAP[01]_REG): Define. - - * t-rdt.s (test_tdt): New file. - - * t-dbt.s (test_dbt): New file. - - * Makefile.in (TESTS): Add t-rdt and t-dbt. - - -Fri Feb 13 16:21:13 1998 Andrew Cagney - - * t-sp.s: New test. - * Makefile.in (TESTS): Update. - -Wed Feb 11 17:58:50 1998 Andrew Cagney - - * t-macros.i: Update trap calls, func in r4, args in - r0... - (start): Force r0 to zero. - - * t-sub2w.s: Ditto. - -Tue Dec 9 10:41:44 1997 Andrew Cagney - - * t-rte.s (success): New file. - * Makefile.in: Update. - - * t-rep.s: Check rep repeats correct number of times. - -Fri Dec 5 10:11:18 1997 Andrew Cagney - - * t-mvtc.s: Check for stuck-zero in MOD_E, MOD_S. - - * t-trap.s: New file. - * Makefile.in (TESTS): Update. - -Thu Dec 4 16:56:55 1997 Andrew Cagney - - * t-macros.i: Add definitions for PSW bits. - - * t-mvtc.s: New file. - * Makefile.in (TESTS): Update. - -Wed Dec 3 16:35:24 1997 Andrew Cagney - - * t-rac.s: New files. - - * t-macros.i: Add macros for checking psw and 2w quantities. - - * Makefile.in (TESTS): Update. - -Tue Dec 2 11:01:36 1997 Andrew Cagney - - * t-sub2w.s, t-mulxu.s, t-mac.s, t-mvtac.s, t-msbu.s, t-sub.s: New - files. - - * Makefile.in: Update. - -Mon Nov 17 20:14:48 1997 Andrew Cagney - - * t-subi.s (test_subi): New file. - * Makefile.in: Update. - -Fri Nov 14 14:06:06 1997 Andrew Cagney - - * t-rep.s: New file. Test case of branch to RPT_E address. - -Mon Nov 10 19:21:26 1997 Andrew Cagney - - * t-macros.i (_start): New file. - * t-rachi.s: New file. - - * Makefile.in (RUN_FOR_TARGET): Look for simulator in d10v - directory. diff --git a/sim/testsuite/d10v/ChangeLog-2021 b/sim/testsuite/d10v/ChangeLog-2021 new file mode 100644 index 0000000..f50a384 --- /dev/null +++ b/sim/testsuite/d10v/ChangeLog-2021 @@ -0,0 +1,151 @@ +2021-04-08 Mike Frysinger + + * allinsn.exp (arch): Delete. + +2021-02-13 Mike Frysinger + + * allinsn.exp: Define arch. + +2021-01-15 Mike Frysinger + + * allinsn.exp: New file. + * configure, configure.ac, loop.s, Makefile.in: Deleted. + +2020-10-06 Andrew Burgess + + * configure: Regnerate. + * configure.ac (AC_CONFIG_AUX_DIR): Update. + +2015-03-30 Mike Frysinger + + * Makefile.in (RUNFLAGS_FOR_TARGET): Set to --environment operating. + +2009-08-22 Ralf Wildenhues + + * configure: Regenerate. + +2005-01-07 Andrew Cagney + + * configure.ac: Rename configure.in, require autoconf 2.59. + * configure: Re-generate. + +Tue Apr 18 16:32:07 2000 Andrew Cagney + + * t-rie-xx.s (test_rie_xx): New test. + * Makefile.in (TESTS): Update. + +Tue Feb 22 17:36:34 2000 Andrew Cagney + + * Makefile.in: Force d10v into operating mode. + +Mon Jan 3 00:17:28 2000 Andrew Cagney + + * t-ae-ld-d.s, t-ae-ld-i.s, t-ae-ld-id.s, t-ae-ld-im.s , + t-ae-ld-ip.s, t-ae-ld2w-d.s, t-ae-ld2w-i.s, t-ae-ld2w-id.s , + t-ae-ld2w-im.s, t-ae-ld2w-ip.s, t-ae-st-d.s, t-ae-st-i.s , + t-ae-st-id.s, t-ae-st-im.s, t-ae-st-ip.s, t-ae-st-is.s , + t-ae-st2w-d.s, t-ae-st2w-i.s, t-ae-st2w-id.s, t-ae-st2w-im.s , + t-ae-st2w-ip.s, t-ae-st2w-is.s: New tests. Check that an address + exception occures when a word/two-word load/store is not word + aligned. + * Makefile.in (TESTS): Update. + +Fri Oct 29 18:36:34 1999 Andrew Cagney + + * t-mvtc.s: Check that the user can not modify the DM bit in the + BPSW or DPSW. + +Thu Oct 28 01:47:26 1999 Andrew Cagney + + * t-mvtc.s: Update. Check that user can not modify DM bit. + +Wed Sep 8 19:34:55 MDT 1999 Diego Novillo + + * t-ld-st.s: New file. + * t-sac.s: New file. + * t-sachi.s: New file. + * t-slae.s: New file. + +1999-01-13 Jason Molenda (jsm@bugshack.cygnus.com) + + * t-sadd.s: New file. + * Makefile.in (TESTS): Add t-sadd. + +Mon Feb 16 09:20:57 1998 Andrew Cagney + + * t-macros.i (VEC_*): Define. + (DMAP_REG, DMAP_BASE, DMAP_MASK): Define. + (IMAP[01]_REG): Define. + + * t-rdt.s (test_tdt): New file. + + * t-dbt.s (test_dbt): New file. + + * Makefile.in (TESTS): Add t-rdt and t-dbt. + + +Fri Feb 13 16:21:13 1998 Andrew Cagney + + * t-sp.s: New test. + * Makefile.in (TESTS): Update. + +Wed Feb 11 17:58:50 1998 Andrew Cagney + + * t-macros.i: Update trap calls, func in r4, args in + r0... + (start): Force r0 to zero. + + * t-sub2w.s: Ditto. + +Tue Dec 9 10:41:44 1997 Andrew Cagney + + * t-rte.s (success): New file. + * Makefile.in: Update. + + * t-rep.s: Check rep repeats correct number of times. + +Fri Dec 5 10:11:18 1997 Andrew Cagney + + * t-mvtc.s: Check for stuck-zero in MOD_E, MOD_S. + + * t-trap.s: New file. + * Makefile.in (TESTS): Update. + +Thu Dec 4 16:56:55 1997 Andrew Cagney + + * t-macros.i: Add definitions for PSW bits. + + * t-mvtc.s: New file. + * Makefile.in (TESTS): Update. + +Wed Dec 3 16:35:24 1997 Andrew Cagney + + * t-rac.s: New files. + + * t-macros.i: Add macros for checking psw and 2w quantities. + + * Makefile.in (TESTS): Update. + +Tue Dec 2 11:01:36 1997 Andrew Cagney + + * t-sub2w.s, t-mulxu.s, t-mac.s, t-mvtac.s, t-msbu.s, t-sub.s: New + files. + + * Makefile.in: Update. + +Mon Nov 17 20:14:48 1997 Andrew Cagney + + * t-subi.s (test_subi): New file. + * Makefile.in: Update. + +Fri Nov 14 14:06:06 1997 Andrew Cagney + + * t-rep.s: New file. Test case of branch to RPT_E address. + +Mon Nov 10 19:21:26 1997 Andrew Cagney + + * t-macros.i (_start): New file. + * t-rachi.s: New file. + + * Makefile.in (RUN_FOR_TARGET): Look for simulator in d10v + directory. diff --git a/sim/testsuite/example-synacor/ChangeLog b/sim/testsuite/example-synacor/ChangeLog deleted file mode 100644 index bb9b0b4..0000000 --- a/sim/testsuite/example-synacor/ChangeLog +++ /dev/null @@ -1,9 +0,0 @@ -2021-04-08 Mike Frysinger - - * allinsn.exp (arch): Delete. - -2021-04-03 Mike Frysinger - - * add.s, allinsn.exp, and.s, call.s, exit-0.s, gt.s, isa.inc, jmp.s, - mem.s, mod.s, mult.s, not.s, or.s, push-pop.s, ret.s, set.s, - testutils.inc: New files. diff --git a/sim/testsuite/example-synacor/ChangeLog-2021 b/sim/testsuite/example-synacor/ChangeLog-2021 new file mode 100644 index 0000000..bb9b0b4 --- /dev/null +++ b/sim/testsuite/example-synacor/ChangeLog-2021 @@ -0,0 +1,9 @@ +2021-04-08 Mike Frysinger + + * allinsn.exp (arch): Delete. + +2021-04-03 Mike Frysinger + + * add.s, allinsn.exp, and.s, call.s, exit-0.s, gt.s, isa.inc, jmp.s, + mem.s, mod.s, mult.s, not.s, or.s, push-pop.s, ret.s, set.s, + testutils.inc: New files. diff --git a/sim/testsuite/frv/ChangeLog b/sim/testsuite/frv/ChangeLog deleted file mode 100644 index aa7409f..0000000 --- a/sim/testsuite/frv/ChangeLog +++ /dev/null @@ -1,94 +0,0 @@ -2021-04-08 Mike Frysinger - - * allinsn.exp (arch): Delete. - * fr400/allinsn.exp, fr500/allinsn.exp, fr550/allinsn.exp, - interrupts.exp, misc.exp, parallel.exp: Likewise. - -2021-02-13 Mike Frysinger - - * allinsn.exp, fr400/allinsn.exp, fr500/allinsn.exp, - fr550/allinsn.exp, interrupts.exp, misc.exp, - parallel.exp: Define arch. - -2021-01-15 Mike Frysinger - - * cache.ms: New testcase from ../../frv-elf/. - * exit47.ms, grloop.ms, hello.ms: Likewise. - * misc.exp: New file. - -2004-03-01 Richard Sandiford - - * allinsn.exp (all_machs): Add fr405 and fr450. - * fr400/allinsn.exp (all_machs): Likewise. - * fr400/addss.cgs (mach): Change to "fr405 fr450". - * fr400/scutss.cgs (mach): Likewise. - * fr400/slass.cgs (mach): Likewise. - * fr400/smass.cgs (mach): Likewise. - * fr400/smsss.cgs (mach): Likewise. - * fr400/smu.cgs (mach): Likewise. - * fr400/subss.cgs (mach): Likewise. - * interrupts/fp_exception.cgs: Replace fmadds with .word. - * interrupts/fp_exception-fr550.cgs: Likewise. - * mqlclrhs.cgs: New test. - * mqlmths.cgs: New test. - * mqsllhi.cgs: New test. - * mqsrahi.cgs: New test. - -2004-03-01 Richard Sandiford - - * fr400/scutss.cgs: Fix tests to account for rounding. - Add some new ones. - -2004-03-01 Richard Sandiford - - * {rstb,rsth,rst,rstd,rstq}.cgs: Delete. - * {rstbf,rsthf,rstf,rstdf,rstqf}.cgs: Delete. - -2003-10-10 Dave Brolley - - * testutils.inc (or_gr_immed): New macro. - * fp_exception-fr550.cgs: Write insns using - unaligned registers into the program in order to - cause the required exceptions. - * fp_exception.cgs: Ditto. - * regalign.cgs: Ditto. - -2003-10-06 Dave Brolley - - * fr550: New subdirectory. - * fr400/*.cgs: Add fr550 as appropriate. - * fr500/*.cgs: Add fr550 as appropriate. - * interrupts/*.cgs: Add fr550 as appropriate. - * interrupts/*-fr550.cgs: New test cases for fr550. - -2003-09-19 Michael Snyder - - * nldqi.cgs: Remove. This insn was never implemented - by Fujitsu. - -2003-09-19 Dave Brolley - - * rstqf.cgs: Use nldq instead of nldqi. - * rstq.cgs: Use nldq instead of nldqi. - -2003-09-11 Michael Snyder - - * movgs.cgs: Change lcr to spr[273], - which according to the comments seems to be the intent. - -2003-09-09 Dave Brolley - - * maddaccs.cgs: move to fr400 subdirectory. - * msubaccs.cgs: move to fr400 subdirectory. - * masaccs.cgs: move to fr400 subdirectory. - -2003-09-03 Michael Snyder - - * fr500/mclracc.cgs: Change mach to 'all', to be - consistent with other tests in the directory. - -2003-09-03 Michael Snyder - - * interrupts/Ipipe-fr400.cgs: New file. - * interrupts/Ipipe-fr500.cgs: New file. - * interrupts/Ipipe.cgs: Remove (replaced by above). diff --git a/sim/testsuite/frv/ChangeLog-2021 b/sim/testsuite/frv/ChangeLog-2021 new file mode 100644 index 0000000..aa7409f --- /dev/null +++ b/sim/testsuite/frv/ChangeLog-2021 @@ -0,0 +1,94 @@ +2021-04-08 Mike Frysinger + + * allinsn.exp (arch): Delete. + * fr400/allinsn.exp, fr500/allinsn.exp, fr550/allinsn.exp, + interrupts.exp, misc.exp, parallel.exp: Likewise. + +2021-02-13 Mike Frysinger + + * allinsn.exp, fr400/allinsn.exp, fr500/allinsn.exp, + fr550/allinsn.exp, interrupts.exp, misc.exp, + parallel.exp: Define arch. + +2021-01-15 Mike Frysinger + + * cache.ms: New testcase from ../../frv-elf/. + * exit47.ms, grloop.ms, hello.ms: Likewise. + * misc.exp: New file. + +2004-03-01 Richard Sandiford + + * allinsn.exp (all_machs): Add fr405 and fr450. + * fr400/allinsn.exp (all_machs): Likewise. + * fr400/addss.cgs (mach): Change to "fr405 fr450". + * fr400/scutss.cgs (mach): Likewise. + * fr400/slass.cgs (mach): Likewise. + * fr400/smass.cgs (mach): Likewise. + * fr400/smsss.cgs (mach): Likewise. + * fr400/smu.cgs (mach): Likewise. + * fr400/subss.cgs (mach): Likewise. + * interrupts/fp_exception.cgs: Replace fmadds with .word. + * interrupts/fp_exception-fr550.cgs: Likewise. + * mqlclrhs.cgs: New test. + * mqlmths.cgs: New test. + * mqsllhi.cgs: New test. + * mqsrahi.cgs: New test. + +2004-03-01 Richard Sandiford + + * fr400/scutss.cgs: Fix tests to account for rounding. + Add some new ones. + +2004-03-01 Richard Sandiford + + * {rstb,rsth,rst,rstd,rstq}.cgs: Delete. + * {rstbf,rsthf,rstf,rstdf,rstqf}.cgs: Delete. + +2003-10-10 Dave Brolley + + * testutils.inc (or_gr_immed): New macro. + * fp_exception-fr550.cgs: Write insns using + unaligned registers into the program in order to + cause the required exceptions. + * fp_exception.cgs: Ditto. + * regalign.cgs: Ditto. + +2003-10-06 Dave Brolley + + * fr550: New subdirectory. + * fr400/*.cgs: Add fr550 as appropriate. + * fr500/*.cgs: Add fr550 as appropriate. + * interrupts/*.cgs: Add fr550 as appropriate. + * interrupts/*-fr550.cgs: New test cases for fr550. + +2003-09-19 Michael Snyder + + * nldqi.cgs: Remove. This insn was never implemented + by Fujitsu. + +2003-09-19 Dave Brolley + + * rstqf.cgs: Use nldq instead of nldqi. + * rstq.cgs: Use nldq instead of nldqi. + +2003-09-11 Michael Snyder + + * movgs.cgs: Change lcr to spr[273], + which according to the comments seems to be the intent. + +2003-09-09 Dave Brolley + + * maddaccs.cgs: move to fr400 subdirectory. + * msubaccs.cgs: move to fr400 subdirectory. + * masaccs.cgs: move to fr400 subdirectory. + +2003-09-03 Michael Snyder + + * fr500/mclracc.cgs: Change mach to 'all', to be + consistent with other tests in the directory. + +2003-09-03 Michael Snyder + + * interrupts/Ipipe-fr400.cgs: New file. + * interrupts/Ipipe-fr500.cgs: New file. + * interrupts/Ipipe.cgs: Remove (replaced by above). diff --git a/sim/testsuite/ft32/ChangeLog b/sim/testsuite/ft32/ChangeLog deleted file mode 100644 index 346ac74..0000000 --- a/sim/testsuite/ft32/ChangeLog +++ /dev/null @@ -1,16 +0,0 @@ -2021-04-08 Mike Frysinger - - * allinsn.exp (arch): Delete. - -2021-02-13 Mike Frysinger - - * allinsn.exp: Define arch. - -2015-10-12 James Bowman - - * basic.s: Add test for memory size link parameters. - Add test for program memory write port. - -2015-02-28 James Bowman - - * basic.s, allinsn.exp, testutils.inc: New files. diff --git a/sim/testsuite/ft32/ChangeLog-2021 b/sim/testsuite/ft32/ChangeLog-2021 new file mode 100644 index 0000000..346ac74 --- /dev/null +++ b/sim/testsuite/ft32/ChangeLog-2021 @@ -0,0 +1,16 @@ +2021-04-08 Mike Frysinger + + * allinsn.exp (arch): Delete. + +2021-02-13 Mike Frysinger + + * allinsn.exp: Define arch. + +2015-10-12 James Bowman + + * basic.s: Add test for memory size link parameters. + Add test for program memory write port. + +2015-02-28 James Bowman + + * basic.s, allinsn.exp, testutils.inc: New files. diff --git a/sim/testsuite/h8300/ChangeLog b/sim/testsuite/h8300/ChangeLog deleted file mode 100644 index 828b136..0000000 --- a/sim/testsuite/h8300/ChangeLog +++ /dev/null @@ -1,134 +0,0 @@ -2021-05-28 Yoshinori Sato - - * addb.s: Add special case reg,<@reg+ / @reg- / @+reg / @-reg>. - * andb.s: Likewise. - * cmpb.s: Likewise. - * orb.s: Likewise. - * subb.s: Likewise. - * xorb.s: Likewise. - * movb.s: Add special case reg,<@reg+ / @reg- / @+reg / @-reg> - @reg+,@reg+ / @-reg,@-reg. - @ movw.s: Likewise. - @ movl.s: Likewise. - -2021-05-04 Yoshinori Sato - - * movb.s: Add special case predec test. - * movw.s: Likewise. - * movl.s: Likewise. - -2021-04-08 Mike Frysinger - - * allinsn.exp (arch): Delete. - -2021-02-13 Mike Frysinger - - * allinsn.exp: Define arch. - -2021-01-05 Mike Frysinger - - * rotl.s (mach): Set to "h8300s h8sx". - * rotr.s, rotxl.s, rotxr.s, shal.s, shar.s, shll.s, shlr.s, tas.s: - Likewise. - -2021-01-05 Mike Frysinger - - * allinsn.exp: Rewrite file to use globs. - -2004-06-28 Alexandre Oliva - - 2003-07-22 Michael Snyder - * mul.s: Don't try to use negative immediate (it's always - unsigned). - * div.s: Ditto. - -2004-06-24 Alexandre Oliva - - 2004-06-17 Alexandre Oliva - * band.s, biand.s: imm3_abs16 is not available on h8300h. - * bset.s: Likewise. Ditto for rn_abs32. - -2003-07-22 Michael Snyder - - * cmpw.s: Add test for less-than-zero immediate. - * shll.s: Test for shll reg, reg. - * shlr.s: Test for shlr reg, reg. - * mova.s: Add dozens of new mova tests. - -2003-05-30 Alexandre Oliva - - * allinsn.exp: Fix typos introduced on 2003-05-27. - -2003-05-29 Michael Snyder - - * tas.s: Use er4 for h8h and h8s, er3 for h8sx. - -2003-05-28 Michael Snyder - - * subs.s: New file. - * subx.s: New file. - * allinsn.exp: Add new subs and subx tests. - * testutils.inc: Simplify (and fix) set_carry_flag. - (clear_carry_flag, set_zero_flag, clear_zero_flag...): New macros. - * addx.s: Use simplified set_carry_flag. - -2003-05-27 Michael Snyder - - * tas.s: New file. - * band.s: New file. - * biand.s: New file. - * allinsn.exp: Add tas, band, biand tests. - * brabc.s: Add abs8 test. - * bset.s: Add bset/ne, bclr/ne tests. - -2003-05-23 Michael Snyder - - * and.b.s: Add andc exr. - * or.b.s: Add orc.exr. - * xor.b.s: Add xor exr. - - * jmp.s: Fix 8-bit indirect test. Add 7-bit vector test. - -2003-05-22 Michael Snyder - - * stack.s: Add rte/l and rts/l tests. - * allinsn.exp: Add stack tests. - -2003-05-21 Michael Snyder - - * stack.s: New file: test stack operations. - * stack.s: Add bsr, jsr tests. - * stack.s: Add trapa, rte tests. - - * div.s: Corrections for size of dividend. - -2003-05-20 Michael Snyder - - * mul.s: Corrections for unsigned multiply. - - * div.s: New file, test div instructions. - * allinsn.exp: Add div test. - -2003-05-19 Michael Snyder - - * mul.s: New file, test mul instructions. - * allinsn.exp: Add mul test. - -2003-05-14 Michael Snyder - - * addb.s, addw.s, addl.s, addw.s, addx.s, andb.s, andw.s, andl.s, - bfld.s, brabc.s, bra.s, bset.s, cmpb.s, cmpw.s, cmpl.s, daa.s, - das.s, dec.s, extw.s, extl.s, inc.s, jmp.s, ldc.s, ldm.s, mac.s, - mova.s, movb.s, movw.s, movl.s, movmd.s, movsd.s, neg.s, nop.s, - not.s, orb.s, orw.s, orl.s, rotl.s, rotr.s, rotxl.s, rotxr.s, - shal.s, shar.s, shll.s, shlr.s, stc.s, subb.s, subw.s, subl.s, - xorb.s, xorw.s, xorl.s: New files. - * allinsn.exp: New file. - -Local Variables: -mode: change-log -left-margin: 8 -fill-column: 74 -version-control: never -change-log-default-name: "ChangeLog" -End: diff --git a/sim/testsuite/h8300/ChangeLog-2021 b/sim/testsuite/h8300/ChangeLog-2021 new file mode 100644 index 0000000..828b136 --- /dev/null +++ b/sim/testsuite/h8300/ChangeLog-2021 @@ -0,0 +1,134 @@ +2021-05-28 Yoshinori Sato + + * addb.s: Add special case reg,<@reg+ / @reg- / @+reg / @-reg>. + * andb.s: Likewise. + * cmpb.s: Likewise. + * orb.s: Likewise. + * subb.s: Likewise. + * xorb.s: Likewise. + * movb.s: Add special case reg,<@reg+ / @reg- / @+reg / @-reg> + @reg+,@reg+ / @-reg,@-reg. + @ movw.s: Likewise. + @ movl.s: Likewise. + +2021-05-04 Yoshinori Sato + + * movb.s: Add special case predec test. + * movw.s: Likewise. + * movl.s: Likewise. + +2021-04-08 Mike Frysinger + + * allinsn.exp (arch): Delete. + +2021-02-13 Mike Frysinger + + * allinsn.exp: Define arch. + +2021-01-05 Mike Frysinger + + * rotl.s (mach): Set to "h8300s h8sx". + * rotr.s, rotxl.s, rotxr.s, shal.s, shar.s, shll.s, shlr.s, tas.s: + Likewise. + +2021-01-05 Mike Frysinger + + * allinsn.exp: Rewrite file to use globs. + +2004-06-28 Alexandre Oliva + + 2003-07-22 Michael Snyder + * mul.s: Don't try to use negative immediate (it's always + unsigned). + * div.s: Ditto. + +2004-06-24 Alexandre Oliva + + 2004-06-17 Alexandre Oliva + * band.s, biand.s: imm3_abs16 is not available on h8300h. + * bset.s: Likewise. Ditto for rn_abs32. + +2003-07-22 Michael Snyder + + * cmpw.s: Add test for less-than-zero immediate. + * shll.s: Test for shll reg, reg. + * shlr.s: Test for shlr reg, reg. + * mova.s: Add dozens of new mova tests. + +2003-05-30 Alexandre Oliva + + * allinsn.exp: Fix typos introduced on 2003-05-27. + +2003-05-29 Michael Snyder + + * tas.s: Use er4 for h8h and h8s, er3 for h8sx. + +2003-05-28 Michael Snyder + + * subs.s: New file. + * subx.s: New file. + * allinsn.exp: Add new subs and subx tests. + * testutils.inc: Simplify (and fix) set_carry_flag. + (clear_carry_flag, set_zero_flag, clear_zero_flag...): New macros. + * addx.s: Use simplified set_carry_flag. + +2003-05-27 Michael Snyder + + * tas.s: New file. + * band.s: New file. + * biand.s: New file. + * allinsn.exp: Add tas, band, biand tests. + * brabc.s: Add abs8 test. + * bset.s: Add bset/ne, bclr/ne tests. + +2003-05-23 Michael Snyder + + * and.b.s: Add andc exr. + * or.b.s: Add orc.exr. + * xor.b.s: Add xor exr. + + * jmp.s: Fix 8-bit indirect test. Add 7-bit vector test. + +2003-05-22 Michael Snyder + + * stack.s: Add rte/l and rts/l tests. + * allinsn.exp: Add stack tests. + +2003-05-21 Michael Snyder + + * stack.s: New file: test stack operations. + * stack.s: Add bsr, jsr tests. + * stack.s: Add trapa, rte tests. + + * div.s: Corrections for size of dividend. + +2003-05-20 Michael Snyder + + * mul.s: Corrections for unsigned multiply. + + * div.s: New file, test div instructions. + * allinsn.exp: Add div test. + +2003-05-19 Michael Snyder + + * mul.s: New file, test mul instructions. + * allinsn.exp: Add mul test. + +2003-05-14 Michael Snyder + + * addb.s, addw.s, addl.s, addw.s, addx.s, andb.s, andw.s, andl.s, + bfld.s, brabc.s, bra.s, bset.s, cmpb.s, cmpw.s, cmpl.s, daa.s, + das.s, dec.s, extw.s, extl.s, inc.s, jmp.s, ldc.s, ldm.s, mac.s, + mova.s, movb.s, movw.s, movl.s, movmd.s, movsd.s, neg.s, nop.s, + not.s, orb.s, orw.s, orl.s, rotl.s, rotr.s, rotxl.s, rotxr.s, + shal.s, shar.s, shll.s, shlr.s, stc.s, subb.s, subw.s, subl.s, + xorb.s, xorw.s, xorl.s: New files. + * allinsn.exp: New file. + +Local Variables: +mode: change-log +left-margin: 8 +fill-column: 74 +version-control: never +change-log-default-name: "ChangeLog" +End: diff --git a/sim/testsuite/iq2000/ChangeLog b/sim/testsuite/iq2000/ChangeLog deleted file mode 100644 index 4c94a66..0000000 --- a/sim/testsuite/iq2000/ChangeLog +++ /dev/null @@ -1,11 +0,0 @@ -2021-04-08 Mike Frysinger - - * allinsn.exp (arch): Delete. - -2021-02-13 Mike Frysinger - - * allinsn.exp: Define arch. - -2015-04-05 Mike Frysinger - - * pass.s, allinsn.exp, testutils.inc: New files. diff --git a/sim/testsuite/iq2000/ChangeLog-2021 b/sim/testsuite/iq2000/ChangeLog-2021 new file mode 100644 index 0000000..4c94a66 --- /dev/null +++ b/sim/testsuite/iq2000/ChangeLog-2021 @@ -0,0 +1,11 @@ +2021-04-08 Mike Frysinger + + * allinsn.exp (arch): Delete. + +2021-02-13 Mike Frysinger + + * allinsn.exp: Define arch. + +2015-04-05 Mike Frysinger + + * pass.s, allinsn.exp, testutils.inc: New files. diff --git a/sim/testsuite/lm32/ChangeLog b/sim/testsuite/lm32/ChangeLog deleted file mode 100644 index 4c94a66..0000000 --- a/sim/testsuite/lm32/ChangeLog +++ /dev/null @@ -1,11 +0,0 @@ -2021-04-08 Mike Frysinger - - * allinsn.exp (arch): Delete. - -2021-02-13 Mike Frysinger - - * allinsn.exp: Define arch. - -2015-04-05 Mike Frysinger - - * pass.s, allinsn.exp, testutils.inc: New files. diff --git a/sim/testsuite/lm32/ChangeLog-2021 b/sim/testsuite/lm32/ChangeLog-2021 new file mode 100644 index 0000000..4c94a66 --- /dev/null +++ b/sim/testsuite/lm32/ChangeLog-2021 @@ -0,0 +1,11 @@ +2021-04-08 Mike Frysinger + + * allinsn.exp (arch): Delete. + +2021-02-13 Mike Frysinger + + * allinsn.exp: Define arch. + +2015-04-05 Mike Frysinger + + * pass.s, allinsn.exp, testutils.inc: New files. diff --git a/sim/testsuite/m32c/ChangeLog b/sim/testsuite/m32c/ChangeLog deleted file mode 100644 index 8172521..0000000 --- a/sim/testsuite/m32c/ChangeLog +++ /dev/null @@ -1,18 +0,0 @@ -2021-04-08 Mike Frysinger - - * allinsn.exp (arch): Delete. - -2021-02-13 Mike Frysinger - - * allinsn.exp: Define arch. - -2015-11-14 Mike Frysinger - - * allinsn.exp: New file. - * fail.s, pass.s: New tests. - * testutils.inc: New test helper logic. - -2015-11-09 Mike Frysinger - - * blinky.s: Moved from ../../../m32c/. - * gloss.s, sample.ld, sample.s, sample2.c: Likewise. diff --git a/sim/testsuite/m32c/ChangeLog-2021 b/sim/testsuite/m32c/ChangeLog-2021 new file mode 100644 index 0000000..8172521 --- /dev/null +++ b/sim/testsuite/m32c/ChangeLog-2021 @@ -0,0 +1,18 @@ +2021-04-08 Mike Frysinger + + * allinsn.exp (arch): Delete. + +2021-02-13 Mike Frysinger + + * allinsn.exp: Define arch. + +2015-11-14 Mike Frysinger + + * allinsn.exp: New file. + * fail.s, pass.s: New tests. + * testutils.inc: New test helper logic. + +2015-11-09 Mike Frysinger + + * blinky.s: Moved from ../../../m32c/. + * gloss.s, sample.ld, sample.s, sample2.c: Likewise. diff --git a/sim/testsuite/m32r/ChangeLog b/sim/testsuite/m32r/ChangeLog deleted file mode 100644 index 535435a..0000000 --- a/sim/testsuite/m32r/ChangeLog +++ /dev/null @@ -1,140 +0,0 @@ -2021-07-01 Mike Frysinger - - * hw-trap.ms: Run sim with --environment virtual. - * trap.cgs: Likewise. - -2021-04-08 Mike Frysinger - - * allinsn.exp (arch): Delete. - * misc.exp: Likewise. - -2021-02-13 Mike Frysinger - - * allinsn.exp, misc.exp: Define arch. - -2021-01-15 Mike Frysinger - - * exit47.ms: New testcase from ../../m32r-elf/. - -1999-04-21 Doug Evans - - * nop.cgs: Add missing nop insn. - -1999-01-05 Doug Evans - - * allinsn.exp: Set all_machs. - * misc.exp: Likewise. - -1998-12-14 Doug Evans - - * hello.ms: Add trailing \n to expected output. - * hw-trap.ms: Ditto. - - * trap.cgs: Properly align trap2_handler. - - * uread16.ms: New testcase. - * uread32.ms: New testcase. - * uwrite16.ms: New testcase. - * uwrite32.ms: New testcase. - -Tue Sep 15 14:56:22 1998 Doug Evans - - * testutils.inc (test_h_gr): Use mvaddr_h_gr. - * rte.cgs: Test bbpc,bbpsw. - * trap.cgs: Test bbpc,bbpsw. - -Wed Jul 1 15:57:54 1998 Doug Evans - - * hw-trap.ms: New testcase. - -Wed Jun 10 10:53:20 1998 Doug Evans - - * addx.cgs: Add another test. - * jmp.cgs: Add another test. - -Mon Jun 8 16:08:27 1998 Doug Evans - - * trap.cgs: Test trap 2. - -Tue Apr 21 10:49:03 1998 Doug Evans - - * addx.cgs: Test (-1)+(-1)+1. - -Fri Apr 17 16:00:52 1998 Doug Evans - - * mv[ft]achi.cgs: Fix expected result - (sign extension of top 8 bits). - -Fri Feb 20 11:00:02 1998 Nick Clifton - - * unlock.cgs: Fixed test. - * mvfc.cgs: Fixed test. - * remu.cgs: Fixed test. - * bnc24.cgs: Test long BNC instruction. - * bnc8.cgs: Test short BNC instruction. - * ld-plus.cgs: Test LD instruction. - * macwhi.cgs: Test MACWHI instruction. - * macwlo.cgs: Test MACWLO instruction. - * mulwhi.cgs: Test MULWHI instruction. - * mulwlo.cgs: Test MULWLO instruction. - * mvfachi.cgs: Test MVFACHI instruction. - * mvfaclo.cgs: Test MVFACLO instruction. - * mvtaclo.cgs: Test MVTACLO instruction. - * addv.cgs: Test ADDV instruction. - * addv3.cgs: Test ADDV3 instruction. - * addx.cgs: Test ADDX instruction. - * lock.cgs: Test LOCK instruction. - * neg.cgs: Test NEG instruction. - * not.cgs: Test NOT instruction. - * unlock.cgs: Test UNLOCK instruction. - -Thu Feb 19 11:15:45 1998 Nick Clifton - - * testutils.inc (mvaddr_h_gr): new macro to load an - address into a general register. - - * or3.cgs: Test OR3 instruction. - * rach.cgs: Test RACH instruction. - * rem.cgs: Test REM instruction. - * sub.cgs: Test SUB instruction. - * mv.cgs: Test MV instruction. - * mul.cgs: Test MUL instruction. - * bl24.cgs: Test long BL instruction. - * bl8.cgs: Test short BL instruction. - * blez.cgs: Test BLEZ instruction. - * bltz.cgs: Test BLTZ instruction. - * bne.cgs: Test BNE instruction. - * bnez.cgs: Test BNEZ instruction. - * bra24.cgs: Test long BRA instruction. - * bra8.cgs: Test short BRA instruction. - * jl.cgs: Test JL instruction. - * or.cgs: Test OR instruction. - * jmp.cgs: Test JMP instruction. - * and.cgs: Test AND instruction. - * and3.cgs: Test AND3 instruction. - * beq.cgs: Test BEQ instruction. - * beqz.cgs: Test BEQZ instruction. - * bgez.cgs: Test BGEZ instruction. - * bgtz.cgs: Test BGTZ instruction. - * cmp.cgs: Test CMP instruction. - * cmpi.cgs: Test CMPI instruction. - * cmpu.cgs: Test CMPU instruction. - * cmpui.cgs: Test CMPUI instruction. - * div.cgs: Test DIV instruction. - * divu.cgs: Test DIVU instruction. - * cmpeq.cgs: Test CMPEQ instruction. - * sll.cgs: Test SLL instruction. - * sll3.cgs: Test SLL3 instruction. - * slli.cgs: Test SLLI instruction. - * sra.cgs: Test SRA instruction. - * sra3.cgs: Test SRA3 instruction. - * srai.cgs: Test SRAI instruction. - * srl.cgs: Test SRL instruction. - * srl3.cgs: Test SRL3 instruction. - * srli.cgs: Test SRLI instruction. - * xor3.cgs: Test XOR3 instruction. - * xor.cgs: Test XOR instruction. - -Tue Feb 17 12:46:05 1998 Doug Evans - - * *: m32r dejagnu simulator testsuite. diff --git a/sim/testsuite/m32r/ChangeLog-2021 b/sim/testsuite/m32r/ChangeLog-2021 new file mode 100644 index 0000000..535435a --- /dev/null +++ b/sim/testsuite/m32r/ChangeLog-2021 @@ -0,0 +1,140 @@ +2021-07-01 Mike Frysinger + + * hw-trap.ms: Run sim with --environment virtual. + * trap.cgs: Likewise. + +2021-04-08 Mike Frysinger + + * allinsn.exp (arch): Delete. + * misc.exp: Likewise. + +2021-02-13 Mike Frysinger + + * allinsn.exp, misc.exp: Define arch. + +2021-01-15 Mike Frysinger + + * exit47.ms: New testcase from ../../m32r-elf/. + +1999-04-21 Doug Evans + + * nop.cgs: Add missing nop insn. + +1999-01-05 Doug Evans + + * allinsn.exp: Set all_machs. + * misc.exp: Likewise. + +1998-12-14 Doug Evans + + * hello.ms: Add trailing \n to expected output. + * hw-trap.ms: Ditto. + + * trap.cgs: Properly align trap2_handler. + + * uread16.ms: New testcase. + * uread32.ms: New testcase. + * uwrite16.ms: New testcase. + * uwrite32.ms: New testcase. + +Tue Sep 15 14:56:22 1998 Doug Evans + + * testutils.inc (test_h_gr): Use mvaddr_h_gr. + * rte.cgs: Test bbpc,bbpsw. + * trap.cgs: Test bbpc,bbpsw. + +Wed Jul 1 15:57:54 1998 Doug Evans + + * hw-trap.ms: New testcase. + +Wed Jun 10 10:53:20 1998 Doug Evans + + * addx.cgs: Add another test. + * jmp.cgs: Add another test. + +Mon Jun 8 16:08:27 1998 Doug Evans + + * trap.cgs: Test trap 2. + +Tue Apr 21 10:49:03 1998 Doug Evans + + * addx.cgs: Test (-1)+(-1)+1. + +Fri Apr 17 16:00:52 1998 Doug Evans + + * mv[ft]achi.cgs: Fix expected result + (sign extension of top 8 bits). + +Fri Feb 20 11:00:02 1998 Nick Clifton + + * unlock.cgs: Fixed test. + * mvfc.cgs: Fixed test. + * remu.cgs: Fixed test. + * bnc24.cgs: Test long BNC instruction. + * bnc8.cgs: Test short BNC instruction. + * ld-plus.cgs: Test LD instruction. + * macwhi.cgs: Test MACWHI instruction. + * macwlo.cgs: Test MACWLO instruction. + * mulwhi.cgs: Test MULWHI instruction. + * mulwlo.cgs: Test MULWLO instruction. + * mvfachi.cgs: Test MVFACHI instruction. + * mvfaclo.cgs: Test MVFACLO instruction. + * mvtaclo.cgs: Test MVTACLO instruction. + * addv.cgs: Test ADDV instruction. + * addv3.cgs: Test ADDV3 instruction. + * addx.cgs: Test ADDX instruction. + * lock.cgs: Test LOCK instruction. + * neg.cgs: Test NEG instruction. + * not.cgs: Test NOT instruction. + * unlock.cgs: Test UNLOCK instruction. + +Thu Feb 19 11:15:45 1998 Nick Clifton + + * testutils.inc (mvaddr_h_gr): new macro to load an + address into a general register. + + * or3.cgs: Test OR3 instruction. + * rach.cgs: Test RACH instruction. + * rem.cgs: Test REM instruction. + * sub.cgs: Test SUB instruction. + * mv.cgs: Test MV instruction. + * mul.cgs: Test MUL instruction. + * bl24.cgs: Test long BL instruction. + * bl8.cgs: Test short BL instruction. + * blez.cgs: Test BLEZ instruction. + * bltz.cgs: Test BLTZ instruction. + * bne.cgs: Test BNE instruction. + * bnez.cgs: Test BNEZ instruction. + * bra24.cgs: Test long BRA instruction. + * bra8.cgs: Test short BRA instruction. + * jl.cgs: Test JL instruction. + * or.cgs: Test OR instruction. + * jmp.cgs: Test JMP instruction. + * and.cgs: Test AND instruction. + * and3.cgs: Test AND3 instruction. + * beq.cgs: Test BEQ instruction. + * beqz.cgs: Test BEQZ instruction. + * bgez.cgs: Test BGEZ instruction. + * bgtz.cgs: Test BGTZ instruction. + * cmp.cgs: Test CMP instruction. + * cmpi.cgs: Test CMPI instruction. + * cmpu.cgs: Test CMPU instruction. + * cmpui.cgs: Test CMPUI instruction. + * div.cgs: Test DIV instruction. + * divu.cgs: Test DIVU instruction. + * cmpeq.cgs: Test CMPEQ instruction. + * sll.cgs: Test SLL instruction. + * sll3.cgs: Test SLL3 instruction. + * slli.cgs: Test SLLI instruction. + * sra.cgs: Test SRA instruction. + * sra3.cgs: Test SRA3 instruction. + * srai.cgs: Test SRAI instruction. + * srl.cgs: Test SRL instruction. + * srl3.cgs: Test SRL3 instruction. + * srli.cgs: Test SRLI instruction. + * xor3.cgs: Test XOR3 instruction. + * xor.cgs: Test XOR instruction. + +Tue Feb 17 12:46:05 1998 Doug Evans + + * *: m32r dejagnu simulator testsuite. diff --git a/sim/testsuite/m68hc11/ChangeLog b/sim/testsuite/m68hc11/ChangeLog deleted file mode 100644 index 4c94a66..0000000 --- a/sim/testsuite/m68hc11/ChangeLog +++ /dev/null @@ -1,11 +0,0 @@ -2021-04-08 Mike Frysinger - - * allinsn.exp (arch): Delete. - -2021-02-13 Mike Frysinger - - * allinsn.exp: Define arch. - -2015-04-05 Mike Frysinger - - * pass.s, allinsn.exp, testutils.inc: New files. diff --git a/sim/testsuite/m68hc11/ChangeLog-2021 b/sim/testsuite/m68hc11/ChangeLog-2021 new file mode 100644 index 0000000..4c94a66 --- /dev/null +++ b/sim/testsuite/m68hc11/ChangeLog-2021 @@ -0,0 +1,11 @@ +2021-04-08 Mike Frysinger + + * allinsn.exp (arch): Delete. + +2021-02-13 Mike Frysinger + + * allinsn.exp: Define arch. + +2015-04-05 Mike Frysinger + + * pass.s, allinsn.exp, testutils.inc: New files. diff --git a/sim/testsuite/mcore/ChangeLog b/sim/testsuite/mcore/ChangeLog deleted file mode 100644 index 78f0769..0000000 --- a/sim/testsuite/mcore/ChangeLog +++ /dev/null @@ -1,16 +0,0 @@ -2021-04-08 Mike Frysinger - - * allinsn.exp (arch): Delete. - -2021-02-13 Mike Frysinger - - * allinsn.exp: Define arch. - -2015-11-15 Mike Frysinger - - * fail.s: New test. - * testutils.inc (fail): Fix exit code. - -2015-03-29 Mike Frysinger - - * pass.s, allinsn.exp, testutils.inc: New files. diff --git a/sim/testsuite/mcore/ChangeLog-2021 b/sim/testsuite/mcore/ChangeLog-2021 new file mode 100644 index 0000000..78f0769 --- /dev/null +++ b/sim/testsuite/mcore/ChangeLog-2021 @@ -0,0 +1,16 @@ +2021-04-08 Mike Frysinger + + * allinsn.exp (arch): Delete. + +2021-02-13 Mike Frysinger + + * allinsn.exp: Define arch. + +2015-11-15 Mike Frysinger + + * fail.s: New test. + * testutils.inc (fail): Fix exit code. + +2015-03-29 Mike Frysinger + + * pass.s, allinsn.exp, testutils.inc: New files. diff --git a/sim/testsuite/microblaze/ChangeLog b/sim/testsuite/microblaze/ChangeLog deleted file mode 100644 index 205646e..0000000 --- a/sim/testsuite/microblaze/ChangeLog +++ /dev/null @@ -1,19 +0,0 @@ -2021-05-04 Mike Frysinger - - * pass.s: Delete output line. - * testutils.inc (system_call, write): New macros. - (exit): Mark nr required. - (pass, fail): Call write - * fail.s: New test. - -2021-04-08 Mike Frysinger - - * allinsn.exp (arch): Delete. - -2021-02-13 Mike Frysinger - - * allinsn.exp: Define arch. - -2015-03-29 Mike Frysinger - - * pass.s, allinsn.exp, testutils.inc: New files. diff --git a/sim/testsuite/microblaze/ChangeLog-2021 b/sim/testsuite/microblaze/ChangeLog-2021 new file mode 100644 index 0000000..205646e --- /dev/null +++ b/sim/testsuite/microblaze/ChangeLog-2021 @@ -0,0 +1,19 @@ +2021-05-04 Mike Frysinger + + * pass.s: Delete output line. + * testutils.inc (system_call, write): New macros. + (exit): Mark nr required. + (pass, fail): Call write + * fail.s: New test. + +2021-04-08 Mike Frysinger + + * allinsn.exp (arch): Delete. + +2021-02-13 Mike Frysinger + + * allinsn.exp: Define arch. + +2015-03-29 Mike Frysinger + + * pass.s, allinsn.exp, testutils.inc: New files. diff --git a/sim/testsuite/mips/ChangeLog b/sim/testsuite/mips/ChangeLog deleted file mode 100644 index b64f691..0000000 --- a/sim/testsuite/mips/ChangeLog +++ /dev/null @@ -1,126 +0,0 @@ -2021-04-08 Mike Frysinger - - * basic.exp (arch): Delete. - -2021-02-13 Mike Frysinger - - * basic.exp: Define arch. - -2016-01-06 Joel Brobecker - - * hilo-hazard-4.s: Change copyright ownder to FSF. - -2015-09-25 Andrew Bennett - Ali Lown - - * basic.exp (run_micromips_test, run_sim_tests): New functions - Add support for micromips tests. - * hilo-hazard-4.s: New file. - * testutils.inc (_dowrite): Changed reserved instruction encoding. - (writemsg): Moved the la and li instructions before the data they are - assigned to, which prevents a bug where MIPS32 relocations are used - instead of micromips relocations when building for micromips. - -2015-04-13 Hans-Peter Nilsson - - * basic.exp: Don't unset target ldscript here. - -2011-01-06 Hans-Peter Nilsson - - * testutils.inc: Correct comment syntax fallout from - copyright update. - * utils-dsp.inc, utils-fpu.inc, utils-mdmx.inc: Ditto. - - * mips32-dsp.s: Update copyright year. - -2010-04-26 Mike Frysinger - - * basic.exp: Delete sim target check. - -2007-08-27 Joel Brobecker - - * testutils.inc: Change license to GPL version 3. - * utils-dsp.inc: Change license to GPL version 3. - * utils-fpu.inc: Change license to GPL version 3. - * utils-mdmx.inc: Change license to GPL version 3. - -2007-02-20 Thiemo Seufer - Chao-Ying Fu - * basic.exp: Run the dsp2 test. - * utils-dsp.inc (dspckacc_astio, dspck_tsimm): New macro. - * mips32-dsp2.s: New test. - -2007-02-17 Thiemo Seufer - - * basic.exp: Add case for mips*-sde-elf*. - (mdmxmodels): Run mdmx tests only on mdmx capable configurations. - -2007-02-13 Thiemo Seufer - - * mips32-dsp.s: Run DSP testcase only for release 2 architecture. - -2007-02-13 Thiemo Seufer - - * mdmx-ob.s: Delete extraneous include. - -2006-11-08 Thiemo Seufer - - * basic.exp: Fix spelling in comment. Use canonical form of target - patterns. Run DSP test only for DSP-capable ISAs. Check also mips32r2 - and mips64r2 if supported by the target. - -2006-08-08 Chris Dearman - - * testutils.inc (setup): __start is also a valid start symbol. - -2006-05-15 Chao-ying Fu - - * mips32-dsp.s: Add some tests for shra_r.ph, shrav_r.ph, shra_r.w, - shrav_r.w. - -2005-12-14 Chao-ying Fu - - * basic.exp: Run the dsp test. - * utils-dsp.inc: New file. - * mips32-dsp.s: New test. - -2004-04-11 Chris Demetriou - - * utils-fpu.inc (enable_fpu, ckm_fp_cc): New macros. - (clrset_fp_cc): Fix mask used for upper 7 condition codes. - * utils-mdmx.inc: Include utils-fpu.inc. - (enable_mdmx): Use enable_fpu. - -2004-04-10 Chris Demetriou - - * utils-fpu.inc: New file. - * utils-mdmx.inc: New file. - * mdmx-ob.s: New file. - * mdmx-ob-sb1.s: New file. - * basic.exp: Run new mdmx-ob and mdmx-ob-sb1 tests. - -2004-04-10 Chris Demetriou - - * fpu64-ps-sb1.s: New file. - * basic.exp: Recognize mipsisa64sb1 targets, and run fpu64-ps-sb1.s - if appropriate. - -2004-04-10 Chris Demetriou - - * fpu64-ps.s: New file. - * basic.exp: Run fpu64-ps.s. - -2004-03-29 Richard Sandiford - - * hilo-hazard-[123].s: New files. - * basic.exp (run_hilo_test): New procedure. - (models): Only list models that are included in the configuration. - (submodels): New variable, set to submodels of the above. - (mips64vr-*-elf, mips64vrel-*-elf): New configuration stanza. - Run hilo-hazard-[123].s. - -2004-01-26 Chris Demetriou - - * basic.exp: New file. - * testutils.inc: New file. - * sanity.s: New file. diff --git a/sim/testsuite/mips/ChangeLog-2021 b/sim/testsuite/mips/ChangeLog-2021 new file mode 100644 index 0000000..b64f691 --- /dev/null +++ b/sim/testsuite/mips/ChangeLog-2021 @@ -0,0 +1,126 @@ +2021-04-08 Mike Frysinger + + * basic.exp (arch): Delete. + +2021-02-13 Mike Frysinger + + * basic.exp: Define arch. + +2016-01-06 Joel Brobecker + + * hilo-hazard-4.s: Change copyright ownder to FSF. + +2015-09-25 Andrew Bennett + Ali Lown + + * basic.exp (run_micromips_test, run_sim_tests): New functions + Add support for micromips tests. + * hilo-hazard-4.s: New file. + * testutils.inc (_dowrite): Changed reserved instruction encoding. + (writemsg): Moved the la and li instructions before the data they are + assigned to, which prevents a bug where MIPS32 relocations are used + instead of micromips relocations when building for micromips. + +2015-04-13 Hans-Peter Nilsson + + * basic.exp: Don't unset target ldscript here. + +2011-01-06 Hans-Peter Nilsson + + * testutils.inc: Correct comment syntax fallout from + copyright update. + * utils-dsp.inc, utils-fpu.inc, utils-mdmx.inc: Ditto. + + * mips32-dsp.s: Update copyright year. + +2010-04-26 Mike Frysinger + + * basic.exp: Delete sim target check. + +2007-08-27 Joel Brobecker + + * testutils.inc: Change license to GPL version 3. + * utils-dsp.inc: Change license to GPL version 3. + * utils-fpu.inc: Change license to GPL version 3. + * utils-mdmx.inc: Change license to GPL version 3. + +2007-02-20 Thiemo Seufer + Chao-Ying Fu + * basic.exp: Run the dsp2 test. + * utils-dsp.inc (dspckacc_astio, dspck_tsimm): New macro. + * mips32-dsp2.s: New test. + +2007-02-17 Thiemo Seufer + + * basic.exp: Add case for mips*-sde-elf*. + (mdmxmodels): Run mdmx tests only on mdmx capable configurations. + +2007-02-13 Thiemo Seufer + + * mips32-dsp.s: Run DSP testcase only for release 2 architecture. + +2007-02-13 Thiemo Seufer + + * mdmx-ob.s: Delete extraneous include. + +2006-11-08 Thiemo Seufer + + * basic.exp: Fix spelling in comment. Use canonical form of target + patterns. Run DSP test only for DSP-capable ISAs. Check also mips32r2 + and mips64r2 if supported by the target. + +2006-08-08 Chris Dearman + + * testutils.inc (setup): __start is also a valid start symbol. + +2006-05-15 Chao-ying Fu + + * mips32-dsp.s: Add some tests for shra_r.ph, shrav_r.ph, shra_r.w, + shrav_r.w. + +2005-12-14 Chao-ying Fu + + * basic.exp: Run the dsp test. + * utils-dsp.inc: New file. + * mips32-dsp.s: New test. + +2004-04-11 Chris Demetriou + + * utils-fpu.inc (enable_fpu, ckm_fp_cc): New macros. + (clrset_fp_cc): Fix mask used for upper 7 condition codes. + * utils-mdmx.inc: Include utils-fpu.inc. + (enable_mdmx): Use enable_fpu. + +2004-04-10 Chris Demetriou + + * utils-fpu.inc: New file. + * utils-mdmx.inc: New file. + * mdmx-ob.s: New file. + * mdmx-ob-sb1.s: New file. + * basic.exp: Run new mdmx-ob and mdmx-ob-sb1 tests. + +2004-04-10 Chris Demetriou + + * fpu64-ps-sb1.s: New file. + * basic.exp: Recognize mipsisa64sb1 targets, and run fpu64-ps-sb1.s + if appropriate. + +2004-04-10 Chris Demetriou + + * fpu64-ps.s: New file. + * basic.exp: Run fpu64-ps.s. + +2004-03-29 Richard Sandiford + + * hilo-hazard-[123].s: New files. + * basic.exp (run_hilo_test): New procedure. + (models): Only list models that are included in the configuration. + (submodels): New variable, set to submodels of the above. + (mips64vr-*-elf, mips64vrel-*-elf): New configuration stanza. + Run hilo-hazard-[123].s. + +2004-01-26 Chris Demetriou + + * basic.exp: New file. + * testutils.inc: New file. + * sanity.s: New file. diff --git a/sim/testsuite/mn10300/ChangeLog b/sim/testsuite/mn10300/ChangeLog deleted file mode 100644 index 4c94a66..0000000 --- a/sim/testsuite/mn10300/ChangeLog +++ /dev/null @@ -1,11 +0,0 @@ -2021-04-08 Mike Frysinger - - * allinsn.exp (arch): Delete. - -2021-02-13 Mike Frysinger - - * allinsn.exp: Define arch. - -2015-04-05 Mike Frysinger - - * pass.s, allinsn.exp, testutils.inc: New files. diff --git a/sim/testsuite/mn10300/ChangeLog-2021 b/sim/testsuite/mn10300/ChangeLog-2021 new file mode 100644 index 0000000..4c94a66 --- /dev/null +++ b/sim/testsuite/mn10300/ChangeLog-2021 @@ -0,0 +1,11 @@ +2021-04-08 Mike Frysinger + + * allinsn.exp (arch): Delete. + +2021-02-13 Mike Frysinger + + * allinsn.exp: Define arch. + +2015-04-05 Mike Frysinger + + * pass.s, allinsn.exp, testutils.inc: New files. diff --git a/sim/testsuite/moxie/ChangeLog b/sim/testsuite/moxie/ChangeLog deleted file mode 100644 index 4c94a66..0000000 --- a/sim/testsuite/moxie/ChangeLog +++ /dev/null @@ -1,11 +0,0 @@ -2021-04-08 Mike Frysinger - - * allinsn.exp (arch): Delete. - -2021-02-13 Mike Frysinger - - * allinsn.exp: Define arch. - -2015-04-05 Mike Frysinger - - * pass.s, allinsn.exp, testutils.inc: New files. diff --git a/sim/testsuite/moxie/ChangeLog-2021 b/sim/testsuite/moxie/ChangeLog-2021 new file mode 100644 index 0000000..4c94a66 --- /dev/null +++ b/sim/testsuite/moxie/ChangeLog-2021 @@ -0,0 +1,11 @@ +2021-04-08 Mike Frysinger + + * allinsn.exp (arch): Delete. + +2021-02-13 Mike Frysinger + + * allinsn.exp: Define arch. + +2015-04-05 Mike Frysinger + + * pass.s, allinsn.exp, testutils.inc: New files. diff --git a/sim/testsuite/msp430/ChangeLog b/sim/testsuite/msp430/ChangeLog deleted file mode 100644 index ebb42c5..0000000 --- a/sim/testsuite/msp430/ChangeLog +++ /dev/null @@ -1,25 +0,0 @@ -2021-04-08 Mike Frysinger - - * allinsn.exp (arch): Delete. - -2021-02-13 Mike Frysinger - - * allinsn.exp: Define arch. - -2020-08-05 Jozef Lawrynowicz - - * mpyull_hwmult.s: New test. - -2020-01-22 Jozef Lawrynowicz - - * rrux.s: New test. - -2016-01-05 Nick Clifton - - * testutils.inc (__pass): Use the LMA addresses of the _passmsg - symbol. - (__fail): Likewise. - -2014-03-10 Mike Frysinger - - * add.s, allinsn.exp, testutils.inc: New files. diff --git a/sim/testsuite/msp430/ChangeLog-2021 b/sim/testsuite/msp430/ChangeLog-2021 new file mode 100644 index 0000000..ebb42c5 --- /dev/null +++ b/sim/testsuite/msp430/ChangeLog-2021 @@ -0,0 +1,25 @@ +2021-04-08 Mike Frysinger + + * allinsn.exp (arch): Delete. + +2021-02-13 Mike Frysinger + + * allinsn.exp: Define arch. + +2020-08-05 Jozef Lawrynowicz + + * mpyull_hwmult.s: New test. + +2020-01-22 Jozef Lawrynowicz + + * rrux.s: New test. + +2016-01-05 Nick Clifton + + * testutils.inc (__pass): Use the LMA addresses of the _passmsg + symbol. + (__fail): Likewise. + +2014-03-10 Mike Frysinger + + * add.s, allinsn.exp, testutils.inc: New files. diff --git a/sim/testsuite/or1k/ChangeLog b/sim/testsuite/or1k/ChangeLog deleted file mode 100644 index b105c0f..0000000 --- a/sim/testsuite/or1k/ChangeLog +++ /dev/null @@ -1,54 +0,0 @@ -2021-04-08 Mike Frysinger - - * alltests.exp (arch): Delete. - -2021-02-13 Mike Frysinger - - * alltests.exp: Define arch. - -2019-06-13 Stafford Horne - - * fpu-unordered.S: New file. - * fpu64a32-unordered.S: New file. - -2019-06-13 Stafford Horne - - * adrp.S: New file. - -2019-06-13 Stafford Horne - - * fpu64a32.S: New file. - -2018-10-05 Stafford Horne - - * div.S: Fix tests to match correct overflow/carry semantics. - * mul.S: Likewise. - -2017-12-12 Peter Gavin - Stafford Horne - - * add.S: New file. - * alltests.exp: New file. - * and.S: New file. - * basic.S: New file. - * div.S: New file. - * ext.S: New file. - * find.S: New file. - * flag.S: New file. - * fpu.S: New file. - * jump.S: New file. - * load.S: New file. - * mac.S: New file. - * mfspr.S: New file. - * mul.S: New file. - * or.S: New file. - * or1k-asm-test-env.h: New file. - * or1k-asm-test-helpers.h: New file. - * or1k-asm-test.h: New file. - * or1k-asm.h: New file. - * or1k-test.ld: New file. - * ror.S: New file. - * shift.S: New file. - * spr-defs.h: New file. - * sub.S: New file. - * xor.S: New file. diff --git a/sim/testsuite/or1k/ChangeLog-2021 b/sim/testsuite/or1k/ChangeLog-2021 new file mode 100644 index 0000000..b105c0f --- /dev/null +++ b/sim/testsuite/or1k/ChangeLog-2021 @@ -0,0 +1,54 @@ +2021-04-08 Mike Frysinger + + * alltests.exp (arch): Delete. + +2021-02-13 Mike Frysinger + + * alltests.exp: Define arch. + +2019-06-13 Stafford Horne + + * fpu-unordered.S: New file. + * fpu64a32-unordered.S: New file. + +2019-06-13 Stafford Horne + + * adrp.S: New file. + +2019-06-13 Stafford Horne + + * fpu64a32.S: New file. + +2018-10-05 Stafford Horne + + * div.S: Fix tests to match correct overflow/carry semantics. + * mul.S: Likewise. + +2017-12-12 Peter Gavin + Stafford Horne + + * add.S: New file. + * alltests.exp: New file. + * and.S: New file. + * basic.S: New file. + * div.S: New file. + * ext.S: New file. + * find.S: New file. + * flag.S: New file. + * fpu.S: New file. + * jump.S: New file. + * load.S: New file. + * mac.S: New file. + * mfspr.S: New file. + * mul.S: New file. + * or.S: New file. + * or1k-asm-test-env.h: New file. + * or1k-asm-test-helpers.h: New file. + * or1k-asm-test.h: New file. + * or1k-asm.h: New file. + * or1k-test.ld: New file. + * ror.S: New file. + * shift.S: New file. + * spr-defs.h: New file. + * sub.S: New file. + * xor.S: New file. diff --git a/sim/testsuite/pru/ChangeLog b/sim/testsuite/pru/ChangeLog deleted file mode 100644 index a10ff0b..0000000 --- a/sim/testsuite/pru/ChangeLog +++ /dev/null @@ -1,25 +0,0 @@ -2021-04-08 Mike Frysinger - - * allinsn.exp (arch): Delete. - -2021-02-13 Mike Frysinger - - * allinsn.exp: Define arch. - -2020-11-12 Dimitar Dimitrov - - * lmbd.s: New test. - -2019-09-23 Dimitar Dimitrov - - * add.s: New test. - * allinsn.exp: New file. - * dmem-zero-pass.s: New test. - * dmem-zero-trap.s: New test. - * dram.s: New test. - * jmp.s: New test. - * loop-imm.s: New test. - * loop-reg.s: New test. - * mul.s: New test. - * subreg.s: New test. - * testutils.inc: New file. diff --git a/sim/testsuite/pru/ChangeLog-2021 b/sim/testsuite/pru/ChangeLog-2021 new file mode 100644 index 0000000..a10ff0b --- /dev/null +++ b/sim/testsuite/pru/ChangeLog-2021 @@ -0,0 +1,25 @@ +2021-04-08 Mike Frysinger + + * allinsn.exp (arch): Delete. + +2021-02-13 Mike Frysinger + + * allinsn.exp: Define arch. + +2020-11-12 Dimitar Dimitrov + + * lmbd.s: New test. + +2019-09-23 Dimitar Dimitrov + + * add.s: New test. + * allinsn.exp: New file. + * dmem-zero-pass.s: New test. + * dmem-zero-trap.s: New test. + * dram.s: New test. + * jmp.s: New test. + * loop-imm.s: New test. + * loop-reg.s: New test. + * mul.s: New test. + * subreg.s: New test. + * testutils.inc: New file. diff --git a/sim/testsuite/riscv/ChangeLog b/sim/testsuite/riscv/ChangeLog deleted file mode 100644 index 9d7feba..0000000 --- a/sim/testsuite/riscv/ChangeLog +++ /dev/null @@ -1,11 +0,0 @@ -2021-04-08 Mike Frysinger - - * allinsn.exp (arch): Delete. - -2021-02-13 Mike Frysinger - - * allinsn.exp: Define arch. - -2021-02-04 Mike Frysinger - - * allinsn.exp, pass.s, testutils.inc: New files. diff --git a/sim/testsuite/riscv/ChangeLog-2021 b/sim/testsuite/riscv/ChangeLog-2021 new file mode 100644 index 0000000..9d7feba --- /dev/null +++ b/sim/testsuite/riscv/ChangeLog-2021 @@ -0,0 +1,11 @@ +2021-04-08 Mike Frysinger + + * allinsn.exp (arch): Delete. + +2021-02-13 Mike Frysinger + + * allinsn.exp: Define arch. + +2021-02-04 Mike Frysinger + + * allinsn.exp, pass.s, testutils.inc: New files. diff --git a/sim/testsuite/sh/ChangeLog b/sim/testsuite/sh/ChangeLog deleted file mode 100644 index 0e1f200..0000000 --- a/sim/testsuite/sh/ChangeLog +++ /dev/null @@ -1,85 +0,0 @@ -2021-04-08 Mike Frysinger - - * allinsn.exp (arch): Delete. - -2021-02-13 Mike Frysinger - - * allinsn.exp: Define arch. - -2004-09-13 DJ Delorie - - * sim/sh/allinsn.exp: Set global_as_options and - global_ld_options appropriately for little endian builds. - * sim/sh/movua.s: Support little endian. - -2004-09-08 Michael Snyder - - Commited by Corinna Vinschen - * allinsn.exp: Add new tests. - * bandor.s: New file. - * bandornot.s: New file. - * bclr.s: New file. - * bld.s: New file. - * bldnot.s: New file. - * bset.s: New file. - * bst.s: New file. - * bxor.s: New file. - * clip.s: New file. - * div.s: New file. - * fail.s: New file, make sure fail works. - * fsca.s: New file. - * fsrra.s: New file. - * mov.s: New file. - * mulr.s: New file. - * pass.s: New file, make sure pass works. - * pushpop.s: New file. - * resbank.s: New file. - * testutils.inc (bf8k, bt8k, assertmem): New macros. - -2004-02-12 Michael Snyder - - * and.s, movi.s, sett.s: New files. - * allinsn.exp: Add new tests. - * testutils.inc (set_sr_bit): Fix macro labels. - -2004-01-07 Michael Snyder - - * dmxy.s, fipr.s, fpchg.s, ldrc.s, loop.s, movli.s, movua.s, - movxy.s, pabs.s, pclr.s, prnd.s, psub.s, pswap.s: New files. - * allinsn.exp: Add new tests. - * testutils.inc (set_sr_bit): Add argument. - (set_greg): Add .align directives. - -2003-08-11 Michael Snyder - - * macl.s: New file. - * macw.s: New file. - * allinsn.exp: Add new tests for mac.w and mac.l. - -2003-07-25 Michael Snyder - - * pshai.s, pshar.s, pshli.s, pshlr.s: New files. - * allinsn.exp: Add psha, pshl tests. - * pdec.s, pinc.s, padd.s, paddc.s: New files. - * allinsn.exp: Add pdec, pinc, padd, paddc tests. - * pand.s, pdmsb.s: New files. - * allinsn.exp: Add pand, pdmsb tests. - -2003-07-23 Michael Snyder - - * pmuls.s: New file. - -2003-07-08 Michael Snyder - - * allinsn.exp, testutils.inc, add.s, fabs.s, fadd.s, fcmpeq.s, - fcmpgt.s, fcnvds.s, fcnvsd.s, fdiv.s, fldi0.s, fldi1.s, flds.s, - float.s, fmac.s, fmov.s, fmul.s, fneg.s, frchg.s, fschg.s, - fsqrt.s, fsub.s, ftrc.s, shll16.s, shll2.s, shll8.s, shll.s, - shlr16.s, shlr2.s, shlr8.s, shlr.s, swap.s: New files. - -Local Variables: -mode: change-log -left-margin: 8 -fill-column: 74 -version-control: never -End: diff --git a/sim/testsuite/sh/ChangeLog-2021 b/sim/testsuite/sh/ChangeLog-2021 new file mode 100644 index 0000000..0e1f200 --- /dev/null +++ b/sim/testsuite/sh/ChangeLog-2021 @@ -0,0 +1,85 @@ +2021-04-08 Mike Frysinger + + * allinsn.exp (arch): Delete. + +2021-02-13 Mike Frysinger + + * allinsn.exp: Define arch. + +2004-09-13 DJ Delorie + + * sim/sh/allinsn.exp: Set global_as_options and + global_ld_options appropriately for little endian builds. + * sim/sh/movua.s: Support little endian. + +2004-09-08 Michael Snyder + + Commited by Corinna Vinschen + * allinsn.exp: Add new tests. + * bandor.s: New file. + * bandornot.s: New file. + * bclr.s: New file. + * bld.s: New file. + * bldnot.s: New file. + * bset.s: New file. + * bst.s: New file. + * bxor.s: New file. + * clip.s: New file. + * div.s: New file. + * fail.s: New file, make sure fail works. + * fsca.s: New file. + * fsrra.s: New file. + * mov.s: New file. + * mulr.s: New file. + * pass.s: New file, make sure pass works. + * pushpop.s: New file. + * resbank.s: New file. + * testutils.inc (bf8k, bt8k, assertmem): New macros. + +2004-02-12 Michael Snyder + + * and.s, movi.s, sett.s: New files. + * allinsn.exp: Add new tests. + * testutils.inc (set_sr_bit): Fix macro labels. + +2004-01-07 Michael Snyder + + * dmxy.s, fipr.s, fpchg.s, ldrc.s, loop.s, movli.s, movua.s, + movxy.s, pabs.s, pclr.s, prnd.s, psub.s, pswap.s: New files. + * allinsn.exp: Add new tests. + * testutils.inc (set_sr_bit): Add argument. + (set_greg): Add .align directives. + +2003-08-11 Michael Snyder + + * macl.s: New file. + * macw.s: New file. + * allinsn.exp: Add new tests for mac.w and mac.l. + +2003-07-25 Michael Snyder + + * pshai.s, pshar.s, pshli.s, pshlr.s: New files. + * allinsn.exp: Add psha, pshl tests. + * pdec.s, pinc.s, padd.s, paddc.s: New files. + * allinsn.exp: Add pdec, pinc, padd, paddc tests. + * pand.s, pdmsb.s: New files. + * allinsn.exp: Add pand, pdmsb tests. + +2003-07-23 Michael Snyder + + * pmuls.s: New file. + +2003-07-08 Michael Snyder + + * allinsn.exp, testutils.inc, add.s, fabs.s, fadd.s, fcmpeq.s, + fcmpgt.s, fcnvds.s, fcnvsd.s, fdiv.s, fldi0.s, fldi1.s, flds.s, + float.s, fmac.s, fmov.s, fmul.s, fneg.s, frchg.s, fschg.s, + fsqrt.s, fsub.s, ftrc.s, shll16.s, shll2.s, shll8.s, shll.s, + shlr16.s, shlr2.s, shlr8.s, shlr.s, swap.s: New files. + +Local Variables: +mode: change-log +left-margin: 8 +fill-column: 74 +version-control: never +End: diff --git a/sim/testsuite/v850/ChangeLog b/sim/testsuite/v850/ChangeLog deleted file mode 100644 index 5e9ddbe..0000000 --- a/sim/testsuite/v850/ChangeLog +++ /dev/null @@ -1,27 +0,0 @@ -2021-04-08 Mike Frysinger - - * allinsns.exp (arch): Delete. - -2021-02-13 Mike Frysinger - - * allinsns.exp: Define arch. - -2008-02-05 DJ Delorie - - * .: New directory. - * allinsns.exp: New. - * bsh.cgs: New. - * div.cgs: New. - * divh.cgs: New. - * divh_3.cgs: New. - * divhu.cgs: New. - * divu.cgs: New. - * sar.cgs: New. - * satadd.cgs: New. - * satsub.cgs: New. - * satsubi.cgs: New. - * satsubr.cgs: New. - * shl.cgs: New. - * shr.cgs: New. - * testutils.cgs: New. - * testutils.inc: New. diff --git a/sim/testsuite/v850/ChangeLog-2021 b/sim/testsuite/v850/ChangeLog-2021 new file mode 100644 index 0000000..5e9ddbe --- /dev/null +++ b/sim/testsuite/v850/ChangeLog-2021 @@ -0,0 +1,27 @@ +2021-04-08 Mike Frysinger + + * allinsns.exp (arch): Delete. + +2021-02-13 Mike Frysinger + + * allinsns.exp: Define arch. + +2008-02-05 DJ Delorie + + * .: New directory. + * allinsns.exp: New. + * bsh.cgs: New. + * div.cgs: New. + * divh.cgs: New. + * divh_3.cgs: New. + * divhu.cgs: New. + * divu.cgs: New. + * sar.cgs: New. + * satadd.cgs: New. + * satsub.cgs: New. + * satsubi.cgs: New. + * satsubr.cgs: New. + * shl.cgs: New. + * shr.cgs: New. + * testutils.cgs: New. + * testutils.inc: New. -- cgit v1.1